NAND08GW3D2AN6E

NAND08GW3D2AN6E Datasheet

NAND08GW3D2A NAND16GW3D2A

Part	Datasheet
NAND08GW3D2AN6E	NAND08GW3D2AN6E (pdf)

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NAND08GW3D2A NAND16GW3D2A 8-Gbit, 16-Gbit, 4224-byte page, multilevel cell, 3 V supply, multiplane, NAND flash memory Preliminary Data • High density multilevel cell MLC flash memory 8, 16 Gbits of memory array 256, 512 Mbits of spare area Cost-effective solutions for mass storage applications • NAND interface x8 bus width Multiplexed address/data • Supply voltage VDD = to V • Page size 4096 + 128 spare bytes • Block size 512K + 16K spare bytes • Multiplane architecture Array split into two independent planes All operations can be performed on both planes simultaneously • Memory cell array 4 K + 128 bytes x 128 pages x 2048 blocks 8-Gbit devices 4 K + 128 bytes x 128 pages x 4096 blocks 16-Gbit devices • Page read/program Random access 60 µs max Sequential access 25 ns min Page program operation time 800 µs typ • Multipage program time 2 pages 800 µs typ • Copy-back program Fast page copy • Fast block erase Block erase time ms typ TSOP48 12 x 20 mm N • Multiblock erase time 2 blocks ms typ • Status register • Electronic signature • Security features OTP area Serial number unique ID option • Chip enable ‘don’t care’ • Data protection Hardware program/erase locked during power transitions • Development tools Error correction code models Bad block management and wear leveling algorithm HW simulation models • Data integrity 10,000 program/erase cycles with ECC 10 years data retention • RoHS compliant packages available January 2009 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 1/64 Contents NAND08GW3D2A, NAND16GW3D2A Description 7 Memory array organization 11 Bad blocks 11 Signals descriptions 13 Inputs/outputs I/O0-I/O7 13 Address Latch Enable AL 13 Command Latch Enable CL 13 Chip Enable E 13 Read Enable R 13 Write Enable W 13 Write Protect WP 14 Ready/Busy RB 14 VDD supply voltage 14 VSS ground 14 Bus operations 15 Command input 15 Address input 15 Data input 15 Ordering information 62 4/64 NAND08GW3D2A, NAND16GW3D2A List of tables Table 5/64 List of figures NAND08GW3D2A, NAND16GW3D2A Figure Logic block diagram 8 Logic diagram 9 TSOP48 connections 10 Memory array organization 12 Random data output 19 Page program operation 20 Random data input during sequential data input 23 Block erase operation 24 Copy back program operation without readout of data 24 Copy back program operation with readout of data 25 Copy back program operation with random data input 25 Multiplane page read operation with random data output. 27 Multiplane page program operation 29 Multiplane erase operation 30 Multiplane copy back program operation 31 Multiplane copy back program operation with random data input. 32 Multiplane copy back operation sequence 33 Multiplane copy back operation flow 33 New multiplane copy back operation sequence 34 New multiplane copy back operation flow. 35 Page program with 2-Kbyte page compatibility 36 Copy back program with 2-Kbyte page compatibility 37 Copy back program with 2-Kbyte page compatibility and random data input 37 Data protection 41 Program enable waveform 42 Program disable waveform 42 Erase enable waveform 43 Erase disable waveform 43 Bad block management flowchart. 45 Garbage collection 45 Command latch AC waveforms 53 Address latch AC waveforms 53 Data input latch AC waveforms 54 Sequential data output after read AC waveforms 54 Read status register AC waveforms 55 Read electronic signature AC waveforms. 55 Page read operation AC waveforms 56 Page program AC waveforms. 57 Block erase AC waveforms. 58 Reset AC waveforms 58 Ready/Busy AC waveform 59 Ready/Busy load circuit 59 Resistor value versus waveform timings for Ready/Busy signal. 60 TSOP48 - 48 lead plastic thin small outline, 12 x 20 mm, package outline 61 6/64 NAND08GW3D2A, NAND16GW3D2A The NANDxxGW3D2A is a multilevel cell MLC device from the NAND flash 4224-byte page family of non-volatile flash memories. The NAND08GW3D2A and the NAND16GW3D2A have a density of 8 and 16 Gbits, respectively. The devices operate from a 3 V power supply. The address lines are multiplexed with the data input/output signals on a multiplexed x8 input/output bus. This interface reduces the pin count and makes it possible to migrate to other densities without changing the footprint. Each block can be programmed and erased up to 10,000 cycles with error correction code ECC on . The devices also have hardware security features a write protect pin is available to provide hardware protection against program and erase operations. The devices feature an open-drain, ready/busy output that identifies if the program/erase/ read P/E/R controller is currently active. The use of an open-drain output allows the ready/busy pins of several memories to be connected to a single pull-up resistor. The memory array is split into 2 planes. This multiplane architecture makes it possible to program 2 pages at a time one in each plane , to erase 2 blocks at a time one in each plane , or to read 2 pages at a time one in each plane dividing by two the average program, erase, and read times. The device has the Chip Enable ’don’t care’ feature, which allows the bus to be shared between more than one memory at the same time, as Chip Enable transition during the latency time do not stop the read operation. Program and erase operations can never be interrupted by Chip Enable transition. The devices come with two security features ● OTP one time programmable area, which is a restricted access area where sensitive data/code can be stored permanently. The access sequence and further details about this feature are subject to an NDA non disclosure agreement ● Serial number unique identifier option, which enables each device to be uniquely identified. It is subject to an NDA and is, therefore, not described in the datasheet. For more details about these security features, contact your nearest Numonyx sales office. The devices are available in TSOP48 12 x 20 mm package. and are shipped from the factory with block 0 always valid and the memory content bits, in valid blocks, erased to Refer to the list of available part numbers and to Table 24 Ordering information scheme for information on how to order these options. 7/64 NAND08GW3D2A, NAND16GW3D2A Table Device summary Density Bus width Page size Block size Timings Memory array Operating voltage VDD Random access time max Sequential access time min Page program Block erase typ Package NAND0 8GW3D 8 Gbits x8 4096+ 128 bytes 512K + 16K bytes 128 pages x 2048 blocks 60 µs 25 ns 800 µs TSOP48 NAND1 6GW3D 16 Gbits 4096+ 128 bytes 512K + 16K bytes 128 pages x 4096 blocks 60 µs 25 ns 800 µs TSOP48 Figure Logic block diagram Address register/counter X Decoder Command Ordering information 14 Ordering information NAND08GW3D2A, NAND16GW3D2A Note: Table Ordering information scheme Example: NAND16G W 3 D 2 A N 6 E Device type NAND flash memory Density 08G = 8 Gbits 16G = 16 Gbits Operating voltage W = VDD = to V Bus width 3 = x8 Family identifier D = 4 Kbyte-page MLC Device options 2 = Chip Enable ‘don't care’ enabled Product version A = first version Package N = TSOP48 12 x 20 mm Temperature range 6 = −40 to 85 °C Option E = RoHS compliant package, standard packing F = RoHS compliant package, tape and reel packing Devices are shipped from the factory with the memory content bits, in valid blocks, erased to For further information on any aspect of this device, please contact your nearest Numonyx sales office. 62/64 NAND08GW3D2A, NAND16GW3D2A Changes 14-May-2008 Initial release. 28-May-2008 Removed the NAND32GW3D4A root part number troughout the document. Modified Figure 12 Multiplane page read operation with random data output and Figure 37 Page read operation AC waveforms. Added Figure 10 Copy back program operation with readout of data , Section Figure Multiplane copy back program operation with random data input and Section Copy back program with 2-Kbyte page compatibility. Document reformatted. 09-Jul-2008 Modified density of spare area on page 1, Table 14 Electronic signature byte 5, Figure 12 Multiplane page read operation with random data output, Figure 15 Multiplane copy back program operation, Section VDD supply voltage, and Section Multiplane copy back program. Added Figure 16 Multiplane copy back program operation with random data input. 07-Aug-2008 Modified Section Multiplane copy back program. Added root part number NAND08GW3D2A, Figure 17 Multiplane copy back operation sequence, Figure 18 Multiplane copy back operation flow, Figure 19 New multiplane copy back operation Removed the temperature range 1= 0 to 70 °C from Table 18 Operating and AC measurement conditions and Table 24 Ordering information scheme. 05-Nov-2008 Modified Figure 12 Multiplane page read operation with random data output and Figure 37 Page read operation AC waveforms. 23-Jan-2009 Added security features on page 1 and in Section 1 Description. Modified Figure 22 Copy back program with 2-Kbyte page compatibility, Figure 41 Ready/Busy AC waveform, and Figure 43 Resistor value versus waveform timings for Ready/Busy signal. Removed references to ECOPACK packages throughout the document. 63/64 NAND08GW3D2A, NAND16GW3D2A Please Read Carefully INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. Numonyx may make changes to specifications and product descriptions at any time, without notice. Numonyx, B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Numonyx reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by visiting Numonyx's website at Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright 11/5/7, Numonyx, B.V., All Rights Reserved. 64/64

PDF Datasheet Preview

NAND08GW3D2A NAND16GW3D2A
8-Gbit, 16-Gbit, 4224-byte page, multilevel cell, 3 V supply, multiplane, NAND flash memory

Preliminary Data
• High density multilevel cell MLC flash memory 8, 16 Gbits of memory array 256, 512 Mbits of spare area Cost-effective solutions for mass storage applications
• NAND interface x8 bus width Multiplexed address/data
• Supply voltage VDD = to V
• Page size 4096 + 128 spare bytes
• Block size 512K + 16K spare bytes
• Multiplane architecture Array split into two independent planes All operations can be performed on both planes simultaneously
• Memory cell array 4 K + 128 bytes x 128 pages x 2048 blocks 8-Gbit devices 4 K + 128 bytes x 128 pages x 4096 blocks 16-Gbit devices
• Page read/program Random access 60 µs max Sequential access 25 ns min Page program operation time 800 µs typ
• Multipage program time 2 pages 800 µs typ
• Copy-back program Fast page copy
• Fast block erase Block erase time ms typ

TSOP48 12 x 20 mm N
• Multiblock erase time 2 blocks ms typ
• Status register
• Electronic signature
• Security features

OTP area Serial number unique ID option
• Chip enable ‘don’t care’
• Data protection Hardware program/erase locked during
power transitions
• Development tools

Error correction code models Bad block management and wear leveling
algorithm HW simulation models
• Data integrity 10,000 program/erase cycles with ECC 10 years data retention
• RoHS compliant packages available

January 2009

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
1/64

Contents

NAND08GW3D2A, NAND16GW3D2A

Description 7

Memory array organization 11

Bad blocks 11

Signals descriptions 13

Inputs/outputs I/O0-I/O7 13

Address Latch Enable AL 13

Command Latch Enable CL 13

Chip Enable E 13

Read Enable R 13

Write Enable W 13

Write Protect WP 14

Ready/Busy RB 14

VDD supply voltage 14 VSS ground 14

Bus operations 15

Command input 15

Address input 15

Data input 15
Ordering information 62
4/64

NAND08GW3D2A, NAND16GW3D2A

List of tables

Table
5/64

List of figures

NAND08GW3D2A, NAND16GW3D2A

Figure

Logic block diagram 8 Logic diagram 9 TSOP48 connections 10 Memory array organization 12 Random data output 19 Page program operation 20 Random data input during sequential data input 23 Block erase operation 24 Copy back program operation without readout of data 24 Copy back program operation with readout of data 25 Copy back program operation with random data input 25 Multiplane page read operation with random data output. 27 Multiplane page program operation 29 Multiplane erase operation 30 Multiplane copy back program operation 31 Multiplane copy back program operation with random data input. 32 Multiplane copy back operation sequence 33 Multiplane copy back operation flow 33 New multiplane copy back operation sequence 34 New multiplane copy back operation flow. 35 Page program with 2-Kbyte page compatibility 36 Copy back program with 2-Kbyte page compatibility 37 Copy back program with 2-Kbyte page compatibility and random data input 37 Data protection 41 Program enable waveform 42 Program disable waveform 42 Erase enable waveform 43 Erase disable waveform 43 Bad block management flowchart. 45 Garbage collection 45 Command latch AC waveforms 53 Address latch AC waveforms 53 Data input latch AC waveforms 54 Sequential data output after read AC waveforms 54 Read status register AC waveforms 55 Read electronic signature AC waveforms. 55 Page read operation AC waveforms 56 Page program AC waveforms. 57 Block erase AC waveforms. 58 Reset AC waveforms 58 Ready/Busy AC waveform 59 Ready/Busy load circuit 59 Resistor value versus waveform timings for Ready/Busy signal. 60 TSOP48 - 48 lead plastic thin small outline, 12 x 20 mm, package outline 61
6/64

NAND08GW3D2A, NAND16GW3D2A

The NANDxxGW3D2A is a multilevel cell MLC device from the NAND flash 4224-byte page family of non-volatile flash memories. The NAND08GW3D2A and the NAND16GW3D2A have a density of 8 and 16 Gbits, respectively. The devices operate from a 3 V power supply.

The address lines are multiplexed with the data input/output signals on a multiplexed x8 input/output bus. This interface reduces the pin count and makes it possible to migrate to other densities without changing the footprint.

Each block can be programmed and erased up to 10,000 cycles with error correction code ECC on . The devices also have hardware security features a write protect pin is available to provide hardware protection against program and erase operations.

The devices feature an open-drain, ready/busy output that identifies if the program/erase/ read P/E/R controller is currently active. The use of an open-drain output allows the ready/busy pins of several memories to be connected to a single pull-up resistor.

The memory array is split into 2 planes. This multiplane architecture makes it possible to program 2 pages at a time one in each plane , to erase 2 blocks at a time one in each plane , or to read 2 pages at a time one in each plane dividing by two the average program, erase, and read times.

The device has the Chip Enable ’don’t care’ feature, which allows the bus to be shared between more than one memory at the same time, as Chip Enable transition during the latency time do not stop the read operation. Program and erase operations can never be interrupted by Chip Enable transition.

The devices come with two security features ● OTP one time programmable area, which is a restricted access area where sensitive
data/code can be stored permanently. The access sequence and further details about this feature are subject to an NDA non disclosure agreement ● Serial number unique identifier option, which enables each device to be uniquely identified. It is subject to an NDA and is, therefore, not described in the datasheet.

For more details about these security features, contact your nearest Numonyx sales office.

The devices are available in TSOP48 12 x 20 mm package. and are shipped from the factory with block 0 always valid and the memory content bits, in valid blocks, erased to
Refer to the list of available part numbers and to Table 24 Ordering information scheme for information on how to order these options.
7/64

NAND08GW3D2A, NAND16GW3D2A

Table Device summary

Density

Bus width

Page size

Block size

Timings

Memory array

Operating voltage VDD

Random access
time max

Sequential access
time min

Page program

Block erase typ

Package

NAND0 8GW3D 8 Gbits x8
4096+ 128 bytes
512K + 16K bytes
128 pages x
2048 blocks
60 µs
25 ns
800 µs

TSOP48

NAND1 6GW3D
16 Gbits
4096+ 128 bytes
512K + 16K bytes
128 pages x
4096 blocks
60 µs
25 ns
800 µs

TSOP48

Figure Logic block diagram

Address register/counter

X Decoder

Command
Ordering information
14 Ordering information

NAND08GW3D2A, NAND16GW3D2A

Note:
Table Ordering information scheme

Example:

NAND16G W 3 D 2 A N 6 E

Device type NAND flash memory

Density 08G = 8 Gbits 16G = 16 Gbits

Operating voltage W = VDD = to V

Bus width 3 = x8

Family identifier D = 4 Kbyte-page MLC

Device options 2 = Chip Enable ‘don't care’ enabled

Product version A = first version

Package N = TSOP48 12 x 20 mm

Temperature range 6 = −40 to 85 °C

Option E = RoHS compliant package, standard packing F = RoHS compliant package, tape and reel packing

Devices are shipped from the factory with the memory content bits, in valid blocks, erased to For further information on any aspect of this device, please contact your nearest Numonyx sales office.
62/64

NAND08GW3D2A, NAND16GW3D2A

Changes
14-May-2008

Initial release.
28-May-2008

Removed the NAND32GW3D4A root part number troughout the
document.

Modified Figure 12 Multiplane page read operation with random
data output and Figure 37 Page read operation AC waveforms.

Added Figure 10 Copy back program operation with readout of
data , Section Figure Multiplane copy back program operation
with random data input and Section Copy back program with
2-Kbyte page compatibility.

Document reformatted.
09-Jul-2008

Modified density of spare area on page 1, Table 14 Electronic
signature byte 5, Figure 12 Multiplane page read operation with
random data output, Figure 15 Multiplane copy back program
operation, Section VDD supply voltage, and Section

Multiplane copy back program.

Added Figure 16 Multiplane copy back program operation with random data input.
07-Aug-2008

Modified Section Multiplane copy back program.

Added root part number NAND08GW3D2A, Figure 17 Multiplane
copy back operation sequence, Figure 18 Multiplane copy back
operation flow, Figure 19 New multiplane copy back operation
Removed the temperature range 1= 0 to 70 °C from Table 18 Operating and AC measurement conditions and Table 24 Ordering information scheme.
05-Nov-2008

Modified Figure 12 Multiplane page read operation with random data output and Figure 37 Page read operation AC waveforms.
23-Jan-2009

Added security features on page 1 and in Section 1 Description.

Modified Figure 22 Copy back program with 2-Kbyte page
compatibility, Figure 41 Ready/Busy AC waveform, and Figure 43 Resistor value versus waveform timings for Ready/Busy signal.

Removed references to ECOPACK packages throughout the document.
63/64

NAND08GW3D2A, NAND16GW3D2A

Please Read Carefully INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY

WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.

Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications.

Numonyx may make changes to specifications and product descriptions at any time, without notice. Numonyx, B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied,
by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Numonyx reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by
visiting Numonyx's website at Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries.
*Other names and brands may be claimed as the property of others. Copyright 11/5/7, Numonyx, B.V., All Rights Reserved.
64/64

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived NAND08GW3D2AN6E Datasheet file may be downloaded here without warranties.

Datasheet ID: NAND08GW3D2AN6E 648540