NAND02GW3B2DN6E

NAND02GW3B2DN6E Datasheet

NAND02G-BxD

Part	Datasheet
NAND02GW3B2DN6E	NAND02GW3B2DN6E (pdf)

Related Parts	Information
NAND02GR3B2DZA6E	NAND02GR3B2DZA6E
NAND02GW3B2DZA6E	NAND02GW3B2DZA6E

PDF Datasheet Preview
NAND02G-BxD 2-Gbit, 2112-byte/1056-word page multiplane architecture, V or 3 V, SLC NAND flash memories • High density NAND flash memory Up to 2 Gbits of memory array Cost-effective solution for mass storage applications • NAND interface x8 or x16 bus width Multiplexed address/data • Supply voltage V or 3 V device • Page size x8 device 2048 + 64 spare bytes x16 device 1024 + 32 spare words • Block size x8 device 128 K + 4 K spare bytes x16 device 64 K + 2 K spare words • Multiplane architecture Array split into two independent planes Program/erase operations can be performed on both planes at the same time • Page read/program Random access 25 µs max Sequential access 25 ns min Page program time 200 µs typ Multiplane page program time 2 pages 200 µs typ • Copy back program with automatic EDC error detection code • Cache read mode • Fast block erase Block erase time ms typ Multiblock erase time 2 blocks ms typ • Status register • Electronic signature TSOP48 12 x 20 mm N VFBGA63 VFBGA63 9 x 11 x mm ZA • Chip Enable ‘don’t care’ • Security features OTP area Serial number unique ID Non-volatile protection option • Data protection Hardware program/erase disabled during power transitions • ONFI compliant command set • Data integrity 100,000 program/erase cycles with ECC 10 years data retention • RoHS compliant packages Table Device summary Reference Root part number NAND02G-BxD NAND02GR3B2D NAND02GW3B2D NAND02GR3BAD NAND02GR4B2D NAND02GW4B2D February 2010 1/67 Contents Contents NAND02G-BxD Description 7 Memory array organization 12 Signals description 14 Inputs/outputs I/O0-I/O7 14 Inputs/outputs I/O8-I/O15 14 Address Latch Enable AL 14 Command Latch Enable CL 14 Chip Enable E 14 Read Enable R 14 Ordering information 65 4/67 NAND02G-BxD List of tables List of tables Table 5/67 List of figures List of figures NAND02G-BxD Figure Logic block diagram 8 Logic diagram 9 TSOP48 connections 10 VFBGA63 connections top view through package 11 Memory array organization 13 Read operations 21 Random data output during sequential data output 22 Cache read sequential operation 23 Cache read random operation 23 Page program operation 25 Random data input during sequential data input 25 Multiplane page program waveform 27 Copy back program without readout of data 28 Copy back program with readout of data 28 Page copy back program with random data input 29 Multiplane copy back program 30 Block erase 31 Multiplane block erase 32 Page organization 33 Bad block management flowchart. 44 Garbage collection 45 Equivalent testing circuit for AC characteristics measurement 49 Command latch AC waveforms 52 Address latch AC waveforms 53 Data input latch AC waveforms 53 Sequential data output after read AC waveforms 54 Sequential data output after read AC waveforms EDO mode 54 Read status register or read EDC status register AC waveform. 55 Read status enhanced waveform 55 Read electronic signature AC waveform 56 Read ONFI signature waveform 56 Page read operation AC waveform. 57 Page program AC waveform 58 Block erase AC waveform 59 Reset AC waveform 59 Program/erase enable waveform 60 Program/erase disable waveform 60 Read parameter page waveform 60 Ready/busy AC waveform 61 Ready/busy load circuit. 61 Resistor value versus waveform timings for ready/busy signal 62 Data protection 62 TSOP48 - 48 lead plastic thin small outline, 12 x 20 mm, package outline 63 VFBGA63 9 x 11 x mm, mm pitch, package outline 64 6/67 NAND02G-BxD The NAND02G-BxD devices are part of the NAND flash 2112-byte/1056-word page family of non-volatile flash memories. They use NAND cell technology and have a density of 2 Gbits. These devices have a memory array that is split into 2 planes of 1024 blocks each. This multiplane architecture makes it possible to program 2 pages at a time one in each plane , or to erase 2 blocks at a time one in each plane . This feature reduces the average program and erase times by The NAND02G-BxD devices operate from a V or 3 V voltage supply. Depending on whether the device has a x8 or x16 bus width, the page size is 2112 bytes 2048 + 64 spare or 1056 words 1024 + 32 spare , respectively. The address lines are multiplexed with the data input/output signals on a multiplexed x8 input/output bus. This interface reduces the pin count and makes it possible to migrate to other densities without changing the footprint. Each block can be programmed and erased up to 100,000 cycles with ECC error correction code on. To extend the lifetime of NAND flash devices, the implementation of an ECC is mandatory. A write protect pin is available to provide hardware protection against program and erase operations. The devices feature an open-drain ready/busy output that identifies if the P/E/R program/erase/read controller is currently active. The use of an open-drain output allows the ready/busy pins from several memories to connect to a single pull-up resistor. A Copy Back Program command is available to optimize the management of defective blocks. When a page program operation fails, the data can be programmed in another page without having to resend the data to be programmed. An embedded error detection code EDC is automatically executed after each copy back operation 1 error bit can be detected for every 528 bytes. With this feature it is no longer necessary to use an external ECC to detect copy back operation errors. The devices have a cache read feature that improves the read throughput for large files. During cache reading, the device loads the data in a cache register while the previous data is transferred to the I/O buffers to be read. The devices have the Chip Enable ‘don’t care’ feature, which allows code to be directly downloaded by a microcontroller. This is possible because Chip Enable transitions during the latency time do not stop the read operation. The NAND02G-BxD devices support the ONFI specification. The devices are available in the following packages ● TSOP48 12 x 20 mm ● VFBGA63 9 x 11 x mm and come with three security features ● OTP one time programmable area, which is a restricted access area where sensitive data/code can be stored permanently. ● Serial number unique identifier , which allows the devices to be uniquely identified. ● Non-volatile protection to lock sensible data permanently. 7/67 NAND02G-BxD These security features are subject to an NDA non-disclosure agreement and are, therefore, not described in the datasheet. For more details about them, contact your nearest Numonyx sales office. For information on how to order these options, refer to Table 31 Ordering information scheme. Devices are shipped from the factory with block 0 always valid and the memory content bits, in valid blocks, erased to Table 2 Product description lists the part numbers and other information for all the devices in the family. Table Product description Density Bus width Page size Block size Timings Memory array Operating voltage Sequential access time min Random Page access Program time max typ Block Erase typ Package NAND02GR3B2D NAND02GR3BAD 2048+64 128 K+4 K bytes bytes NAND02GW3B2D 64 pages 2 Gbits x 2048 blocks NAND02GR4B2D 1024+ 64 K+2 K 32 words NAND02GW4B2D 45 ns 25 ns 45 ns 25 ns VFBGA63 25 µs 200 µs TSOP48 VFBGA63 Figure Logic block diagram Address Register/Counter X Decoder Command P/E/R Controller, Interface Logic High Voltage Generator Command Register 13 Ordering information Ordering information Note: Table Ordering information scheme Example: NAND02GW3B2D N 6 E Device type NAND flash memory Density 02G = 2 Gbits Operating voltage W = VDD = to V R = VDD = to V Bus width 3 = x8 4 = x16 Family identifier B = 2112-byte page Device options 2 = Chip Enable ‘don't care’ enabled A = Automotive testing Product version D = Fourth version Package N = TSOP48 12 x 20 mm ZA = VFBGA63 9 x 11 x mm, mm pitch Temperature range 6 = to 85 °C Option E = RoHS compliant package, standard packing F = RoHS compliant package, tape and reel packing Devices are shipped from the factory with the memory content bits, in valid blocks, erased to Not all combinations are necessarily available. For a list of available devices or for further information on any aspect of these products, please contact your nearest Numonyx sales office. 65/67 NAND02G-BxD Changes 07-Sep-2007 Initial release. 13-Feb-2008 03-Apr-2008 Document status promoted from target specification to preliminary data. Modified Figure 12 Multiplane page program waveform, Figure 16 Multiplane copy back program, Figure 18 Multiplane block erase, Figure 29 Read status enhanced waveform, Figure 36 Program/erase enable waveform, Figure 37: Program/erase disable waveform, Figure 41 Resistor value versus waveform timings for ready/busy signal, Section Multiplane page program, Section Error correction code, Table 8 Address definition x16 devices , Table 21 Program erase times and program erase endurance cycles, Table 23: Operating and AC measurement conditions. Minor text changes. Applied Numonyx branding. 24-Apr-2008 12-Sep-2008 VFBGA63 x 12 mm replaced by VFBGA63 9 x 11 x mm throughout the document. Minor text changes. Document status promoted from preliminary data to full datasheet. Removed note below Table 1 and Table 11-Mar-2009 16-Feb-2010 Modified silhouette for the VFBGA63 package on the cover page. Added NAND02GR3BAD root part number throughout the document, automotive testing option in Table 31 Ordering information scheme. 66/67 NAND02G-BxD Please Read Carefully INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. Numonyx may make changes to specifications and product descriptions at any time, without notice. Numonyx, B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Numonyx reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by visiting Numonyx's website at Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright 11/5/7, Numonyx, B.V., All Rights Reserved. 67/67

PDF Datasheet Preview

NAND02G-BxD
2-Gbit, 2112-byte/1056-word page multiplane architecture, V or 3 V, SLC NAND flash memories
• High density NAND flash memory Up to 2 Gbits of memory array Cost-effective solution for mass storage applications
• NAND interface x8 or x16 bus width Multiplexed address/data
• Supply voltage V or 3 V device
• Page size x8 device 2048 + 64 spare bytes x16 device 1024 + 32 spare words
• Block size x8 device 128 K + 4 K spare bytes x16 device 64 K + 2 K spare words
• Multiplane architecture Array split into two independent planes Program/erase operations can be performed on both planes at the same time
• Page read/program Random access 25 µs max Sequential access 25 ns min Page program time 200 µs typ Multiplane page program time 2 pages 200 µs typ
• Copy back program with automatic EDC error detection code
• Cache read mode
• Fast block erase Block erase time ms typ Multiblock erase time 2 blocks ms typ
• Status register
• Electronic signature

TSOP48 12 x 20 mm N

VFBGA63

VFBGA63 9 x 11 x mm ZA
• Chip Enable ‘don’t care’
• Security features

OTP area Serial number unique ID Non-volatile protection option
• Data protection Hardware program/erase disabled during
power transitions
• ONFI compliant command set
• Data integrity
100,000 program/erase cycles with ECC 10 years data retention
• RoHS compliant packages

Table Device summary

Reference

Root part number

NAND02G-BxD

NAND02GR3B2D NAND02GW3B2D NAND02GR3BAD NAND02GR4B2D

NAND02GW4B2D

February 2010
1/67

Contents

Contents

NAND02G-BxD

Description 7

Memory array organization 12

Signals description 14

Inputs/outputs I/O0-I/O7 14

Inputs/outputs I/O8-I/O15 14

Address Latch Enable AL 14

Command Latch Enable CL 14

Chip Enable E 14

Read Enable R 14
Ordering information 65
4/67

NAND02G-BxD

List of tables

List of tables

Table
5/67

List of figures

List of figures

NAND02G-BxD

Figure

Logic block diagram 8 Logic diagram 9 TSOP48 connections 10 VFBGA63 connections top view through package 11 Memory array organization 13 Read operations 21 Random data output during sequential data output 22 Cache read sequential operation 23 Cache read random operation 23 Page program operation 25 Random data input during sequential data input 25 Multiplane page program waveform 27 Copy back program without readout of data 28 Copy back program with readout of data 28 Page copy back program with random data input 29 Multiplane copy back program 30 Block erase 31 Multiplane block erase 32 Page organization 33 Bad block management flowchart. 44 Garbage collection 45 Equivalent testing circuit for AC characteristics measurement 49 Command latch AC waveforms 52 Address latch AC waveforms 53 Data input latch AC waveforms 53 Sequential data output after read AC waveforms 54 Sequential data output after read AC waveforms EDO mode 54 Read status register or read EDC status register AC waveform. 55 Read status enhanced waveform 55 Read electronic signature AC waveform 56 Read ONFI signature waveform 56 Page read operation AC waveform. 57 Page program AC waveform 58 Block erase AC waveform 59 Reset AC waveform 59 Program/erase enable waveform 60 Program/erase disable waveform 60 Read parameter page waveform 60 Ready/busy AC waveform 61 Ready/busy load circuit. 61 Resistor value versus waveform timings for ready/busy signal 62 Data protection 62 TSOP48 - 48 lead plastic thin small outline, 12 x 20 mm, package outline 63 VFBGA63 9 x 11 x mm, mm pitch, package outline 64
6/67

NAND02G-BxD

The NAND02G-BxD devices are part of the NAND flash 2112-byte/1056-word page family of non-volatile flash memories. They use NAND cell technology and have a density of 2 Gbits.

These devices have a memory array that is split into 2 planes of 1024 blocks each. This multiplane architecture makes it possible to program 2 pages at a time one in each plane , or to erase 2 blocks at a time one in each plane . This feature reduces the average program and erase times by

The NAND02G-BxD devices operate from a V or 3 V voltage supply. Depending on whether the device has a x8 or x16 bus width, the page size is 2112 bytes 2048 + 64 spare or 1056 words 1024 + 32 spare , respectively.

The address lines are multiplexed with the data input/output signals on a multiplexed x8 input/output bus. This interface reduces the pin count and makes it possible to migrate to other densities without changing the footprint.

Each block can be programmed and erased up to 100,000 cycles with ECC error correction code on. To extend the lifetime of NAND flash devices, the implementation of an ECC is mandatory.

A write protect pin is available to provide hardware protection against program and erase operations.

The devices feature an open-drain ready/busy output that identifies if the P/E/R program/erase/read controller is currently active. The use of an open-drain output allows the ready/busy pins from several memories to connect to a single pull-up resistor.

A Copy Back Program command is available to optimize the management of defective blocks. When a page program operation fails, the data can be programmed in another page without having to resend the data to be programmed. An embedded error detection code EDC is automatically executed after each copy back operation 1 error bit can be detected for every 528 bytes. With this feature it is no longer necessary to use an external ECC to detect copy back operation errors.

The devices have a cache read feature that improves the read throughput for large files. During cache reading, the device loads the data in a cache register while the previous data is transferred to the I/O buffers to be read.

The devices have the Chip Enable ‘don’t care’ feature, which allows code to be directly downloaded by a microcontroller. This is possible because Chip Enable transitions during the latency time do not stop the read operation.

The NAND02G-BxD devices support the ONFI specification.

The devices are available in the following packages ● TSOP48 12 x 20 mm ● VFBGA63 9 x 11 x mm
and come with three security features ● OTP one time programmable area, which is a restricted access area where sensitive
data/code can be stored permanently. ● Serial number unique identifier , which allows the devices to be uniquely identified. ● Non-volatile protection to lock sensible data permanently.
7/67

NAND02G-BxD

These security features are subject to an NDA non-disclosure agreement and are, therefore, not described in the datasheet. For more details about them, contact your nearest Numonyx sales office.
For information on how to order these options, refer to Table 31 Ordering information scheme. Devices are shipped from the factory with block 0 always valid and the memory content bits, in valid blocks, erased to

Table 2 Product description lists the part numbers and other information for all the devices in the family.

Table Product description

Density

Bus width

Page size

Block size

Timings

Memory array

Operating voltage

Sequential access
time min

Random Page access Program time max typ

Block Erase typ

Package

NAND02GR3B2D

NAND02GR3BAD
2048+64 128 K+4 K
bytes
bytes

NAND02GW3B2D
64 pages
2 Gbits
x 2048
blocks

NAND02GR4B2D
1024+ 64 K+2 K 32 words

NAND02GW4B2D
45 ns 25 ns 45 ns 25 ns

VFBGA63
25 µs
200 µs

TSOP48 VFBGA63

Figure Logic block diagram

Address Register/Counter

X Decoder

Command

P/E/R Controller,

Interface Logic

High Voltage Generator

Command Register
13 Ordering information
Ordering information

Note:
Table Ordering information scheme Example:

NAND02GW3B2D N 6 E

Device type NAND flash memory

Density 02G = 2 Gbits

Operating voltage W = VDD = to V R = VDD = to V

Bus width 3 = x8 4 = x16

Family identifier B = 2112-byte page

Device options 2 = Chip Enable ‘don't care’ enabled A = Automotive testing

Product version D = Fourth version

Package N = TSOP48 12 x 20 mm ZA = VFBGA63 9 x 11 x mm, mm pitch

Temperature range 6 = to 85 °C

Option E = RoHS compliant package, standard packing F = RoHS compliant package, tape and reel packing

Devices are shipped from the factory with the memory content bits, in valid blocks, erased to

Not all combinations are necessarily available. For a list of available devices or for further information on any aspect of these products, please contact your nearest Numonyx sales office.
65/67

NAND02G-BxD

Changes
07-Sep-2007

Initial release.
13-Feb-2008 03-Apr-2008

Document status promoted from target specification to
preliminary data.

Modified Figure 12 Multiplane page program waveform,

Figure 16 Multiplane copy back program, Figure 18 Multiplane
block erase, Figure 29 Read status enhanced waveform,

Figure 36 Program/erase enable waveform, Figure 37:

Program/erase disable waveform, Figure 41 Resistor value
versus waveform timings for ready/busy signal, Section

Multiplane page program, Section Error correction code,

Table 8 Address definition x16 devices , Table 21 Program
erase times and program erase endurance cycles, Table 23:

Operating and AC measurement conditions.

Minor text changes.

Applied Numonyx branding.
24-Apr-2008 12-Sep-2008

VFBGA63 x 12 mm replaced by VFBGA63 9 x 11 x mm
throughout the document.

Minor text changes.

Document status promoted from preliminary data to full datasheet. Removed note below Table 1 and Table
11-Mar-2009 16-Feb-2010

Modified silhouette for the VFBGA63 package on the cover page.
Added NAND02GR3BAD root part number throughout the document, automotive testing option in Table 31 Ordering information scheme.
66/67

NAND02G-BxD

Please Read Carefully INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY

WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.

Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications.

Numonyx may make changes to specifications and product descriptions at any time, without notice. Numonyx, B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied,
by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Numonyx reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by
visiting Numonyx's website at Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries.
*Other names and brands may be claimed as the property of others. Copyright 11/5/7, Numonyx, B.V., All Rights Reserved.
67/67

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived NAND02GW3B2DN6E Datasheet file may be downloaded here without warranties.

Datasheet ID: NAND02GW3B2DN6E 648538