N25Q128A31EF840E

N25Q128A31EF840E Datasheet

N25Q128

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N25Q128A31EF840E	N25Q128A31EF840E (pdf)

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N25Q128 128-Mbit, V, multiple I/O, 4-Kbyte subsector erase on boot sectors, XiP enabled, serial flash memory with 108 MHz SPI bus interface - SPI-compatible serial bus interface - 108 MHz maximum clock frequency - V to 2 V single supply voltage - Supports legacy SPI protocol and new Quad I/O or Dual I/O SPI protocol - Quad/Dual I/O instructions resulting in an equivalent clock frequency up to 432 MHz - XIP mode for all three protocols Configurable via volatile or non-volatile registers enabling the memory to work in XiP mode directly after power on - Program/Erase suspend instructions - Continuous read of entire memory via single instruction Fast Read Quad or Dual Output Fast Read Quad or Dual I/O Fast Read - Flexible to fit application Configurable number of dummy cycles Output buffer configurable Fast POR instruction to speed up power on phase Reset function available upon customer request - 64-byte user-lockable, one-time programmable OTP area - Erase capability Subsector 4-Kbyte granularity in the 8 boot sectors bottom or top parts . Sector 64-Kbyte granularity - Write protections Software write protection applicable to every 64-Kbyte sector volatile lock bit Hardware write protection protected area size defined by five non-volatile bits BP0, BP1, BP2, BP3 and TB bit VDFPN8 F8 8 x 6 mm MLP8 SO16 SF 300 mils width TBGA24 12 6 x 8 mm Additional smart protections available upon customer request - Deep Power-down mode 5 µA typical - Electronic signature JEDEC standard two-byte signature BB18h Additional 2 Extended Device ID EDID bytes to identify device factory options Unique ID code UID with 14 bytes readonly, available upon customer request - 100,000 + program/erase cycles per sector - More than 20 years data retention - Packages February 2010 1/185 Contents Contents N25Q128 - V Description 12 Signal descriptions 16 Serial data output DQ1 16 Serial data input DQ0 16 Serial Clock C 16 Chip Select S 16 Hold or Reset 17 Write protect/enhanced program supply voltage W/VPP , DQ2 18 VCC supply voltage 18 VSS ground 18 SPI Modes 19 SPI Protocols 21 Extended SPI protocol 21 Ordering information 182 7/185 List of tables List of tables N25Q128 - V Table Table 8/185 N25Q128 - V List of figures List of figures Figure Logic diagram 13 VDFPN8 connections 14 SO16 connections 14 BGA connections 15 Bus master and memory devices on the SPI bus 19 Extended SPI protocol example 20 Hold condition activation 25 Non Volatile and Volatile configuration Register Scheme 33 Block diagram 52 Read identification instruction and data-out sequence 80 Read Data Bytes instruction and data-out sequence 81 Read Data Bytes at Higher Speed instruction and data-out sequence 82 Dual Output Fast Read instruction sequence 83 Dual I/O Fast Read instruction sequence 84 Quad Input/Output Fast Read instruction sequence. 85 Quad Input/ Output Fast Read instruction sequence 86 Read OTP instruction and data-out sequence 87 Write Enable instruction sequence 88 Write Disable instruction sequence 89 Page Program instruction sequence. 91 Dual Input Fast Program instruction sequence. 92 Dual Input Extended Fast Program instruction sequence 93 Quad Input Fast Program instruction sequence 94 Quad Input Extended Fast Program instruction sequence 95 Program OTP instruction sequence 96 How to permanently lock the OTP bytes 97 Subsector Erase instruction sequence 98 Sector Erase instruction sequence 99 Bulk Erase instruction sequence 99 Read Status Register instruction sequence 102 Write Status Register instruction sequence 103 Read Lock Register instruction and data-out sequence 104 Write to Lock Register instruction sequence 105 Read Flag Status Register instruction sequence 106 Clear Flag Status Register instruction sequence 107 Read NV Configuration Register instruction sequence 107 Write NV Configuration Register instruction sequence. 108 Read Volatile Configuration Register instruction sequence 109 Write Volatile Configuration Register instruction sequence 110 Read Volatile Enhanced Configuration Register instruction sequence. 110 Write Volatile Enhanced Configuration Register instruction sequence. 111 Deep Power-down instruction sequence 112 Release from Deep Power-down instruction sequence 113 Multiple I/O Read Identification instruction and data-out sequence DIO-SPI 115 Dual Command Fast Read instruction and data-out sequence DIO-SPI 116 Read OTP instruction and data-out sequence DIO-SPI 117 Write Enable instruction sequence DIO-SPI 117 Write Disable instruction sequence DIO-SPI 118 9/185 List of figures N25Q128 - V Figure Dual Command Page Program instruction sequence DSP, 02h 118 Figure Dual Command Page Program instruction sequence DSP, A2h 119 Figure Dual Command Page Program instruction sequence DSP, D2h 119 Figure Program OTP instruction sequence DIO-SPI 120 Figure Subsector Erase instruction sequence DIO-SPI 120 Figure Sector Erase instruction sequence DIO-SPI. 121 Figure Bulk Erase instruction sequence DIO-SPI 122 Figure Program/Erase Suspend instruction sequence DIO-SPI 122 Figure Program/Erase Resume instruction sequence DIO-SPI 123 Figure Read Status Register instruction sequence DIO-SPI 124 Figure Write Status Register instruction sequence DIO-SPI 124 Figure Read Lock Register instruction and data-out sequence DIO-SPI. 125 Figure Write to Lock Register instruction sequence DIO-SPI 126 Figure Read Flag Status Register instruction sequence DIO-SPI 126 Figure Clear Flag Status Register instruction sequence DIO-SPI 127 Figure Read NV Configuration Register instruction sequence DIO-SPI 127 Figure Write NV Configuration Register instruction sequence DIO-SPI 128 Figure Read Volatile Configuration Register instruction sequence DIO-SPI 129 Figure Write Volatile Configuration Register instruction sequence DIO-SPI 129 Figure Read Volatile Enhanced Configuration Register instruction sequence DIO-SPI 130 Figure Write Volatile Enhanced Configuration Register instruction sequence DIO-SPI 131 Figure Deep Power-down instruction sequence 131 Figure Release from Deep Power-down instruction sequence 132 Figure Multiple I/O Read Identification instruction and data-out sequence QIO-SPI 135 Figure Quad Command Fast Read instruction and data-out sequence QSP, 0Bh 136 Figure Quad Command Fast Read instruction and data-out sequence QSP, 6Bh 136 Figure Quad Command Fast Read instruction and data-out sequence QSP, EBh 137 Figure Read OTP instruction and data-out sequence QIO-SPI 138 Figure Write Enable instruction sequence QIO-SPI. 138 Figure Write Disable instruction sequence QIO-SPI 139 Figure Quad Command Page Program instruction sequence QIO-SPI, 02h. 140 Figure Quad Command Page Program instruction sequence QIO-SPI, 12h. 140 Figure Quad Command Page Program instruction sequence QIO-SPI, 32h. 141 Figure Program OTP instruction sequence QIO-SPI 142 Figure Subsector Erase instruction sequence QIO-SPI. 143 Figure Sector Erase instruction sequence QIO-SPI 143 Figure Bulk Erase instruction sequence QIO-SPI 144 Figure Program/Erase Suspend instruction sequence QIO-SPI 145 Figure Program/Erase Resume instruction sequence QIO-SPI. 146 Figure Read Status Register instruction sequence QIO-SPI 147 Figure Write Status Register instruction sequence QIO-SPI 148 Figure Read Lock Register instruction and data-out sequence QIO-SPI 149 Figure Write to Lock Register instruction sequence QIO-SPI 150 Figure Read Flag Status Register instruction sequence QIO-SPI 151 Figure Clear Flag Status Register instruction sequence QIO-SPI 152 Figure Read NV Configuration Register instruction sequence QIO-SPI 153 Figure Write NV Configuration Register instruction sequence QIO-SPI 154 Figure Read Volatile Configuration Register instruction sequence QIO-SPI 155 Figure Write Volatile Configuration Register instruction sequence QIO-SPI 156 Figure Read Volatile Enhanced Configuration Register instruction sequence QIO-SPI 157 Figure Write Volatile Enhanced Configuration Register instruction sequence QIO-SPI 158 Figure Deep Power-down instruction sequence 159 10/185 N25Q128 - V List of figures Figure Deep Power-down instruction sequence 160 Figure N25Q128 Read functionality Flow Chart 162 Figure XIP mode directly after power on 163 Figure XiP enter by VCR 2/2 QIOFR in normal SPI protocol example 165 Figure Power-up timing, Fast POR selected 168 Figure Power-up timing, Fast POR not selected 168 Figure AC measurement I/O waveform 171 Figure Reset AC waveforms program or erase cycle is in progress 174 Figure Serial input timing 175 Figure Write protect setup and hold timing during WRSR when SRWD=1 176 Figure Hold timing 176 Figure Output timing 177 Figure VPPH timing 177 Figure VDFPN8 MLP8 8-lead very thin dual flat package no lead, 8 x 6 mm, package outline 178 Figure SO16 wide - 16-lead plastic small outline, 300 mils body width, package outline 179 Figure TBGA - 6 x 8 mm, 24-ball, mechanical package outline 180 11/185 N25Q128 - V The N25Q128 is a 128 Mbit 16Mb x 8 serial Flash memory, with advanced write protection mechanisms. It is accessed by a high speed SPI-compatible bus and features the possibility to work in XIP “eXecute in Place” mode. The N25Q128 supports innovative, high-performance quad/dual I/O instructions, these new instructions allow to double or quadruple the transfer bandwidth for read and program operations. Furthermore the memory can be operated with 3 different protocols - Standard SPI Extended SPI protocol - Dual I/O SPI - Quad I/O SPI The Standard SPI protocol is enriched by the new quad and dual instructions Extended SPI protocol . For Dual I/O SPI DIO-SPI all the instructions codes, the addresses and the data are always transmitted across two data lines. For Quad I/O SPI QIO-SPI the instructions codes, the addresses and the data are always transmitted across four data lines thus enabling a tremendous improvement in both random access time and data throughput. The memory can work in “XIP mode”, that means the device only requires the addresses and not the instructions to output the data. This mode dramatically reduces random access time thus enabling many applications requiring fast code execution without shadowing the memory content on a RAM. The XIP mode can be used with QIO-SPI, DIO-SPI, or Extended SPI protocol, and can be entered and exited using different dedicated instructions to allow maximum flexibility for applications required to enter in XIP mode right after power up of the device, this can be set as default mode by using dedicated Non Volatile Register NVR bits. It is also possible to reduce the power on sequence time with the Fast POR Power on Reset feature, enabling a reduction of the latency time before the first read instruction can be performed. Another feature is the ability to pause and resume program and erase cycles by using dedicated Program/Erase Suspend and Resume instructions. The N25Q128 memory offers the following additional Features to be configured by using the Non Volatile Configuration Register NVCR for default /Non-Volatile settings or by using the Volatile and Volatile Enhanced Configuration Registers for Volatile settings - the number of dummy cycles for fast read instructions single, dual and, quad I/O according to the operating frequency - the output buffer impedance - the type of SPI protocol extended SPI, DIO-SPI or QIO-SPI - the required XIP mode - Fast or standard POR sequence - the Hold Reset functionality enabling/disabling The memory is organized as 248 64-Kbyte main sectors, in products with Bottom or Top architecture there are 8 64-Kbyte boot sectors, and each boot sector is further divided into 16 4-Kbyte subsectors 128 subsectors in total . The boot sectors can be erased a 4-Kbyte subsector at a time or as a 64-Kbyte sector at a time. The entire memory can be also erased at a time or by sector. 12/185 N25Q128 - V The memory can be write protected by software using a mix of volatile and non-volatile protection features, depending on the application needs. The protection granularity is of 64Kbyte sector granularity for volatile protections. Many different N25Q128 configurations are available, please refer to the ordering scheme page for the possibilities. Additional features are available as security options The Security features are described in a dedicated Application Note . Please contact your nearest Numonyx Sales office for more information. Figure Logic diagram W/VPP/DQ2 HOLD/DQ3 Note: Logic_Diagram_x25x Reset functionality is available in devices with a dedicated part number. See Section 16 Ordering information. Table Signal names Signal C DQ0 DQ1 Serial Clock Serial Data input Serial Data output Input I/O 1 I/O 2 S W/VPP/DQ2 HOLD/DQ3 4 Chip Select Write Protect/Enhanced Program supply voltage/additional data I/O Hold Reset function available upon customer request /additional data I/O Input I/O 3 I/O 3 Supply voltage Ground Provides dual and quad I/O for Extended SPI protocol instructions, dual I/O for Dual I/O SPI protocol instructions, and quad I/O for Quad I/O SPI protocol instructions. Provides dual and quad instruction input for Extended SPI protocol, dual instruction input for Dual I/O SPI protocol, and quad instruction input for Quad I/O SPI protocol. Provides quad I/O for Extended SPI protocol instructions, and quad I/O for Quad I/O SPI protocol instructions. Reset functionality available with a dedicated part number. See Section 16 Ordering information. 13/185 N25Q128 - V Note: There is an exposed central pad on the underside of the VDFPN8 package. This is pulled, internally, to VSS, and must not be connected to any other voltage or signal line on the PCB. Figure VDFPN8 connections DQ1 2 W/V /DQ2 PP VSS 4 8 VCC 7 HOLD/DQ3 6C 5 DQ0 AI13720c Reset functionality available in devices with a dedicated part number. See Section 16 Ordering information. Figure SO16 connections HOLD/DQ3 1 VCC 2 DU 3 DU 4 DU 5 DU 6 S7 DQ1 8 16 C 15 DQ0 14 DU 13 DU 12 DU 11 DU 10 VSS 9 W/V /DQ2 PP DU = don’t use. AI13721c See Package mechanical section for package dimensions, and how to identify pin-1. Reset functionality available in devices with a dedicated part number. See Section 16 Ordering information. 14/185 N25Q128 - V Figure BGA connections W/VPP/DQ2 DQ1 DQ0 HOLD/DQ3 NC = No Connect. See Figure TBGA - 6 x 8 mm, 24-ball, mechanical package outline. 15/185 Signal descriptions Signal descriptions N25Q128 - V Serial data output DQ1 This output signal is used to transfer data serially out of the device. Data are shifted out on the falling edge of Serial Clock C . When used as an Input, It is latched on the rising edge of the Serial Clock C . In the Extended SPI protocol, during the Quad and Dual Input Fast Program QIFP, DIFP instructions and during the Quad and Dual Input Extended Fast Program QIEFP, DIEFP instructions, pin DQ1 is used also as an input. In the Dual I/O SPI protocol DIO-SPI the DQ1 pin always acts as an input/output. In the Quad I/O SPI protocol QIO-SPI the DQ1 pin always acts as an input/output, with the exception of the Program or Erase cycle performed with the Enhanced Program Supply Voltage VPP . In this case the device temporarily goes in Extended SPI protocol. The protocol then becomes QIO-SPI as soon as the VPP pin voltage goes low. Serial data input DQ0 This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data to be programmed. Values are latched on the rising edge of Serial Clock C . Data are shifted out on the falling edge of the Serial Clock C . In the Extended SPI protocol, during the Quad and Dual Output Fast Read QOFR, DOFR and the Quad and Dual Input/Output Fast Read QIOFR, DIOFR instructions, pin DQ0 is also used as an input/output. In the DIO-SPI protocol the DQ0 pin always acts as an input/output. In the QIO-SPI protocol, the DQ0 pin always acts as an input/output, with the exception of the Program or Erase cycle performed with the VPP. In this case the device temporarily goes in Extended SPI protocol. Then, the protocol returns to QIO-SPI as soon as the VPP pin voltage goes low. Serial Clock C This input signal provides the timing for the serial interface. Instructions, addresses, or data present at serial data input DQ0 are latched on the rising edge of Serial Clock C . Data are shifted out on the falling edge of the Serial Clock C . Chip Select S When this input signal is high, the device is deselected and serial data output DQ1 is at high impedance. Unless an internal program, erase or write status register cycle is in progress, the device will be in the standby power mode this is not the deep power-down mode . Driving Chip Select S low enables the device, placing it in the active power mode. After power-up, a falling edge on Chip Select S is required prior to the start of any instruction. 16/185 N25Q128 - V Signal descriptions Hold or Reset The Hold signal is used to pause any serial communications with the device without deselecting the device. Reset functionality is present instead of Hold in devices with a dedicated part number. See Section 16 Ordering information. During Hold condition, the Serial Data output DQ1 is in high impedance, and Serial Data input DQ0 and Serial Clock C are Don't Care. To start the Hold condition, the device must be selected, with Chip Select S driven Low. For devices featuring Reset instead of Hold functionality, the Reset input provides a hardware reset for the memory. When Reset is driven High, the memory is in the normal operating mode. When Reset is driven Low, the memory will enter the Reset mode. In this mode, the output is high impedance. Driving Reset Low while an internal operation is in progress will affect this operation write, program or erase cycle and data may be lost. In the Extended SPI protocol, during the QOFR, QIOFR, QIFP and the Quad Extended Fast Program QIEFP instructions, the Hold Reset / DQ3 is used as an input/output DQ3 functionality . In QIO-SPI, the Hold Reset / DQ3 pin acts as an I/O DQ3 functionality , and the HOLD Reset functionality disabled when the device is selected. When the device is deselected S signal is high , in parts with Reset functionality, it is possible to reset the device unless this functionality is not disabled by mean of dedicated registers bits. The HOLD Reset functionality can be disabled using bit 3 of the NVCR or bit 4 of the VECR. 17/185 Signal descriptions N25Q128 - V Write protect/enhanced program supply voltage W/VPP , W/VPP/DQ2 can be used as - A protection control input. - A power supply pin. - I/O in Extended SPI protocol quad instructions and in QIO-SPI protocol instructions. When the device is operated in Extended SPI protocol with single or dual instructions, the two functions W or VPP are selected by the voltage range applied to the pin. If the W/VPP input is kept in a low voltage range 0 V to VCC the pin is seen as a control input. This input signal is used to freeze the size of the area of memory that is protected against program or erase instructions as specified by the values in the BP[0:3] bits of the Status Register. See Table Status register format . If VPP is in the range of VPPH, it acts as an additional power supply during the Program or Erase cycles See Table Operating conditions . In this case VPP must be stable until the Program or Erase algorithm is completed. During the Extended SPI protocol, the QOFR and QIOFR instructions, and the QIO-SPI protocol instructions, the pin W/VPP/DQ2 is used as an input/output DQ2 functionality . Using the Extended SPI protocol the QIFP, QIEFP and the QIO-SPI Program/Erase instructions, it is still possible to use the VPP additional power supply to speed up internal operations. However, to enable this possibility it is necessary to set bit 3 of the Volatile Enhanced Configuration Register to In this case the W/VPP/DQ2 pin is used as an I/O pin until the end of the instruction sequence. After the last input data is shifted in, the application should apply VPP voltage to W/VPP/DQ2 within 200 ms to speed up the internal operations. If the VPP voltage is not applied within 200 ms the Program/Erase operations start with standard speed. The default value of the VECR bit 3 is 1, and the VPP functionality for Quad I/O modify instruction is disabled. VCC supply voltage VCC is the supply voltage. VSS ground VSS is the reference for the VCC supply voltage. 18/185 N25Q128 - V SPI Modes SPI Modes These devices can be driven by a micro controller with its SPI peripheral running in either of the two following modes CPOL=0, CPHA=0 CPOL=1, CPHA=1 For these two modes, input data is latched in on the rising edge of Serial Clock C , and output data is available from the falling edge of Serial Clock C . The difference between the two modes, as shown in Figure 5, is the clock polarity when the bus master is in standby mode and not transferring data C remains at 0 for CPOL=0, CPHA=0 C remains at 1 for CPOL=1, CPHA=1 Figure Bus master and memory devices on the SPI bus SPI interface with CPOL, CPHA = 0, 0 or 1, 1 SDO SDI SCK SPI Bus Master VSS VCC DQ1 DQ0 DQ1 DQ0 DQ1 DQ0 CS3 CS2 CS1 SPI memory R device the 8 boot sectors at the bottom or top addressable area of a device with a dedicated part number See Section 16 Ordering information - a sector at a time, using the sector erase SE instruction - throughout the entire memory, using the bulk erase BE instruction. This starts an internal erase cycle of duration tSSE, tSE or tBE . The erase instruction must be preceded by a write enable WREN instruction. Polling during a write, program or erase cycle A further improvement in the time to Write Status Register WRSR , POTP, PP, DIFP,DIEFP,QIFP, QIEFP or Erase SSE, SE or BE can be achieved by not waiting for the worst case delay tW, tPP, tSSE, tSE, or tBE . The application program can monitor if the required internal operation is completed, by polling the dedicated register bits to establish when the previous Write, Program or Erase cycle is complete. The information on the memory being in progress for a Program, Erase, or Write instruction can be checked either on the Write In Progress WIP bit of the Status Register or in the Program/Erase Controller bit of the Flag Status Register. The Program/Erase Controller bit is the opposite state of the WIP bit in the Status Register. In the Flag Status Register additional information can be checked, as eventual Program/Erase failures by mean of the Program or erase Error bits. Active power and standby power modes When Chip Select S is Low, the device is selected, and in the active power mode. 24/185 N25Q128 - V Operating features When Chip Select S is High, the device is deselected, but could remain in the active power mode until all internal cycles have completed program, erase, write status register . The device then goes in to the standby power mode. The device consumption drops to ICC1. Hold or Reset condition The Hold signal is used to pause serial communications with the device without resetting the clocking sequence. However, taking this signal Low does not terminate any write status register, program or erase cycle that is currently in progress. To enter the hold condition, the device must be selected, with Chip Select S Low. The hold condition starts on the falling edge of the Hold signal, provided that the Serial Clock C is Low as shown in Figure The hold condition ends on the rising edge of the Hold signal, provided that the Serial Clock C is Low. If the falling edge does not coincide with Serial Clock C being Low, the hold condition starts after Serial Clock C next goes Low. Similarly, if the rising edge does not coincide with Serial Clock C being Low, the hold condition ends after Serial Clock C next goes Low this is shown in Figure During the hold condition, the serial data output DQ1 is high impedance, and serial data input DQ0 and Serial Clock C are don’t care. Normally, the device is kept selected, with Chip Select S driven Low for the whole duration of the hold condition. This is to ensure that the state of the internal logic remains unchanged from the moment of entering the hold condition. If Chip Select S goes High while the device is in the Hold condition, this has the effect of resetting the internal logic of the device. To restart communication with the device, it is necessary to drive Hold High, and then to drive Chip Select S Low. This prevents the device from going back to the hold condition. Figure Hold condition activation HOLD Hold condition standard use Hold condition non-standard use AI02029D Reset functionality is available instead of Hold in parts with a dedicated part number. See Section 16 Ordering information. Driving Reset Low while an internal operation is in progress will affect this operation write, program or erase cycle and data may be lost. On Reset going Low, the device enters the reset mode and a time of tRHSL is then required before the device can be reselected by driving Chip Select S Low. For the value of tRHSL, see Table AC Characteristics. All the lock bits are reset to 0 after a Reset Low pulse. 25/185 Operating features N25Q128 - V Table Device Status after Reset Low Pulse Conditions reset pulse occurred Lock bits status Internal logic status Addressed data While decoding an instruction 1 WREN, WRDI, RDID, RDSR, READ, RDLR, Fast_Read, DOFR, DIOFR, QOFR, QIOFR, WRLR, PW, PP, PE, SE, BE, SSE, DP, RDP Reset to 0 Same as POR 2 Not significant Under completion of an Erase or Program cycle of a PW, PP, DIFP, DIEFP, SSE, SE, BE operation Reset to 0 Equivalent to POR 2 Addressed data could be modified Under completion of a WRSR operation Device deselected S High and in standby mode Reset to 0 Reset to 0 Equivalent to POR after tW Same as POR 2 Write is correctly completed Not significant Note 1 S remains Low while Reset is Low. 2 See 11 Power-up and power-down The Hold/Reset feature is not available when the Hold Reset / DQ3 pin is used as I/O DQ3 functionality during Quad Instructions QOFR, QIOFR,QIFP and QIEFP. The Hold/Reset feature can be disabled by using of the bit 4 of the VECR. 26/185 N25Q128 - V Operating features Dual SPI DIO-SPI Protocol In the Dual SPI DIO-SPI protocol all the instructions, addresses and I/O data are transmitted on two data lines. All the functionality available in the Extended SPI protocol is also available in the DIO-SPI protocol. The DIO-SPI instructions are comparable with the Extended SPI instructions however, in DIO-SPI, the instructions are multiplexed on the two data lines, DQ0 and DQ1. The only exceptions are the READ, Quad Read, and Program instructions, which are not available in DIO-SPI protocol, and the RDID instruction, which is replaced in the DIO-SPI protocol by the Multiple I/O Read Identification MIORDID instruction. The Multiple I/O Read Identification Instruction reads just the standard SPI electronic ID 3 bytes , while the Extended SPI protocol RDID instruction allows access to the UID bytes. To help the application code port from Extended SPI to DIO-SPI protocol, the instructions available in the DIO-SPI protocol have the same operation code as the Extended SPI protocol, the only exception being the MIORDID instruction. Multiple Read Identification The Multiple I/O Read Identification MIORDID instruction is available to read the device electronic ID.With respect to the RDID instruction of the Extended SPI protocol, the output data, shifted out on the 2 data lines DQ0 and DQ1. Since the read ID instruction in the DIO-SPI protocol is limited to 3 bytes of the standard electronic ID, the UID bytes are not read with the MIORDID instruction Dual Command Fast reading Reading the memory data multiplexing the instruction, the addresses and the output data on 2 data lines can be achieved in DIO-SPI protocol by mean of the Dual Command Fast Read instruction, that has 3 instruction codes BBh, 3Bh and 0Bh to help the application code porting from Extended SPI protocol to DIO-SPI protocol. Of course quad and single I/O Read instructions are not available in DIO-SPI mode. For Dual Command fast read instructions the number of dummy clock cycles is configurable by using VCR bits [7:4] or NVCR bits After a successful reading instruction, a reduced tSHSL equal to 20ns is allowed to further improve random access time in all the other cases tSHSL should be at least 50 ns . See Table AC Characteristics. Page programming Reset functionality is available instead of Hold in devices with a dedicated part number. See Section 16 Ordering information. Quad Input NV configuration bit NVCR bit 3 The Quad Input NV configuration bit can be used to make the memory start working in QIOSPI protocol directly after the power on sequence. The products are delivered with this set to 1, making the memory default in Extended SPI protocol, if the application sets this bit to 0 the device will enter in QIO-SPI protocol right after the next power on. Please note that in case both QIO-SPI and DIO-SPI are enabled both bit 3 and bit 2 of the Non Volatile Configuration Register set to 0 , the memory will work in QIO-SPI. 38/185 N25Q128 - V Volatile and Non Volatile Registers Dual Input NV configuration bit NVCR bit 2 The Dual Input NV configuration bit can be used to make the memory start working in DIOSPI protocol directly after the power on sequence. The products are delivered with this set to 1, making the memory default in Extended SPI protocol, if the application sets this bit to 0 the device will enter in QIO-SPI protocol right after the next power on. Please note that in case both QIO-SPI and DIO-SPI are enabled both bit 3 and bit 2 of the Non Volatile Configuration Register set to 0 , the memory will work in QIO-SPI. Volatile Configuration Register The Volatile Configuration Register VCR affects the memory configuration after every execution of Write Volatile Configuration Register WRVCR instruction this instruction overwrite the memory configuration set at POR by the Non Volatile Configuration Register NVCR . Its purpose is to define the dummy clock cycles number and to make the device ready to enter in the required XIP mode. 39/185 Volatile and Non Volatile Registers N25Q128 - V Table Volatile Configuration Register Parameter Value Note 0000 As '1111' 0001 0010 0011 0100 0101 0110 0111 VCR<7:4> 1000 Dummy clock cycle 1001 1010 1011 To optimize instruction execution FASTREAD, DOFR,DIOFR,QOFR, QIOFR, ROTP according to the frequency 1100 1101 1110 1111 Target on maximum allowed frequency fc 108MHz and to guarantee backward compatibility default VCR<3> Ready to enter XIP mode To make the data on DQ0 during the first The bit 3 of the Volatile Configuration Register is the XIP enabling bit, this bit must be set to 0 to enable the memory working on XIP mode. For devices with a feature set digit equal to 2 or 4 in the part number Basic XiP , this bit is always Don't Care, and it is possible to operate the memory in XIP mode without setting it to See Section 16 Ordering information. Volatile Enhanced Configuration Register The Volatile Enhanced Configuration Register VECR affects the memory configuration after every execution of Write Volatile Enhanced Configuration Register WRVECR instruction this instruction overwrite the memory configuration set during the POR sequence by the Non Volatile Configuration Register NVCR . Its purpose is: - enabling of QIO-SPI protocol and DIO-SPI protocol Warning in case of both QIO-SPI and DIO-SPI enabled, the memory works in QIO-SPI - HOLD Reset functionality disabling - To enable the VPP functionality in Quad I/O modify operations - To define output driver strength 3 bit 41/185 Volatile and Non Volatile Registers N25Q128 - V Table Volatile Enhanced Configuration Register Parameter Value 0 VECR<7> Quad Input Command 0 VECR<6> Dual Input Command Enabled Disabled default Enabled Disabled default VECR<5> Reserved Reserved VECR<4> Reset/Hold disable Disabled Enabled default VECR<3> Accelerator pin enable in 0 QIO-SPI protocol or in QIFP/QIEFP Enabled Disabled default 000 reserved 001 90 010 60 VECR<2:0> Output Driver Strength 011 45 100 reserved 101 20 110 15 111 30 default Note Enable command on four input lines Enable command on two input lines Fixed value = 0b Disable Pad Hold/Reset functionality The bit must be considered in case of QIFP, QIEFP, or QIO-SPI protocol. It is “Don’t Care” otherwise. Impedance at VCC/2 Quad Input Command VECR<7> The Quad Input Command configuration bit can be used to make the memory start working in QIO-SPI protocol directly after the Write Volatile Enhanced Configuration Register WRVECR instruction. The default value of this bit is 1, corresponding to Extended SPI protocol, If this bit is set to 0 the memory works in QIO-SPI protocol. If VECR bit 7 is set back to 1 the memory start working again in Extended SPI protocol, unless the bit 6 is set to 0 in this case the memory start working in DIO-SPI mode . Please note that in case both QIO-SPI and DIO-SPI are enabled both bit 7and bit 6 of the VECR set to 0 , the memory will work in QIO-SPI. Dual Input Command VECR<6> The Dual Input Command configuration bit can be used to make the memory start working in DIO-SPI protocol directly after the Write Volatile Enhanced Configuration Register WVECR instruction. The default value of this bit is 1, corresponding to Extended SPI protocol, if this bit is set to 0 the memory works in DIO-SPI protocol unless the Volatile Enhanced Configuration Register bit 7 is also set to If the Volatile Enhanced Configuration Register bit 6 is set back to 1 the memory start working again in Extended SPI protocol. Please note that in case both QIO-SPI and DIO-SPI are enabled both bit 7 and bit 6 of the VECR are set to 0 , the memory will work in QIO-SPI. 42/185 N25Q128 - V Reset functionality is available instead of Hold in devices with a dedicated part number. See Section 16 Ordering information. Accelerator pin enable QIO-SPI protocol / QIFP/QIEFP VECR<3> The bit 3 of the Volatile Enhanced Configuration Register determines whether it is possible to use the Vpp accelerating voltage to speed up the internal modify operation with the Quad program and erase instructions both in Extended or QIO-SPI protocols . To use the Vpp voltage with the Quad I/O modify instructions, this bit must be set to The default value is 1, in which case the Vpp pin functionality is disabled in all Quad I/O operations both in Extended SPI and QIO-SPI protocols. If the Volatile Enhanced Configuration Register bit 3 is set to 0, using the QIO-SPI protocol, after a Quad Command Page Program instruction or an Erase instruction is received with all input data in the Program case and the memory is de-selected, the protocol temporarily switches to Extended SPI protocol until Vpp passes from Vpph to normal I/O value this transition is mandatory to come back to QIO-SPI protocol , to enable the possibility to perform polling instructions to check if the internal modify cycle is finished by means of the WIP bit of the Status Register or of the Program/Erase controller bit of the Flag Status register or Program/Erase Suspend instruction even if the DQ2 pin is temporarily used in his Vpp functionality. If the Volatile Enhanced Configuration Register bit 3 is set to 0, after any quad modify instruction both in Extended SPI protocol and QIO-SPI protocol , there is a maximum allowed time-out of 200 ms after the last instruction input is received and the memory is deselected to raise the Vpp signal to Vpph otherwise, the modify instruction starts at normal speed, without the Vpph enhancement, and a flag error appears on Flag Status Register bit Output Driver Strength VECR<2:0> The bits from 2 to 0 of the VECR set the value of the output driver strength, enabling to optimize the impedance at Vcc/2 output voltage for the specific application as described in Table Volatile Enhanced Configuration Register. The default values of Output Driver Strength is set by the dedicated bits of the Non Volatile Configuration Register NVCR , the parts are delivered with the output impedance at Vcc/2 equal to 30 Ohms. 43/185 Volatile and Non Volatile Registers N25Q128 - V Flag Status Register The Flag Status Register is a powerful tool to investigate the status of the device, checking information regarding what is actually doing the memory and detecting possible error conditions. The Flag status register is composed by 8 bit.Three bits Program/Erase Controller bit, Erase Suspend bit and Program Suspend bit are a “Status Indicator bit”, they are set and reset automatically by the memory. Four bits Erase error bit, Program error bit, VPP 1 to 0 error bit and Protection error bit are “Error Indicators bits”, they are set by the memory when some program or erase operation fails or the user tries to perform a forbidden operation. The user can clear the Error Indicators bits by mean of the Clear Flag Status Register CLFSR instruction. All the Flag Status Register bits can be read by mean of the Read Status Register RFSR instruction. 44/185 N25Q128 - V Volatile and Non Volatile Registers Table BIT 7 6 5 4 3 2 1 0 Flag Status Register Description P/E Controller not WIP Erase Suspend Erase Program VPP Program Suspend Protection RESERVED Status Error Status Error Note P/E Controller Status bit The bit 7 of the Flag Status register represents the Program/Erase Controller Status bit, It indicates whether there is a Program/Erase internal cycle active. When P/E Controller Status bit is Low FSR<7>=0 the device is busy when the bit is High FSR<7>=1 the device is ready to process a new command. This bit has the same meaning of Write In Progress WIP bit of the standard SPI Status Register, but with opposite logic FSR<7> = not WIP It's possible to make the polling instructions, to check if the internal modify operations are finished, both on the Flag Status register bit 7 or on WIP bit of the Status Register. Erase Suspend Status bit The bit 6 of the Flag Status register represents the Erase Suspend Status bit, It indicates that an Erase operation has been suspended or is going to be suspended. The bit is set FSR<6>=1 within the Erase Suspend Latency time, that is as soon as the Program/Erase Suspend command PES has been issued, therefore the device may still complete the operation before entering the Suspend Mode. The Erase Suspend Status should be considered valid when the P/E Controller bit is high FSR<7>=1 . When a Program/Erase Resume command PER is issued the Erase Suspend Status bit returns Low FSR<6>=0 Erase Status bit The bit 5 of the Flag Status Register represents the Erase Status bit. It indicates an erase failure or a protection error when an erase operation is issued. When the Erase Status bit is High FSR<5>=1 after an Erase failure that means that the P/E Controller has applied the maximum pulses number to the portion to be erased and still failed to verify that it has correctly erased. The Erase Status bit should be read once the P/E Controller Status bit is High. 45/185 Volatile and Non Volatile Registers N25Q128 - V The second software protected mode SPM2 uses the Block Protect bits BP3, BP2, BP1, BP0 and the Top/Bottom bit TB bit to allow part of the memory to be configured as readonly. See Section 16 Ordering information. Table Software protection truth table Sectors 0 to 255, 64 Kbyte Sector Lock Register Lock Down bit Write Lock bit Protection Status Sector unprotected from Program/Erase/Write operations. Sector protection status cannot be changed except by a power-up. Sector protected from Program/Erase/Write operations. Sector protection status cannot be changed except by a power-up. As a second level of protection, the Write Protect signal applied on the W/VPP pin can freeze the Status Register in a read-only mode. In this mode, the Block Protect bits BP3, BP2, BP1, BP0 and the Status Register Write Disable bit SRWD are protected. 49/185 Protection modes N25Q128 - V Table Protected area sizes TB bit = 0 Status Register Content Memory Content TB bit BP3 Bit PB2 Bit BP1 Bit BP0 Bit Protected Area Unprotected Area None All sectors 0 to 255 Upper 256th 1/2 Mbit, sector 255 Sectors 0 to 254 Upper 128th Sectors 0 to 253 1 Mbit, 2 sectors 254 to 255 Upper 64th Sectors 0 to 251 2 Mbit, 4 sectors 252 to 255 Upper 32nd Sectors 0 to 247 4 Mbit, 8 sectors 248 to 255 Upper 16th Sectors 0 to 239 8 Mbit, 16 sectors 240 to 255 Upper 8th Sectors 0 to 223 16 Mbit, 32 sectors 224 to 255 Upper quarter Lower 3 quarters sectors 0 to 32 Mbit, 64 sectors 193 to 255 191 Upper half Reset functionality is available instead of Hold in devices with a dedicated part number. See Section 16 Ordering information. Figure Quad Input/Output Fast Read instruction sequence Mode 3 C Mode 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 21 22 23 24 25 26 27 Instruction Address 01234567 IO switches from Input to Output 4040 4 DQ1 DQ2 Don’t Care Don’t Care 5151 5 6 262 6 Note: 7373 7 ‘1’ A23-16 A15-8 A7-0 Dummy ex. 10 Byte 1 Byte 2 Quad_Output_Fast_Read Quad I/O Fast Read The Quad I/O Fast Read QIOFR instruction is very similar to the Quad Output Fast Read QOFR , except that the address bits are shifted in on four pins pin DQ0, pin DQ1, pin W/VPP/DQ2 and pin HOLD/DQ3 1 instead of only one. Reset functionality is available instead of Hold in devices with a dedicated part number. See Section 16 Ordering information. 85/185 Instructions N25Q128 - V Figure Quad Input/ Output Fast Read instruction sequence Mode 3 C Mode 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 21 22 23 24 25 26 27 Instruction 404040 IO switches from Input to Output 4040 4 DQ1 DQ2 Don’t Care Don’t Care 515151 626262 5151 5 6 262 6 737373 ‘1’ 7373 7 A23-16 A15-8 A7-0 Dummy ex. 10 Byte 1 Byte 2 Quad_IO_Fast_Read Read OTP ROTP The device is first selected by driving Chip Select S Low. The instruction code for the Read OTP ROTP instruction is followed by a 3-byte address A23- A0 and a dummy byte. Each bit is latched in on the rising edge of Serial Clock C . Then the memory contents at that address are shifted out on Serial Data output DQ1 . Each bit is shifted out at the maximum frequency, fCmax, on the falling edge of Serial Clock C . The instruction sequence is shown in Figure The address is automatically incremented to the next higher address after each byte of data is shifted out. There is no rollover mechanism with the Read OTP ROTP instruction. This means that the Read OTP ROTP instruction must be sent with a maximum of 65 bytes to read. All other bytes outside the OTP area are “Don’t Care.” The Read OTP ROTP instruction is terminated by driving Chip Select S High. Chip Select S can be driven High at any time during data output. Any Read OTP ROTP instruction issued while an Erase, Program or Write cycle is in progress, is rejected without having any effect on the cycle that is in progress. 86/185 N25Q128 - V Figure Read OTP instruction and data-out sequence Instructions DQ0 DQ1 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 Instruction High Impedance 24-bit address 23 22 21 3210 S 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 C Dummy cycles DQ0 DQ1 76543210 DATA OUT 1 76543210 MSB DATA OUT n For devices with a dedicated part number, at the bottom or top of the addressable area there are 8 boot sectors, each one having 16 4Kbytes subsectors. See Section 16 Ordering information. The Subsector Erase SSE instruction sets to '1' FFh all bits inside the chosen subsector. Before it can be accepted, a Write Enable WREN instruction must previously have been executed. Apart form the parallelizing of the instruction code and the address on the four pins DQ0, DQ1, DQ2 and DQ3, the instruction functionality is exactly the same as the Subsector Erase SSE instruction of the Extended SPI protocol, please refer to Section Subsector Erase SSE for further details. 142/185 N25Q128 - V Instructions Figure Subsector Erase instruction sequence QIO-SPI 0123456789 C Instruction 24-Bit Address 20 16 12 8 4 0 21 17 13 9 5 1 22 18 14 10 6 2 23 19 15 11 7 3 Quad_Subsector_Erase Sector Erase SE The Sector Erase SE instruction sets to '1' FFh all bits inside the chosen sector. Before it can be accepted, a Write Enable WREN instruction must previously have been executed. Apart form the parallelizing of the instruction code and the address on the four pins DQ0, DQ1, DQ2 and DQ3, the instruction functionality is exactly the same as the Sector Erase SE instruction of the Extended SPI protocol, please refer to Section Sector Erase SE for further details. Figure Sector Erase instruction sequence QIO-SPI S 0123456789 C Instruction 24-Bit Address 20 16 12 8 4 0 21 17 13 9 5 1 22 18 14 10 6 2 23 19 15 11 7 3 Quad_Sector_Erase 143/185 Instructions N25Q128 - V Bulk Erase BE The Bulk Erase BE instruction sets all bits to '1' FFh . Before it can be accepted, a Write Enable WREN instruction must previously have been executed. Apart form the parallelizing of the instruction code on the four pins DQ0, DQ1, DQ2 and DQ3, the instruction functionality is exactly the same as the Bulk Erase BE instruction of the Extended SPI protocol, please refer to Section Bulk Erase BE for further details. Figure Bulk Erase instruction sequence QIO-SPI 01 Instruction Quad_Bulk_Erase Program/Erase Suspend The Program/Erase Suspend instruction allows the controller to interrupt a Program or an Erase instruction, in particular Sector Erase and Quad Command Page Program can be suspended and erased while that Subsector Erase, Bulk Erase, Write Non Volatile Configuration register and Program OTP can not be suspended. Apart form the parallelizing of the instruction code on the four pins DQ0, DQ1, DQ2 and DQ3, the instruction functionality is exactly the same as the Program/Erase Suspend PES instruction of the Extended SPI protocol, please refer to Section Program/Erase Suspend for further details. 144/185 N25Q128 - V Figure Program/Erase Suspend instruction sequence QIO-SPI S 01 C Instruction Instructions Quad_Program_Erase_Suspend For devices with a feature set digit equal to 2 or 4 in the part number Basic XiP , it is not necessary to set the Volatile Configuration Register bit 3 to enter XIP mode it is possible to enter XIP mode directly by setting XIP Confirmation bit to 1 during the first dummy clock cycle after a fast read instruction.See Section 16 Ordering information. 161/185 XIP Operations Figure N25Q128 Read functionality Flow Chart Power On NVCR Check N25Q128 - V Is XIP enabled ? Yes No SPI standard mode no XiP, VCR <3> = 1 XIP mode No Yes XiP Confirmation bit = 0 ? VCR<3> = 0 ? SPI mode no XIP but Yes ready to enter XIP No Read Instructions ? XiP Confirmation bit = 0 ? Enter XIP mode by setting the Non Volatile Configuration Register To use the Non Volatile Configuration Register method to enter in XIP mode it is necessary to set the Non Volatile Configuration Register bits from 11 to 9 with the pattern corresponding to the required XIP mode by mean of the Write Non Volatile Configuration Register WRNVCR instruction. See Table NVCR XIP bits setting example. This instruction doesn't affect the XIP state until the next Power on sequence. In this case, after the next power on sequence, the memory directly accept addresses and then, after the dummy clock cycles configurable , outputs the data as described in Table NVCR XIP bits setting example. For example to enable fast POR and XIP on QIOFR in normal SPI protocol with six dummy clock cycles the following pattern must be issued: 162/185 N25Q128 - V XIP Operations Table NVCR XIP bits setting example WRNVCR + 0110 opcode 6 dummy cycles for fast read instructions XIP set as default Quad I/O mode Output Buffer driver strength default FAST POR enabled Hold/Reset not disabled Extended SPI protocol Don’t Care Figure XIP mode directly after power on NVCR check XIP enabled Vd tVSI <100u Mode 3 C Mode 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 IO switches from Input to Output For devices with a feature set digit equal to 2 or 4 in the part number Basic XiP , it is not necessary to set the Volatile Configuration Register bit 3 to enter in XIP mode it is possible to enter directly in XIP mode by setting XIP Confirmation bit to 1 during the first dummy clock cycle after a fast read instruction. See Section 16 Ordering information. Table VCR XIP bits setting example 81h WRVCR opcode + 0110 6 dummy cycles Ready for XIP 000 Reserved 164/185 N25Q128 - V XIP Operations Figure XiP enter by VCR 2/2 QIOFR in normal SPI protocol example Mode 3 C Mode 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Instruction 4 0 4 0 4 0 Xb IO switches from Input to Output 4040 4 DQ1 DQ2 Don’t Care Don’t Care 515151 626262 5151 5 6 262 6 Note: 737373 7373 7 ‘1’ A23-16 A15-8 A7-0 Dummy ex. 6 Byte 1 Byte 2 XIP_VCR Xb is the XIP Confirmation bit, and it should be set to '0' to keep XIP state or '1' to exit XIP mode and return to standard read mode. XIP mode hold and exit The XIP mode does require at least one additional clock cycle to allow the XIP Confirmation bit to be sent to the memory on DQ0 during the first dummy clock cycle. The device decodes the XIP Confirmation bit with the scheme - XIP Confirmation bit=0 means to hold XIP Mode - XIP Confirmation bit=1 means to exit XIP Mode and comes back to read mode, that means codifying the first byte after the next chip select as an instruction code. In Dual I/O XIP mode, the values of DQ1 during the first dummy clock cycle after the addresses is always Don't Care. In Quad I/O XIP mode, the values of DQ3, DQ2 and DQ1 during the first dummy clock cycle after the addresses are always Don't Care. In Dual and Single I/O XIP mode, in presence of the RESET pin enabled in devices with a dedicated part number , a low pulse on that pin resets the XIP protocol as defined by the Volatile Configuration Register, reporting the memory at the state of last power up, as defined by the Non Volatile Configuration Register. In Quad I/O XiP modes, it is possible to reset the memory for devices with a dedicated part number only when the device is deselected. See Section 16 Ordering information. 165/185 XIP Operations N25Q128 - V XIP Memory reset after a controller reset If during the application life the system controller is reset during operation, and the device features the RESET functionality in devices with a dedicated part number , and the feature has not been disabled, after the controller resets, the memory returns to POR state and there is no issue. See Section 16 Ordering information. In all the other cases, it is possible to exit the memory from the XIP mode by sending the following rescue sequence at the first chip selection after a system reset: DQ0= '1' for: 7 clock cycles within S low S becomes high before 8th clock cycle + 13 clock cycles within S low S becomes high before 14th clock cycle + 25 clock cycles within S low S becomes high before 26th clock cycle The global effect is only to exit from XIP without any other reset. 166/185 N25Q128 - V 11 Power-up and power-down Power-up and power-down At power-up and power-down, the device must not be selected that is Chip Select S must follow the voltage applied on VCC until VCC reaches the correct value - VCC min at power-up, and then for a further delay of tVSL - VSS at power-down A safe configuration is provided in Section 3 SPI Modes. To avoid data corruption and inadvertent write operations during power-up, a Power On Reset POR circuit is included. The logic inside the device is held reset while VCC is less than the Power On Reset POR threshold voltage, VWI - all operations are disabled, and the device does not respond to any instruction. Moreover, the device ignores the Write Enable WREN instruction and all the modify instructions until a time delay of tPUW has elapsed after the moment that VCC rises above the VWI threshold. However, the correct operation of the device is not guaranteed if, by this time, VCC is still below VCC min . No Write Status Register, Program or Erase instructions should be sent until the later of - tPUW after VCC has passed the VWI threshold - tVSL after VCC has passed the VCC min level These values are specified in Table Power-up timing and VWI threshold. If the time, tVSL, has elapsed, after VCC rises above VCC min , the device can be selected for READ instructions even if the tPUW delay has not yet fully elapsed. After power-up, the device is in the following state - The device is in the Standby Power mode not the Deep Power-down mode - The Write Enable Latch WEL bit is reset - The Write In Progress WIP bit is reset - The Lock Registers are configured as Write Lock bit, Lock Down bit = Normal precautions must be taken for supply line decoupling, to stabilize the VCC supply. Each device in a system should have the VCC line decoupled by a suitable capacitor close to the package pins generally, this capacitor is of the order of 100 nF . At power-down, when VCC drops from the operating voltage, to below the Power On Reset POR threshold voltage, VWI, all operations are disabled and the device does not respond to any instruction the designer needs to be aware that if power-down occurs while a Write, Program or Erase cycle is in progress, some data corruption may result . VPPH must be applied only when VCC is stable and in the VCC min to VCC max voltage range. 167/185 Power-up and power-down Figure Power-up timing, Fast POR selected N25Q128 - V VCC max Chip selection not allowed WREN issued VCC min Chip reset VWI tVTR Polling allowed SPI protocol WIP = 1 WEL = 0 tDTW All read, WRCR, Polling WRECR allowed Device fully accessible Starting protocol defined by NVCR WIP = 0 WEL = 0 WIP = 1 WEL = 1 WIP = 0 WEL = 1 time Ordering information 16 Ordering information N25Q128 - V Note: For further information on line items not listed here or on any aspect of this device, please contact your nearest Numonyx Sales Office. Table Ordering information scheme Example: N25Q128 A 1 B F8 4 0 E Device type N25Q = serial Flash memory, Quad I/O, XiP Device density 128 = 128 Mbit Technology A = 65 nm Feature set 1 = Byte addressability, Hold pin, Numonyx XiP 2 = Byte addressability, Hold pin, Basic XiP 3 = Byte addressability, Reset pin, Numonyx XiP 4 = Byte addressability, Reset pin, Basic XiP Operating voltage 1 = VCC = V to 2 V Block Structure B = Bottom T = Top E = Uniform no boot sectors Package F8 = VDFPN8 8 x 6 mm MLP8 RoHS compliant SF = SO16 300 mils width RoHS compliant 12 = TBGA24 6 x 8 mm RoHS compliant Temperature and test flow 4 = Industrial temperature range, to 85 °C Device tested with standard test flow A = Automotive temperature range, to 125 °C Device tested with high reliability certified test flow H = Industrial temperature range, to 85 °C Device tested with high reliability certified test flow Security features 1 0 = No extra security Packing options E = Tray packing F = Tape and reel packing G = Tube packing Additional secure options are available upon customer request. 182/185 N25Q128 - V Ordering information Table Valid Order Information Line Items Block Structure Package Temperature and Test Flow N25Q128A11BF840E N25Q128A11BF840F N25Q128A21BF840E N25Q128A21BF840F N25Q128A11TF840E N25Q128A11TF840F Byte addressability, Hold pin, Numonyx XiP Bottom Byte addressability, Hold pin, Basic XiP Bottom Byte addressability, Hold pin, Numonyx XiP VDFPN8 8x6 mm VDFPN8 8x6 mm VDFPN8 8x6 mm Industrial temp Standard test flow Industrial temp Standard test flow Industrial temp Standard test flow N25Q128A21TF840E N25Q128A21TF840F N25Q128A11B1240E N25Q128A11B1240F N25Q128A21B1240E N25Q128A21B1240F Byte addressability, Hold pin, Basic XiP Byte addressability, Hold pin, Numonyx XiP Bottom Byte addressability, Hold pin, Basic XiP Bottom VDFPN8 8x6 mm TBGA24 6x8 mm TBGA24 6x8 mm Industrial temp Standard test flow Industrial temp Standard test flow Industrial temp Standard test flow N25Q128A11T1240E N25Q128A11T1240F N25Q128A21T1240E N25Q128A21T1240F N25Q128A11BSF40F N25Q128A11BSF40G Byte addressability, Hold pin, Numonyx XiP Byte addressability, Hold pin, Basic XiP Byte addressability, Hold pin, Numonyx XiP Bottom TBGA24 Industrial temp 6x8 mm Standard test flow

PDF Datasheet Preview

N25Q128
128-Mbit, V, multiple I/O, 4-Kbyte subsector erase on boot sectors, XiP enabled, serial flash memory with 108 MHz SPI bus interface
- SPI-compatible serial bus interface - 108 MHz maximum clock frequency - V to 2 V single supply voltage - Supports legacy SPI protocol and new Quad

I/O or Dual I/O SPI protocol - Quad/Dual I/O instructions resulting in an
equivalent clock frequency up to 432 MHz - XIP mode for all three protocols

Configurable via volatile or non-volatile registers enabling the memory to work in XiP mode directly after power on
- Program/Erase suspend instructions - Continuous read of entire memory via single
instruction Fast Read Quad or Dual Output Fast Read Quad or Dual I/O Fast Read - Flexible to fit application Configurable number of dummy cycles Output buffer configurable Fast POR instruction to speed up power
on phase Reset function available upon customer
request - 64-byte user-lockable, one-time programmable

OTP area - Erase capability

Subsector 4-Kbyte granularity in the 8 boot sectors bottom or top parts .

Sector 64-Kbyte granularity - Write protections

Software write protection applicable to every 64-Kbyte sector volatile lock bit

Hardware write protection protected area size defined by five non-volatile bits BP0, BP1, BP2, BP3 and TB bit

VDFPN8 F8 8 x 6 mm MLP8

SO16 SF 300 mils width

TBGA24 12 6 x 8 mm

Additional smart protections available upon customer request
- Deep Power-down mode 5 µA typical - Electronic signature

JEDEC standard two-byte signature BB18h

Additional 2 Extended Device ID EDID bytes to identify device factory options

Unique ID code UID with 14 bytes readonly, available upon customer request
- 100,000 + program/erase cycles per sector - More than 20 years data retention - Packages

February 2010
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Contents

Contents

N25Q128 - V

Description 12

Signal descriptions 16

Serial data output DQ1 16

Serial data input DQ0 16

Serial Clock C 16

Chip Select S 16

Hold or Reset 17

Write protect/enhanced program supply voltage W/VPP , DQ2 18

VCC supply voltage 18 VSS ground 18

SPI Modes 19

SPI Protocols 21

Extended SPI protocol 21
Ordering information 182
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List of tables

List of tables

N25Q128 - V

Table

Table
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N25Q128 - V

List of figures

List of figures

Figure

Logic diagram 13 VDFPN8 connections 14 SO16 connections 14 BGA connections 15 Bus master and memory devices on the SPI bus 19 Extended SPI protocol example 20 Hold condition activation 25 Non Volatile and Volatile configuration Register Scheme 33 Block diagram 52 Read identification instruction and data-out sequence 80 Read Data Bytes instruction and data-out sequence 81 Read Data Bytes at Higher Speed instruction and data-out sequence 82 Dual Output Fast Read instruction sequence 83 Dual I/O Fast Read instruction sequence 84 Quad Input/Output Fast Read instruction sequence. 85 Quad Input/ Output Fast Read instruction sequence 86 Read OTP instruction and data-out sequence 87 Write Enable instruction sequence 88 Write Disable instruction sequence 89 Page Program instruction sequence. 91 Dual Input Fast Program instruction sequence. 92 Dual Input Extended Fast Program instruction sequence 93 Quad Input Fast Program instruction sequence 94 Quad Input Extended Fast Program instruction sequence 95 Program OTP instruction sequence 96 How to permanently lock the OTP bytes 97 Subsector Erase instruction sequence 98 Sector Erase instruction sequence 99 Bulk Erase instruction sequence 99 Read Status Register instruction sequence 102 Write Status Register instruction sequence 103 Read Lock Register instruction and data-out sequence 104 Write to Lock Register instruction sequence 105 Read Flag Status Register instruction sequence 106 Clear Flag Status Register instruction sequence 107 Read NV Configuration Register instruction sequence 107 Write NV Configuration Register instruction sequence. 108 Read Volatile Configuration Register instruction sequence 109 Write Volatile Configuration Register instruction sequence 110 Read Volatile Enhanced Configuration Register instruction sequence. 110 Write Volatile Enhanced Configuration Register instruction sequence. 111 Deep Power-down instruction sequence 112 Release from Deep Power-down instruction sequence 113 Multiple I/O Read Identification instruction and data-out sequence DIO-SPI 115 Dual Command Fast Read instruction and data-out sequence DIO-SPI 116 Read OTP instruction and data-out sequence DIO-SPI 117 Write Enable instruction sequence DIO-SPI 117 Write Disable instruction sequence DIO-SPI 118
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N25Q128 - V

Figure Dual Command Page Program instruction sequence DSP, 02h 118 Figure Dual Command Page Program instruction sequence DSP, A2h 119 Figure Dual Command Page Program instruction sequence DSP, D2h 119 Figure Program OTP instruction sequence DIO-SPI 120 Figure Subsector Erase instruction sequence DIO-SPI 120 Figure Sector Erase instruction sequence DIO-SPI. 121 Figure Bulk Erase instruction sequence DIO-SPI 122 Figure Program/Erase Suspend instruction sequence DIO-SPI 122 Figure Program/Erase Resume instruction sequence DIO-SPI 123 Figure Read Status Register instruction sequence DIO-SPI 124 Figure Write Status Register instruction sequence DIO-SPI 124 Figure Read Lock Register instruction and data-out sequence DIO-SPI. 125 Figure Write to Lock Register instruction sequence DIO-SPI 126 Figure Read Flag Status Register instruction sequence DIO-SPI 126 Figure Clear Flag Status Register instruction sequence DIO-SPI 127 Figure Read NV Configuration Register instruction sequence DIO-SPI 127 Figure Write NV Configuration Register instruction sequence DIO-SPI 128 Figure Read Volatile Configuration Register instruction sequence DIO-SPI 129 Figure Write Volatile Configuration Register instruction sequence DIO-SPI 129 Figure Read Volatile Enhanced Configuration Register instruction sequence DIO-SPI 130 Figure Write Volatile Enhanced Configuration Register instruction sequence DIO-SPI 131 Figure Deep Power-down instruction sequence 131 Figure Release from Deep Power-down instruction sequence 132 Figure Multiple I/O Read Identification instruction and data-out sequence QIO-SPI 135 Figure Quad Command Fast Read instruction and data-out sequence QSP, 0Bh 136 Figure Quad Command Fast Read instruction and data-out sequence QSP, 6Bh 136 Figure Quad Command Fast Read instruction and data-out sequence QSP, EBh 137 Figure Read OTP instruction and data-out sequence QIO-SPI 138 Figure Write Enable instruction sequence QIO-SPI. 138 Figure Write Disable instruction sequence QIO-SPI 139 Figure Quad Command Page Program instruction sequence QIO-SPI, 02h. 140 Figure Quad Command Page Program instruction sequence QIO-SPI, 12h. 140 Figure Quad Command Page Program instruction sequence QIO-SPI, 32h. 141 Figure Program OTP instruction sequence QIO-SPI 142 Figure Subsector Erase instruction sequence QIO-SPI. 143 Figure Sector Erase instruction sequence QIO-SPI 143 Figure Bulk Erase instruction sequence QIO-SPI 144 Figure Program/Erase Suspend instruction sequence QIO-SPI 145 Figure Program/Erase Resume instruction sequence QIO-SPI. 146 Figure Read Status Register instruction sequence QIO-SPI 147 Figure Write Status Register instruction sequence QIO-SPI 148 Figure Read Lock Register instruction and data-out sequence QIO-SPI 149 Figure Write to Lock Register instruction sequence QIO-SPI 150 Figure Read Flag Status Register instruction sequence QIO-SPI 151 Figure Clear Flag Status Register instruction sequence QIO-SPI 152 Figure Read NV Configuration Register instruction sequence QIO-SPI 153 Figure Write NV Configuration Register instruction sequence QIO-SPI 154 Figure Read Volatile Configuration Register instruction sequence QIO-SPI 155 Figure Write Volatile Configuration Register instruction sequence QIO-SPI 156 Figure Read Volatile Enhanced Configuration Register instruction sequence QIO-SPI 157 Figure Write Volatile Enhanced Configuration Register instruction sequence QIO-SPI 158 Figure Deep Power-down instruction sequence 159
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List of figures

Figure Deep Power-down instruction sequence 160 Figure N25Q128 Read functionality Flow Chart 162 Figure XIP mode directly after power on 163 Figure XiP enter by VCR 2/2 QIOFR in normal SPI protocol example 165 Figure Power-up timing, Fast POR selected 168 Figure Power-up timing, Fast POR not selected 168 Figure AC measurement I/O waveform 171 Figure Reset AC waveforms program or erase cycle is in progress 174 Figure Serial input timing 175 Figure Write protect setup and hold timing during WRSR when SRWD=1 176 Figure Hold timing 176 Figure Output timing 177 Figure VPPH timing 177 Figure VDFPN8 MLP8 8-lead very thin dual flat package no lead,
8 x 6 mm, package outline 178 Figure SO16 wide - 16-lead plastic small outline, 300 mils body width, package outline 179 Figure TBGA - 6 x 8 mm, 24-ball, mechanical package outline 180
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N25Q128 - V

The N25Q128 is a 128 Mbit 16Mb x 8 serial Flash memory, with advanced write protection mechanisms. It is accessed by a high speed SPI-compatible bus and features the possibility to work in XIP “eXecute in Place” mode.

The N25Q128 supports innovative, high-performance quad/dual I/O instructions, these new instructions allow to double or quadruple the transfer bandwidth for read and program operations.

Furthermore the memory can be operated with 3 different protocols - Standard SPI Extended SPI protocol - Dual I/O SPI - Quad I/O SPI

The Standard SPI protocol is enriched by the new quad and dual instructions Extended SPI protocol . For Dual I/O SPI DIO-SPI all the instructions codes, the addresses and the data are always transmitted across two data lines. For Quad I/O SPI QIO-SPI the instructions codes, the addresses and the data are always transmitted across four data lines thus enabling a tremendous improvement in both random access time and data throughput.

The memory can work in “XIP mode”, that means the device only requires the addresses and not the instructions to output the data. This mode dramatically reduces random access time thus enabling many applications requiring fast code execution without shadowing the memory content on a RAM.

The XIP mode can be used with QIO-SPI, DIO-SPI, or Extended SPI protocol, and can be entered and exited using different dedicated instructions to allow maximum flexibility for applications required to enter in XIP mode right after power up of the device, this can be set as default mode by using dedicated Non Volatile Register NVR bits.

It is also possible to reduce the power on sequence time with the Fast POR Power on Reset feature, enabling a reduction of the latency time before the first read instruction can be performed. Another feature is the ability to pause and resume program and erase cycles by using dedicated Program/Erase Suspend and Resume instructions.

The N25Q128 memory offers the following additional Features to be configured by using the Non Volatile Configuration Register NVCR for default /Non-Volatile settings or by using the Volatile and Volatile Enhanced Configuration Registers for Volatile settings - the number of dummy cycles for fast read instructions single, dual and, quad I/O
according to the operating frequency - the output buffer impedance - the type of SPI protocol extended SPI, DIO-SPI or QIO-SPI - the required XIP mode - Fast or standard POR sequence - the Hold Reset functionality enabling/disabling

The memory is organized as 248 64-Kbyte main sectors, in products with Bottom or Top architecture there are 8 64-Kbyte boot sectors, and each boot sector is further divided into 16 4-Kbyte subsectors 128 subsectors in total . The boot sectors can be erased a 4-Kbyte subsector at a time or as a 64-Kbyte sector at a time. The entire memory can be also erased at a time or by sector.
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The memory can be write protected by software using a mix of volatile and non-volatile protection features, depending on the application needs. The protection granularity is of 64Kbyte sector granularity for volatile protections.
Many different N25Q128 configurations are available, please refer to the ordering scheme page for the possibilities. Additional features are available as security options The Security features are described in a dedicated Application Note . Please contact your nearest Numonyx Sales office for more information.

Figure Logic diagram

W/VPP/DQ2

HOLD/DQ3

Note:

Logic_Diagram_x25x
Reset functionality is available in devices with a dedicated part number. See Section 16 Ordering information.

Table Signal names

Signal

C DQ0 DQ1

Serial Clock Serial Data input Serial Data output

Input I/O 1 I/O 2

S W/VPP/DQ2 HOLD/DQ3 4

Chip Select Write Protect/Enhanced Program supply voltage/additional data I/O Hold Reset function available upon customer request /additional data I/O

Input I/O 3 I/O 3

Supply voltage

Ground

Provides dual and quad I/O for Extended SPI protocol instructions, dual I/O for Dual I/O SPI protocol instructions, and quad I/O for Quad I/O SPI protocol instructions.

Provides dual and quad instruction input for Extended SPI protocol, dual instruction input for Dual I/O SPI protocol, and quad instruction input for Quad I/O SPI protocol.

Provides quad I/O for Extended SPI protocol instructions, and quad I/O for Quad I/O SPI protocol instructions.
Reset functionality available with a dedicated part number. See Section 16 Ordering information.
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Note:

There is an exposed central pad on the underside of the VDFPN8 package. This is pulled, internally, to VSS, and must not be connected to any other voltage or signal line on the PCB.

Figure VDFPN8 connections

DQ1 2

W/V /DQ2 PP

VSS 4
8 VCC 7 HOLD/DQ3 6C 5 DQ0

AI13720c
Reset functionality available in devices with a dedicated part number. See Section 16 Ordering information.

Figure SO16 connections

HOLD/DQ3 1 VCC 2 DU 3 DU 4 DU 5 DU 6 S7 DQ1 8
16 C 15 DQ0 14 DU 13 DU 12 DU 11 DU 10 VSS
9 W/V /DQ2 PP

DU = don’t use.

AI13721c

See Package mechanical section for package dimensions, and how to identify pin-1.
Reset functionality available in devices with a dedicated part number. See Section 16 Ordering information.
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Figure BGA connections

W/VPP/DQ2

DQ1 DQ0 HOLD/DQ3

NC = No Connect. See Figure TBGA - 6 x 8 mm, 24-ball, mechanical package outline.
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Signal descriptions

Signal descriptions

N25Q128 - V

Serial data output DQ1

This output signal is used to transfer data serially out of the device. Data are shifted out on the falling edge of Serial Clock C . When used as an Input, It is latched on the rising edge of the Serial Clock C .

In the Extended SPI protocol, during the Quad and Dual Input Fast Program QIFP, DIFP instructions and during the Quad and Dual Input Extended Fast Program QIEFP, DIEFP instructions, pin DQ1 is used also as an input.

In the Dual I/O SPI protocol DIO-SPI the DQ1 pin always acts as an input/output.

In the Quad I/O SPI protocol QIO-SPI the DQ1 pin always acts as an input/output, with the exception of the Program or Erase cycle performed with the Enhanced Program Supply Voltage VPP . In this case the device temporarily goes in Extended SPI protocol. The protocol then becomes QIO-SPI as soon as the VPP pin voltage goes low.

Serial data input DQ0

This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data to be programmed. Values are latched on the rising edge of Serial Clock C . Data are shifted out on the falling edge of the Serial Clock C .

In the Extended SPI protocol, during the Quad and Dual Output Fast Read QOFR, DOFR and the Quad and Dual Input/Output Fast Read QIOFR, DIOFR instructions, pin DQ0 is also used as an input/output.

In the DIO-SPI protocol the DQ0 pin always acts as an input/output.

In the QIO-SPI protocol, the DQ0 pin always acts as an input/output, with the exception of the Program or Erase cycle performed with the VPP. In this case the device temporarily goes in Extended SPI protocol. Then, the protocol returns to QIO-SPI as soon as the VPP pin voltage goes low.

Serial Clock C

This input signal provides the timing for the serial interface. Instructions, addresses, or data present at serial data input DQ0 are latched on the rising edge of Serial Clock C . Data are shifted out on the falling edge of the Serial Clock C .

Chip Select S

When this input signal is high, the device is deselected and serial data output DQ1 is at high impedance. Unless an internal program, erase or write status register cycle is in progress, the device will be in the standby power mode this is not the deep power-down mode . Driving Chip Select S low enables the device, placing it in the active power mode.

After power-up, a falling edge on Chip Select S is required prior to the start of any instruction.
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Signal descriptions

Hold or Reset

The Hold signal is used to pause any serial communications with the device without deselecting the device.
Reset functionality is present instead of Hold in devices with a dedicated part number. See Section 16 Ordering information.

During Hold condition, the Serial Data output DQ1 is in high impedance, and Serial Data input DQ0 and Serial Clock C are Don't Care.

To start the Hold condition, the device must be selected, with Chip Select S driven Low.

For devices featuring Reset instead of Hold functionality, the Reset input provides a hardware reset for the memory.

When Reset is driven High, the memory is in the normal operating mode. When Reset is driven Low, the memory will enter the Reset mode. In this mode, the output is high impedance.

Driving Reset Low while an internal operation is in progress will affect this operation write, program or erase cycle and data may be lost.

In the Extended SPI protocol, during the QOFR, QIOFR, QIFP and the Quad Extended Fast Program QIEFP instructions, the Hold Reset / DQ3 is used as an input/output DQ3 functionality .

In QIO-SPI, the Hold Reset / DQ3 pin acts as an I/O DQ3 functionality , and the HOLD Reset functionality disabled when the device is selected. When the device is deselected S signal is high , in parts with Reset functionality, it is possible to reset the device unless this functionality is not disabled by mean of dedicated registers bits.

The HOLD Reset functionality can be disabled using bit 3 of the NVCR or bit 4 of the VECR.
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Signal descriptions

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Write protect/enhanced program supply voltage W/VPP ,

W/VPP/DQ2 can be used as - A protection control input. - A power supply pin. - I/O in Extended SPI protocol quad instructions and in QIO-SPI protocol instructions.

When the device is operated in Extended SPI protocol with single or dual instructions, the two functions W or VPP are selected by the voltage range applied to the pin. If the W/VPP input is kept in a low voltage range 0 V to VCC the pin is seen as a control input. This input signal is used to freeze the size of the area of memory that is protected against program or erase instructions as specified by the values in the BP[0:3] bits of the Status Register. See Table Status register format .

If VPP is in the range of VPPH, it acts as an additional power supply during the Program or Erase cycles See Table Operating conditions . In this case VPP must be stable until the Program or Erase algorithm is completed.

During the Extended SPI protocol, the QOFR and QIOFR instructions, and the QIO-SPI protocol instructions, the pin W/VPP/DQ2 is used as an input/output DQ2 functionality .

Using the Extended SPI protocol the QIFP, QIEFP and the QIO-SPI Program/Erase instructions, it is still possible to use the VPP additional power supply to speed up internal operations. However, to enable this possibility it is necessary to set bit 3 of the Volatile Enhanced Configuration Register to

In this case the W/VPP/DQ2 pin is used as an I/O pin until the end of the instruction sequence. After the last input data is shifted in, the application should apply VPP voltage to W/VPP/DQ2 within 200 ms to speed up the internal operations. If the VPP voltage is not applied within 200 ms the Program/Erase operations start with standard speed.

The default value of the VECR bit 3 is 1, and the VPP functionality for Quad I/O modify instruction is disabled.

VCC supply voltage

VCC is the supply voltage.

VSS ground

VSS is the reference for the VCC supply voltage.
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SPI Modes

SPI Modes

These devices can be driven by a micro controller with its SPI peripheral running in either of the two following modes CPOL=0, CPHA=0 CPOL=1, CPHA=1 For these two modes, input data is latched in on the rising edge of Serial Clock C , and output data is available from the falling edge of Serial Clock C . The difference between the two modes, as shown in Figure 5, is the clock polarity when the bus master is in standby mode and not transferring data C remains at 0 for CPOL=0, CPHA=0 C remains at 1 for CPOL=1, CPHA=1

Figure Bus master and memory devices on the SPI bus

SPI interface with CPOL, CPHA =
0, 0 or 1, 1

SDO SDI SCK

SPI Bus Master

VSS VCC

DQ1 DQ0

DQ1 DQ0

DQ1 DQ0

CS3 CS2 CS1

SPI memory R
device
the 8 boot sectors at the bottom or top addressable area of a device with a dedicated part number See Section 16 Ordering information - a sector at a time, using the sector erase SE instruction - throughout the entire memory, using the bulk erase BE instruction.

This starts an internal erase cycle of duration tSSE, tSE or tBE . The erase instruction must be preceded by a write enable WREN instruction.

Polling during a write, program or erase cycle

A further improvement in the time to Write Status Register WRSR , POTP, PP, DIFP,DIEFP,QIFP, QIEFP or Erase SSE, SE or BE can be achieved by not waiting for the worst case delay tW, tPP, tSSE, tSE, or tBE . The application program can monitor if the required internal operation is completed, by polling the dedicated register bits to establish when the previous Write, Program or Erase cycle is complete.

The information on the memory being in progress for a Program, Erase, or Write instruction can be checked either on the Write In Progress WIP bit of the Status Register or in the Program/Erase Controller bit of the Flag Status Register.

The Program/Erase Controller bit is the opposite state of the WIP bit in the Status Register.

In the Flag Status Register additional information can be checked, as eventual Program/Erase failures by mean of the Program or erase Error bits.

Active power and standby power modes

When Chip Select S is Low, the device is selected, and in the active power mode.
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Operating features

When Chip Select S is High, the device is deselected, but could remain in the active power mode until all internal cycles have completed program, erase, write status register . The device then goes in to the standby power mode. The device consumption drops to ICC1.

Hold or Reset condition

The Hold signal is used to pause serial communications with the device without resetting the clocking sequence. However, taking this signal Low does not terminate any write status register, program or erase cycle that is currently in progress.

To enter the hold condition, the device must be selected, with Chip Select S Low.

The hold condition starts on the falling edge of the Hold signal, provided that the Serial Clock C is Low as shown in Figure

The hold condition ends on the rising edge of the Hold signal, provided that the Serial Clock C is Low.

If the falling edge does not coincide with Serial Clock C being Low, the hold condition starts after Serial Clock C next goes Low. Similarly, if the rising edge does not coincide with Serial Clock C being Low, the hold condition ends after Serial Clock C next goes Low this is shown in Figure

During the hold condition, the serial data output DQ1 is high impedance, and serial data input DQ0 and Serial Clock C are don’t care.

Normally, the device is kept selected, with Chip Select S driven Low for the whole duration of the hold condition. This is to ensure that the state of the internal logic remains unchanged from the moment of entering the hold condition.

If Chip Select S goes High while the device is in the Hold condition, this has the effect of resetting the internal logic of the device. To restart communication with the device, it is necessary to drive Hold High, and then to drive Chip Select S Low. This prevents the device from going back to the hold condition.

Figure Hold condition activation

HOLD

Hold condition standard use

Hold condition non-standard use

AI02029D
Reset functionality is available instead of Hold in parts with a dedicated part number. See Section 16 Ordering information.

Driving Reset Low while an internal operation is in progress will affect this operation write, program or erase cycle and data may be lost. On Reset going Low, the device enters the reset mode and a time of tRHSL is then required before the device can be reselected by driving Chip Select S Low. For the value of tRHSL, see Table AC Characteristics. All the lock bits are reset to 0 after a Reset Low pulse.
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Operating features

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Table Device Status after Reset Low Pulse

Conditions reset pulse occurred

Lock bits status

Internal logic status Addressed data

While decoding an instruction 1 WREN, WRDI, RDID, RDSR, READ, RDLR, Fast_Read, DOFR, DIOFR, QOFR, QIOFR, WRLR, PW, PP, PE, SE, BE, SSE, DP, RDP

Reset to 0 Same as POR 2

Not significant

Under completion of an Erase or Program cycle of a PW, PP, DIFP, DIEFP, SSE, SE, BE operation

Reset to 0

Equivalent to POR 2

Addressed data could be modified

Under completion of a WRSR operation Device deselected S High and in standby mode

Reset to 0 Reset to 0

Equivalent to POR after tW

Same as POR 2

Write is correctly completed

Not significant

Note 1 S remains Low while Reset is Low. 2 See 11 Power-up and power-down

The Hold/Reset feature is not available when the Hold Reset / DQ3 pin is used as I/O DQ3 functionality during Quad Instructions QOFR, QIOFR,QIFP and QIEFP.

The Hold/Reset feature can be disabled by using of the bit 4 of the VECR.
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Operating features

Dual SPI DIO-SPI Protocol

In the Dual SPI DIO-SPI protocol all the instructions, addresses and I/O data are transmitted on two data lines. All the functionality available in the Extended SPI protocol is also available in the DIO-SPI protocol. The DIO-SPI instructions are comparable with the Extended SPI instructions however, in DIO-SPI, the instructions are multiplexed on the two data lines, DQ0 and DQ1.

The only exceptions are the READ, Quad Read, and Program instructions, which are not available in DIO-SPI protocol, and the RDID instruction, which is replaced in the DIO-SPI protocol by the Multiple I/O Read Identification MIORDID instruction.

The Multiple I/O Read Identification Instruction reads just the standard SPI electronic ID 3 bytes , while the Extended SPI protocol RDID instruction allows access to the UID bytes.

To help the application code port from Extended SPI to DIO-SPI protocol, the instructions available in the DIO-SPI protocol have the same operation code as the Extended SPI protocol, the only exception being the MIORDID instruction.

Multiple Read Identification

The Multiple I/O Read Identification MIORDID instruction is available to read the device electronic ID.With respect to the RDID instruction of the Extended SPI protocol, the output data, shifted out on the 2 data lines DQ0 and DQ1.

Since the read ID instruction in the DIO-SPI protocol is limited to 3 bytes of the standard electronic ID, the UID bytes are not read with the MIORDID instruction

Dual Command Fast reading

Reading the memory data multiplexing the instruction, the addresses and the output data on 2 data lines can be achieved in DIO-SPI protocol by mean of the Dual Command Fast Read instruction, that has 3 instruction codes BBh, 3Bh and 0Bh to help the application code porting from Extended SPI protocol to DIO-SPI protocol. Of course quad and single I/O Read instructions are not available in DIO-SPI mode.

For Dual Command fast read instructions the number of dummy clock cycles is configurable by using VCR bits [7:4] or NVCR bits

After a successful reading instruction, a reduced tSHSL equal to 20ns is allowed to further improve random access time in all the other cases tSHSL should be at least 50 ns . See Table AC Characteristics.

Page programming
Reset functionality is available instead of Hold in devices with a dedicated part number. See Section 16 Ordering information.

Quad Input NV configuration bit NVCR bit 3

The Quad Input NV configuration bit can be used to make the memory start working in QIOSPI protocol directly after the power on sequence. The products are delivered with this set to 1, making the memory default in Extended SPI protocol, if the application sets this bit to 0 the device will enter in QIO-SPI protocol right after the next power on.

Please note that in case both QIO-SPI and DIO-SPI are enabled both bit 3 and bit 2 of the Non Volatile Configuration Register set to 0 , the memory will work in QIO-SPI.
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Volatile and Non Volatile Registers

Dual Input NV configuration bit NVCR bit 2

The Dual Input NV configuration bit can be used to make the memory start working in DIOSPI protocol directly after the power on sequence. The products are delivered with this set to 1, making the memory default in Extended SPI protocol, if the application sets this bit to 0 the device will enter in QIO-SPI protocol right after the next power on.

Please note that in case both QIO-SPI and DIO-SPI are enabled both bit 3 and bit 2 of the Non Volatile Configuration Register set to 0 , the memory will work in QIO-SPI.

Volatile Configuration Register

The Volatile Configuration Register VCR affects the memory configuration after every execution of Write Volatile Configuration Register WRVCR instruction this instruction overwrite the memory configuration set at POR by the Non Volatile Configuration Register NVCR . Its purpose is to define the dummy clock cycles number and to make the device ready to enter in the required XIP mode.
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Volatile and Non Volatile Registers

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Table Volatile Configuration Register

Parameter Value

Note
0000

As '1111'
0001
0010
0011
0100
0101
0110
0111

VCR<7:4>
1000

Dummy clock
cycle
1001
1010
1011

To optimize instruction execution FASTREAD, DOFR,DIOFR,QOFR, QIOFR, ROTP according to the frequency
1100
1101
1110 1111

Target on maximum allowed frequency fc 108MHz and to guarantee backward compatibility default

VCR<3>

Ready to enter XIP mode To make the data on DQ0 during the first
The bit 3 of the Volatile Configuration Register is the XIP enabling bit, this bit must be set to 0 to enable the memory working on XIP mode. For devices with a feature set digit equal to 2 or 4 in the part number Basic XiP , this bit is always Don't Care, and it is possible to operate the memory in XIP mode without setting it to See Section 16 Ordering information.

Volatile Enhanced Configuration Register

The Volatile Enhanced Configuration Register VECR affects the memory configuration after every execution of Write Volatile Enhanced Configuration Register WRVECR instruction this instruction overwrite the memory configuration set during the POR sequence by the Non Volatile Configuration Register NVCR . Its purpose is:
- enabling of QIO-SPI protocol and DIO-SPI protocol

Warning in case of both QIO-SPI and DIO-SPI enabled, the memory works in QIO-SPI
- HOLD Reset functionality disabling - To enable the VPP functionality in Quad I/O modify operations - To define output driver strength 3 bit
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Volatile and Non Volatile Registers

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Table Volatile Enhanced Configuration Register

Parameter

Value
0 VECR<7> Quad Input Command
0 VECR<6> Dual Input Command

Enabled Disabled default Enabled Disabled default

VECR<5> Reserved

Reserved

VECR<4> Reset/Hold disable

Disabled

Enabled default

VECR<3>

Accelerator pin enable in 0

QIO-SPI protocol or in

QIFP/QIEFP

Enabled Disabled default
000 reserved
001 90 010 60

VECR<2:0> Output Driver Strength
011 45 100 reserved
101 20
110 15 111 30 default

Note Enable command on four input lines Enable command on two input lines Fixed value = 0b Disable Pad Hold/Reset functionality The bit must be considered in case of QIFP, QIEFP, or QIO-SPI protocol. It is “Don’t Care” otherwise.

Impedance at VCC/2

Quad Input Command VECR<7>

The Quad Input Command configuration bit can be used to make the memory start working in QIO-SPI protocol directly after the Write Volatile Enhanced Configuration Register WRVECR instruction. The default value of this bit is 1, corresponding to Extended SPI protocol, If this bit is set to 0 the memory works in QIO-SPI protocol. If VECR bit 7 is set back to 1 the memory start working again in Extended SPI protocol, unless the bit 6 is set to 0 in this case the memory start working in DIO-SPI mode .

Please note that in case both QIO-SPI and DIO-SPI are enabled both bit 7and bit 6 of the VECR set to 0 , the memory will work in QIO-SPI.

Dual Input Command VECR<6>

The Dual Input Command configuration bit can be used to make the memory start working in DIO-SPI protocol directly after the Write Volatile Enhanced Configuration Register WVECR instruction. The default value of this bit is 1, corresponding to Extended SPI protocol, if this bit is set to 0 the memory works in DIO-SPI protocol unless the Volatile Enhanced Configuration Register bit 7 is also set to If the Volatile Enhanced Configuration Register bit 6 is set back to 1 the memory start working again in Extended SPI protocol.

Please note that in case both QIO-SPI and DIO-SPI are enabled both bit 7 and bit 6 of the VECR are set to 0 , the memory will work in QIO-SPI.
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Reset functionality is available instead of Hold in devices with a dedicated part number. See Section 16 Ordering information.

Accelerator pin enable QIO-SPI protocol / QIFP/QIEFP VECR<3>

The bit 3 of the Volatile Enhanced Configuration Register determines whether it is possible to use the Vpp accelerating voltage to speed up the internal modify operation with the Quad program and erase instructions both in Extended or QIO-SPI protocols .

To use the Vpp voltage with the Quad I/O modify instructions, this bit must be set to The default value is 1, in which case the Vpp pin functionality is disabled in all Quad I/O operations both in Extended SPI and QIO-SPI protocols.

If the Volatile Enhanced Configuration Register bit 3 is set to 0, using the QIO-SPI protocol, after a Quad Command Page Program instruction or an Erase instruction is received with all input data in the Program case and the memory is de-selected, the protocol temporarily switches to Extended SPI protocol until Vpp passes from Vpph to normal I/O value this transition is mandatory to come back to QIO-SPI protocol , to enable the possibility to perform polling instructions to check if the internal modify cycle is finished by means of the WIP bit of the Status Register or of the Program/Erase controller bit of the Flag Status register or Program/Erase Suspend instruction even if the DQ2 pin is temporarily used in his Vpp functionality.

If the Volatile Enhanced Configuration Register bit 3 is set to 0, after any quad modify instruction both in Extended SPI protocol and QIO-SPI protocol , there is a maximum allowed time-out of 200 ms after the last instruction input is received and the memory is deselected to raise the Vpp signal to Vpph otherwise, the modify instruction starts at normal speed, without the Vpph enhancement, and a flag error appears on Flag Status Register bit

Output Driver Strength VECR<2:0>

The bits from 2 to 0 of the VECR set the value of the output driver strength, enabling to optimize the impedance at Vcc/2 output voltage for the specific application as described in Table Volatile Enhanced Configuration Register.

The default values of Output Driver Strength is set by the dedicated bits of the Non Volatile Configuration Register NVCR , the parts are delivered with the output impedance at Vcc/2 equal to 30 Ohms.
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Volatile and Non Volatile Registers

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Flag Status Register

The Flag Status Register is a powerful tool to investigate the status of the device, checking information regarding what is actually doing the memory and detecting possible error conditions.

The Flag status register is composed by 8 bit.Three bits Program/Erase Controller bit, Erase Suspend bit and Program Suspend bit are a “Status Indicator bit”, they are set and reset automatically by the memory. Four bits Erase error bit, Program error bit, VPP 1 to 0 error bit and Protection error bit are “Error Indicators bits”, they are set by the memory when some program or erase operation fails or the user tries to perform a forbidden operation. The user can clear the Error Indicators bits by mean of the Clear Flag Status Register CLFSR instruction.

All the Flag Status Register bits can be read by mean of the Read Status Register RFSR instruction.
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Volatile and Non Volatile Registers

Table BIT
7 6 5 4 3 2 1 0

Flag Status Register Description

P/E Controller not WIP Erase Suspend Erase Program VPP Program Suspend Protection RESERVED

Status Error Status Error

Note

P/E Controller Status bit

The bit 7 of the Flag Status register represents the Program/Erase Controller Status bit, It indicates whether there is a Program/Erase internal cycle active. When P/E Controller Status bit is Low FSR<7>=0 the device is busy when the bit is High FSR<7>=1 the device is ready to process a new command.

This bit has the same meaning of Write In Progress WIP bit of the standard SPI Status Register, but with opposite logic FSR<7> = not WIP

It's possible to make the polling instructions, to check if the internal modify operations are finished, both on the Flag Status register bit 7 or on WIP bit of the Status Register.

Erase Suspend Status bit

The bit 6 of the Flag Status register represents the Erase Suspend Status bit, It indicates that an Erase operation has been suspended or is going to be suspended.

The bit is set FSR<6>=1 within the Erase Suspend Latency time, that is as soon as the Program/Erase Suspend command PES has been issued, therefore the device may still complete the operation before entering the Suspend Mode.

The Erase Suspend Status should be considered valid when the P/E Controller bit is high FSR<7>=1 .

When a Program/Erase Resume command PER is issued the Erase Suspend Status bit returns Low FSR<6>=0

Erase Status bit

The bit 5 of the Flag Status Register represents the Erase Status bit. It indicates an erase failure or a protection error when an erase operation is issued.

When the Erase Status bit is High FSR<5>=1 after an Erase failure that means that the P/E Controller has applied the maximum pulses number to the portion to be erased and still failed to verify that it has correctly erased.

The Erase Status bit should be read once the P/E Controller Status bit is High.
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Volatile and Non Volatile Registers

N25Q128 - V
The second software protected mode SPM2 uses the Block Protect bits BP3, BP2, BP1, BP0 and the Top/Bottom bit TB bit to allow part of the memory to be configured as readonly. See Section 16 Ordering information.

Table Software protection truth table Sectors 0 to 255, 64 Kbyte

Sector Lock Register Lock Down bit Write Lock bit

Protection Status

Sector unprotected from Program/Erase/Write operations.

Sector protection status cannot be changed except by a power-up.

Sector protected from Program/Erase/Write operations.

Sector protection status cannot be changed except by a power-up.

As a second level of protection, the Write Protect signal applied on the W/VPP pin can freeze the Status Register in a read-only mode. In this mode, the Block Protect bits BP3, BP2, BP1, BP0 and the Status Register Write Disable bit SRWD are protected.
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Protection modes

N25Q128 - V

Table Protected area sizes TB bit = 0 Status Register Content

Memory Content

TB bit BP3 Bit PB2 Bit BP1 Bit BP0 Bit

Protected Area

Unprotected Area

None

All sectors 0 to 255

Upper 256th
1/2 Mbit, sector 255

Sectors 0 to 254

Upper 128th

Sectors 0 to 253
1 Mbit, 2 sectors 254 to 255

Upper 64th

Sectors 0 to 251
2 Mbit, 4 sectors 252 to 255

Upper 32nd

Sectors 0 to 247
4 Mbit, 8 sectors 248 to 255

Upper 16th

Sectors 0 to 239
8 Mbit, 16 sectors 240 to 255

Upper 8th

Sectors 0 to 223
16 Mbit, 32 sectors 224 to 255

Upper quarter

Lower 3 quarters sectors 0 to
32 Mbit, 64 sectors 193 to 255 191

Upper half
Reset functionality is available instead of Hold in devices with a dedicated part number. See Section 16 Ordering information.

Figure Quad Input/Output Fast Read instruction sequence

Mode 3 C Mode 0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 21 22 23 24 25 26 27

Instruction

Address 01234567

IO switches from Input to Output 4040 4

DQ1 DQ2

Don’t Care Don’t Care
5151 5 6 262 6

Note:
7373 7 ‘1’

A23-16 A15-8 A7-0 Dummy ex. 10

Byte 1 Byte 2

Quad_Output_Fast_Read

Quad I/O Fast Read

The Quad I/O Fast Read QIOFR instruction is very similar to the Quad Output Fast Read QOFR , except that the address bits are shifted in on four pins pin DQ0, pin DQ1, pin W/VPP/DQ2 and pin HOLD/DQ3 1 instead of only one.
Reset functionality is available instead of Hold in devices with a dedicated part number. See Section 16 Ordering information.
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Instructions

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Figure Quad Input/ Output Fast Read instruction sequence

Mode 3 C Mode 0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 21 22 23 24 25 26 27

Instruction
404040

IO switches from Input to Output 4040 4

DQ1 DQ2

Don’t Care Don’t Care
515151 626262
5151 5 6 262 6
737373 ‘1’
7373 7

A23-16 A15-8 A7-0 Dummy ex. 10

Byte 1 Byte 2

Quad_IO_Fast_Read

Read OTP ROTP

The device is first selected by driving Chip Select S Low. The instruction code for the Read OTP ROTP instruction is followed by a 3-byte address A23- A0 and a dummy byte. Each bit is latched in on the rising edge of Serial Clock C .

Then the memory contents at that address are shifted out on Serial Data output DQ1 .

Each bit is shifted out at the maximum frequency, fCmax, on the falling edge of Serial Clock C . The instruction sequence is shown in Figure

The address is automatically incremented to the next higher address after each byte of data is shifted out.

There is no rollover mechanism with the Read OTP ROTP instruction. This means that the Read OTP ROTP instruction must be sent with a maximum of 65 bytes to read. All other bytes outside the OTP area are “Don’t Care.”

The Read OTP ROTP instruction is terminated by driving Chip Select S High. Chip Select S can be driven High at any time during data output. Any Read OTP ROTP instruction issued while an Erase, Program or Write cycle is in progress, is rejected without having any effect on the cycle that is in progress.
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N25Q128 - V Figure Read OTP instruction and data-out sequence

Instructions

DQ0 DQ1
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31

Instruction High Impedance
24-bit address
23 22 21
3210

S 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

C Dummy cycles

DQ0 DQ1
76543210

DATA OUT 1 76543210 MSB

DATA OUT n
For devices with a dedicated part number, at the bottom or top of the addressable area there are 8 boot sectors, each one having 16 4Kbytes subsectors. See Section 16 Ordering information. The Subsector Erase SSE instruction sets to '1' FFh all bits inside the chosen subsector. Before it can be accepted, a Write Enable WREN instruction must previously have been executed.

Apart form the parallelizing of the instruction code and the address on the four pins DQ0, DQ1, DQ2 and DQ3, the instruction functionality is exactly the same as the Subsector Erase SSE instruction of the Extended SPI protocol, please refer to Section Subsector Erase SSE for further details.
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Instructions

Figure Subsector Erase instruction sequence QIO-SPI
0123456789 C

Instruction 24-Bit Address
20 16 12 8 4 0
21 17 13 9 5 1
22 18 14 10 6 2
23 19 15 11 7 3

Quad_Subsector_Erase

Sector Erase SE

The Sector Erase SE instruction sets to '1' FFh all bits inside the chosen sector. Before it can be accepted, a Write Enable WREN instruction must previously have been executed.

Apart form the parallelizing of the instruction code and the address on the four pins DQ0, DQ1, DQ2 and DQ3, the instruction functionality is exactly the same as the Sector Erase SE instruction of the Extended SPI protocol, please refer to Section Sector Erase SE for further details.

Figure Sector Erase instruction sequence QIO-SPI

S 0123456789

C Instruction 24-Bit Address
20 16 12 8 4 0
21 17 13 9 5 1
22 18 14 10 6 2
23 19 15 11 7 3

Quad_Sector_Erase
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Instructions

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Bulk Erase BE

The Bulk Erase BE instruction sets all bits to '1' FFh . Before it can be accepted, a Write Enable WREN instruction must previously have been executed.

Apart form the parallelizing of the instruction code on the four pins DQ0, DQ1, DQ2 and DQ3, the instruction functionality is exactly the same as the Bulk Erase BE instruction of the Extended SPI protocol, please refer to Section Bulk Erase BE for further details.

Figure Bulk Erase instruction sequence QIO-SPI
01 Instruction

Quad_Bulk_Erase

Program/Erase Suspend

The Program/Erase Suspend instruction allows the controller to interrupt a Program or an Erase instruction, in particular Sector Erase and Quad Command Page Program can be suspended and erased while that Subsector Erase, Bulk Erase, Write Non Volatile Configuration register and Program OTP can not be suspended.

Apart form the parallelizing of the instruction code on the four pins DQ0, DQ1, DQ2 and DQ3, the instruction functionality is exactly the same as the Program/Erase Suspend PES instruction of the Extended SPI protocol, please refer to Section Program/Erase Suspend for further details.
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Figure Program/Erase Suspend instruction sequence QIO-SPI S 01 C Instruction

Instructions

Quad_Program_Erase_Suspend
For devices with a feature set digit equal to 2 or 4 in the part number Basic XiP , it is not necessary to set the Volatile Configuration Register bit 3 to enter XIP mode it is possible to enter XIP mode directly by setting XIP Confirmation bit to 1 during the first dummy clock cycle after a fast read instruction.See Section 16 Ordering information.
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XIP Operations Figure N25Q128 Read functionality Flow Chart

Power On

NVCR Check

N25Q128 - V

Is XIP enabled ? Yes

No SPI standard mode no XiP, VCR <3> = 1

XIP mode

No Yes

XiP Confirmation bit = 0 ?

VCR<3> = 0 ?

SPI mode no XIP but Yes ready to enter XIP

No Read Instructions ?

XiP Confirmation
bit = 0 ?

Enter XIP mode by setting the Non Volatile Configuration Register

To use the Non Volatile Configuration Register method to enter in XIP mode it is necessary to set the Non Volatile Configuration Register bits from 11 to 9 with the pattern corresponding to the required XIP mode by mean of the Write Non Volatile Configuration Register WRNVCR instruction. See Table NVCR XIP bits setting example.

This instruction doesn't affect the XIP state until the next Power on sequence. In this case, after the next power on sequence, the memory directly accept addresses and then, after the dummy clock cycles configurable , outputs the data as described in Table NVCR XIP bits setting example. For example to enable fast POR and XIP on QIOFR in normal SPI protocol with six dummy clock cycles the following pattern must be issued:
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XIP Operations

Table NVCR XIP bits setting example

WRNVCR
+ 0110
opcode
6 dummy cycles for fast read instructions

XIP set as default Quad

I/O mode

Output Buffer driver strength
default

FAST POR enabled

Hold/Reset not disabled

Extended SPI protocol

Don’t Care

Figure XIP mode directly after power on

NVCR check XIP enabled

Vd tVSI <100u

Mode 3 C Mode 0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

IO switches from Input to Output
For devices with a feature set digit equal to 2 or 4 in the part number Basic XiP , it is not necessary to set the Volatile Configuration Register bit 3 to enter in XIP mode it is possible to enter directly in XIP mode by setting XIP Confirmation bit to 1 during the first dummy clock cycle after a fast read instruction. See Section 16 Ordering information.

Table VCR XIP bits setting example
81h WRVCR opcode
+ 0110
6 dummy cycles

Ready for XIP
000 Reserved
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XIP Operations

Figure XiP enter by VCR 2/2 QIOFR in normal SPI protocol example

Mode 3 C Mode 0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

Instruction
4 0 4 0 4 0 Xb

IO switches from Input to Output 4040 4

DQ1 DQ2

Don’t Care Don’t Care
515151 626262
5151 5 6 262 6

Note:
737373
7373 7
‘1’

A23-16 A15-8 A7-0 Dummy ex. 6

Byte 1 Byte 2

XIP_VCR

Xb is the XIP Confirmation bit, and it should be set to '0' to keep XIP state or '1' to exit XIP mode and return to standard read mode.

XIP mode hold and exit

The XIP mode does require at least one additional clock cycle to allow the XIP Confirmation bit to be sent to the memory on DQ0 during the first dummy clock cycle.

The device decodes the XIP Confirmation bit with the scheme - XIP Confirmation bit=0 means to hold XIP Mode - XIP Confirmation bit=1 means to exit XIP Mode and comes back to read mode, that
means codifying the first byte after the next chip select as an instruction code.

In Dual I/O XIP mode, the values of DQ1 during the first dummy clock cycle after the addresses is always Don't Care.

In Quad I/O XIP mode, the values of DQ3, DQ2 and DQ1 during the first dummy clock cycle after the addresses are always Don't Care.
In Dual and Single I/O XIP mode, in presence of the RESET pin enabled in devices with a dedicated part number , a low pulse on that pin resets the XIP protocol as defined by the Volatile Configuration Register, reporting the memory at the state of last power up, as defined by the Non Volatile Configuration Register. In Quad I/O XiP modes, it is possible to reset the memory for devices with a dedicated part number only when the device is deselected. See Section 16 Ordering information.
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XIP Operations

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XIP Memory reset after a controller reset
If during the application life the system controller is reset during operation, and the device features the RESET functionality in devices with a dedicated part number , and the feature has not been disabled, after the controller resets, the memory returns to POR state and there is no issue. See Section 16 Ordering information.

In all the other cases, it is possible to exit the memory from the XIP mode by sending the following rescue sequence at the first chip selection after a system reset:

DQ0= '1' for:
7 clock cycles within S low S becomes high before 8th clock cycle
+ 13 clock cycles within S low S becomes high before 14th clock cycle
+ 25 clock cycles within S low S becomes high before 26th clock cycle

The global effect is only to exit from XIP without any other reset.
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N25Q128 - V
11 Power-up and power-down

Power-up and power-down

At power-up and power-down, the device must not be selected that is Chip Select S must follow the voltage applied on VCC until VCC reaches the correct value - VCC min at power-up, and then for a further delay of tVSL - VSS at power-down

A safe configuration is provided in Section 3 SPI Modes.

To avoid data corruption and inadvertent write operations during power-up, a Power On Reset POR circuit is included. The logic inside the device is held reset while VCC is less than the Power On Reset POR threshold voltage, VWI - all operations are disabled, and the device does not respond to any instruction.

Moreover, the device ignores the Write Enable WREN instruction and all the modify instructions until a time delay of tPUW has elapsed after the moment that VCC rises above the VWI threshold. However, the correct operation of the device is not guaranteed if, by this time, VCC is still below VCC min . No Write Status Register, Program or Erase instructions should be sent until the later of - tPUW after VCC has passed the VWI threshold - tVSL after VCC has passed the VCC min level

These values are specified in Table Power-up timing and VWI threshold.

If the time, tVSL, has elapsed, after VCC rises above VCC min , the device can be selected for READ instructions even if the tPUW delay has not yet fully elapsed.

After power-up, the device is in the following state - The device is in the Standby Power mode not the Deep Power-down mode - The Write Enable Latch WEL bit is reset - The Write In Progress WIP bit is reset - The Lock Registers are configured as Write Lock bit, Lock Down bit =

Normal precautions must be taken for supply line decoupling, to stabilize the VCC supply.

Each device in a system should have the VCC line decoupled by a suitable capacitor close to the package pins generally, this capacitor is of the order of 100 nF .

At power-down, when VCC drops from the operating voltage, to below the Power On Reset POR threshold voltage, VWI, all operations are disabled and the device does not respond to any instruction the designer needs to be aware that if power-down occurs while a Write, Program or Erase cycle is in progress, some data corruption may result .

VPPH must be applied only when VCC is stable and in the VCC min to VCC max voltage range.
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Power-up and power-down Figure Power-up timing, Fast POR selected

N25Q128 - V

VCC max

Chip selection not allowed

WREN issued

VCC min

Chip reset VWI
tVTR

Polling allowed

SPI protocol WIP = 1 WEL = 0
tDTW

All read, WRCR, Polling WRECR allowed

Device fully accessible

Starting protocol defined by NVCR

WIP = 0 WEL = 0

WIP = 1 WEL = 1

WIP = 0 WEL = 1
time
Ordering information
16 Ordering information

N25Q128 - V

Note:

For further information on line items not listed here or on any aspect of this device, please contact your nearest Numonyx Sales Office.
Table Ordering information scheme Example:

N25Q128 A 1 B F8 4 0 E

Device type

N25Q = serial Flash memory, Quad I/O, XiP

Device density
128 = 128 Mbit

Technology

A = 65 nm

Feature set
1 = Byte addressability, Hold pin, Numonyx XiP 2 = Byte addressability, Hold pin, Basic XiP 3 = Byte addressability, Reset pin, Numonyx XiP 4 = Byte addressability, Reset pin, Basic XiP

Operating voltage
1 = VCC = V to 2 V

Block Structure

B = Bottom T = Top E = Uniform no boot sectors

Package

F8 = VDFPN8 8 x 6 mm MLP8 RoHS compliant SF = SO16 300 mils width RoHS compliant 12 = TBGA24 6 x 8 mm RoHS compliant

Temperature and test flow
4 = Industrial temperature range, to 85 °C Device tested with standard test flow

A = Automotive temperature range, to 125 °C Device tested with high reliability certified test flow

H = Industrial temperature range, to 85 °C Device tested with high reliability certified test flow

Security features 1
0 = No extra security

Packing options

E = Tray packing F = Tape and reel packing G = Tube packing

Additional secure options are available upon customer request.
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Ordering information

Table Valid Order Information Line Items

Block Structure

Package

Temperature and Test Flow

N25Q128A11BF840E N25Q128A11BF840F

N25Q128A21BF840E N25Q128A21BF840F

N25Q128A11TF840E N25Q128A11TF840F

Byte addressability, Hold pin, Numonyx XiP

Bottom

Byte addressability, Hold pin, Basic XiP

Bottom

Byte addressability, Hold pin, Numonyx XiP

VDFPN8 8x6 mm

VDFPN8 8x6 mm

VDFPN8 8x6 mm

Industrial temp Standard test flow

Industrial temp Standard test flow

Industrial temp Standard test flow

N25Q128A21TF840E N25Q128A21TF840F

N25Q128A11B1240E N25Q128A11B1240F

N25Q128A21B1240E N25Q128A21B1240F

Byte addressability, Hold pin, Basic XiP

Byte addressability, Hold pin, Numonyx XiP

Bottom

Byte addressability, Hold pin, Basic XiP

Bottom

VDFPN8 8x6 mm

TBGA24 6x8 mm

TBGA24 6x8 mm

Industrial temp Standard test flow

Industrial temp Standard test flow

Industrial temp Standard test flow

N25Q128A11T1240E N25Q128A11T1240F

N25Q128A21T1240E N25Q128A21T1240F

N25Q128A11BSF40F N25Q128A11BSF40G

Byte addressability, Hold pin, Numonyx XiP

Byte addressability, Hold pin, Basic XiP

Byte addressability, Hold pin, Numonyx XiP

Bottom

TBGA24 Industrial temp 6x8 mm Standard test flow

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Datasheet ID: N25Q128A31EF840E 648536