MT9VDDT6472PHG-40BF2

MT9VDDT6472PHG-40BF2 Datasheet

MT9VDDT1672PH I 128MB, MT9VDDT3272PH I 256MB, MT9VDDT6472PH I 512MB, MT9VDDT12872PH I 1GB

Part	Datasheet
MT9VDDT6472PHG-40BF2	MT9VDDT6472PHG-40BF2 (pdf)

Related Parts	Information
MT9VDDT6472PHG-335F2	MT9VDDT6472PHG-335F2
MT9VDDT6472PHY-40BF2	MT9VDDT6472PHY-40BF2
MT9VDDT1672PHG-335D2	MT9VDDT1672PHG-335D2
MT9VDDT3272PHG-335G2	MT9VDDT3272PHG-335G2
MT9VDDT3272PHG-265G2	MT9VDDT3272PHG-265G2

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128MB, 256MB, 512MB, 1GB x72, ECC, PLL, SR 200-PIN DDR SDRAM SODIMM DDR SDRAM SMALL-OUTLINE DIMM MT9VDDT1672PH I 128MB, MT9VDDT3272PH I 256MB, MT9VDDT6472PH I 512MB, MT9VDDT12872PH I 1GB For the lastest data sheet, please refer to the Web site: • 200-pin, small-outline, dual in-line memory module SODIMM • Supports ECC error detection and correction • Fast data transfer rates PC2100 and PC2700 • Utilizes 266 MT/s and 333 MT/s DDR SDRAM components • 128MB 16 Meg x 72 256MB 32 Meg x 72 512MB 64 Meg x 72 1GB 128 Meg x 72 • VDD = VDDQ = +2.5V • VDDSPD = +2.3V to +3.6V • 2.5V I/O SSTL_2 compatible • Commands entered on each positive CK edge • DQS edge-aligned with data for READs center- aligned with data for WRITEs • Internal, pipelined double data rate DDR architecture two data accesses per clock cycle • Four internal device banks for concurrent operation • Programmable burst lengths 2, 4, or 8 • Auto precharge option • Auto Refresh and Self Refresh Modes • 15.625µs 128MB , 7.8125µs 256MB, 512MB, 1GB maximum average periodic refresh interval • Serial Presence Detect SPD with EEPROM • Programmable READ CAS latency • Bidirectional data strobe DQS transmitted/re- ceived with source-synchronous data capture • Differential clock inputs CK and CK# • Gold edge contacts Figure 1 200-Pin SODIMM MO-224 Low Profile 1.25in. 31.75mm OPTIONS • Operating Temperature Range Commercial 0°C TA +70°C Industrial -40°C TA +85°C • Package 200-pin SODIMM standard 200-pin SODIMM lead-free • Memory Clock, Speed, CAS Latency2 6ns 267 MHz , 333 MT/s, CL = 7.5ns 133 MHz , 266 MT/s, CL = 2 7.5ns 133 MHz , 266 MT/s, CL = 2 7.5ns 133 MHz , 266 MT/s, CL = • PCB 1.25in. 31.75mm MARKING None I1 -335 -2621 -26A1 -265 NOTE: Consult Micron for product availability industrial temperature option available in -265 speed only. CL = Device CAS READ Latency. Table 1 Address Table Refresh Count Row Addressing DeviceBankAddressing Base Device Configuration Column Addressing Module Rank Addressing 128MB 4K 4 BA0, BA1 128Mb 16 Meg x 8 1K 1 S0# 256MB 8K 4 BA0, BA1 256Mb 32 Meg x 8 1K 1 S0# 512MB 8K 4 BA0, BA1 512Mb 64 Meg x 8 1K A11 1 S0# 8K 16K 4 BA0, BA1 1Gb 128 Meg x 8 2K A11 1 S0# 2004 Micron Technology, Inc. All rights reserved. AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 6, Burst Definition Table, on page Read Latency The READ latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The latency can be set to 2 or clocks, as shown in Figure 5, CAS Latency Diagram, on page Figure 4 Mode Register Definition Diagram 128MB Module BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mode Register Mx 0* 0* Operating Mode CAS Latency BT Burst Length * M13 and M12 BA0 and BA1 must be “0, 0” to select the base mode register vs. the extended mode register . 256MB and 512MB Modules BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mode Register Mx 0* 0* Operating Mode CAS Latency BT Burst Length * M14 and M13 BA0 and BA1 must be “0, 0” to select the base mode register vs. the extended mode register . 1GB Module BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mode Register Mx 0* 0* Operating Mode CAS Latency BT Burst Length * M15 and M14 BA1 and BA0 must be “0, 0” to select the base mode register vs. the extended mode register . Burst Length M2 M1 M0 0 00 0 01 0 10 0 11 1 00 1 01 1 10 1 11 M3 = 0 Reserved 2 4 8 Reserved Burst Type Sequential Interleaved M6 M5 M4 000 001 010 011 100 101 110 111 CAS Latency Reserved 2 Reserved M13 M12 M11 M10 M9 M8 M7 0 00 0 10 - - - - - -- M6-M0 Valid Operating Mode Normal Operation Normal Operation/Reset DLL All other states reserved Micron Technology, Inc., reserves the right to change products or specifications without notice. 2004 Micron Technology, Inc. All rights reserved. ADVANCE 128MB, 256MB, 512MB, 1GB x72, ECC, PLL, SR 200-PIN DDR SDRAM SODIMM Table 6 Burst Definition Table BURST LENGTH STARTING COLUMN ADDRESS ORDER OF ACCESSES WITHIN A BURST TYPE = TYPE = SEQUENTIAL INTERLEAVED

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128MB, 256MB, 512MB, 1GB x72, ECC, PLL, SR 200-PIN DDR SDRAM SODIMM

DDR SDRAM SMALL-OUTLINE DIMM

MT9VDDT1672PH I 128MB, MT9VDDT3272PH I 256MB, MT9VDDT6472PH I 512MB, MT9VDDT12872PH I 1GB

For the lastest data sheet, please refer to the

Web site:
• 200-pin, small-outline, dual in-line memory module SODIMM
• Supports ECC error detection and correction
• Fast data transfer rates PC2100 and PC2700
• Utilizes 266 MT/s and 333 MT/s DDR SDRAM
components
• 128MB 16 Meg x 72 256MB 32 Meg x 72 512MB
64 Meg x 72 1GB 128 Meg x 72
• VDD = VDDQ = +2.5V
• VDDSPD = +2.3V to +3.6V
• 2.5V I/O SSTL_2 compatible
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs center-
aligned with data for WRITEs
• Internal, pipelined double data rate DDR
architecture two data accesses per clock cycle
• Four internal device banks for concurrent operation
• Programmable burst lengths 2, 4, or 8
• Auto precharge option
• Auto Refresh and Self Refresh Modes
• 15.625µs 128MB , 7.8125µs 256MB, 512MB, 1GB
maximum average periodic refresh interval
• Serial Presence Detect SPD with EEPROM
• Programmable READ CAS latency
• Bidirectional data strobe DQS transmitted/re-
ceived with source-synchronous data capture
• Differential clock inputs CK and CK#
• Gold edge contacts

Figure 1 200-Pin SODIMM MO-224

Low Profile 1.25in. 31.75mm

OPTIONS
• Operating Temperature Range Commercial 0°C TA +70°C Industrial -40°C TA +85°C
• Package 200-pin SODIMM standard 200-pin SODIMM lead-free
• Memory Clock, Speed, CAS Latency2
6ns 267 MHz , 333 MT/s, CL = 7.5ns 133 MHz , 266 MT/s, CL = 2 7.5ns 133 MHz , 266 MT/s, CL = 2 7.5ns 133 MHz , 266 MT/s, CL =
• PCB 1.25in. 31.75mm

MARKING

None I1
-335 -2621 -26A1 -265

NOTE:

Consult Micron for product availability industrial temperature option available in -265 speed only.

CL = Device CAS READ Latency.

Table 1 Address Table

Refresh Count Row Addressing DeviceBankAddressing Base Device Configuration Column Addressing Module Rank Addressing
128MB
4K 4 BA0, BA1 128Mb 16 Meg x 8 1K
1 S0#
256MB
8K 4 BA0, BA1 256Mb 32 Meg x 8 1K
1 S0#
512MB
8K 4 BA0, BA1 512Mb 64 Meg x 8 1K A11
1 S0#
8K 16K 4 BA0, BA1 1Gb 128 Meg x 8 2K A11
1 S0#
2004 Micron Technology, Inc. All rights reserved.

AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS.
The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 6, Burst Definition Table, on page

Read Latency

The READ latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The latency can be set to 2 or clocks, as shown in Figure 5, CAS Latency Diagram, on page

Figure 4 Mode Register Definition Diagram
128MB Module

BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mode Register Mx 0* 0* Operating Mode CAS Latency BT Burst Length
* M13 and M12 BA0 and BA1 must be “0, 0” to select the base mode register vs. the extended mode register .
256MB and 512MB Modules

BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mode Register Mx 0* 0* Operating Mode CAS Latency BT Burst Length
* M14 and M13 BA0 and BA1 must be “0, 0” to select the base mode register vs. the extended mode register .
1GB Module

BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mode Register Mx
0* 0*

Operating Mode

CAS Latency BT Burst Length
* M15 and M14 BA1 and BA0 must be “0, 0” to select the base mode register vs. the extended mode register .

Burst Length

M2 M1 M0 0 00 0 01 0 10 0 11 1 00 1 01 1 10 1 11

M3 = 0 Reserved
2 4 8 Reserved

Burst Type

Sequential

Interleaved

M6 M5 M4 000 001 010 011 100 101 110 111

CAS Latency Reserved 2 Reserved

M13 M12 M11 M10 M9 M8 M7 0 00 0 10 - - - - - --

M6-M0 Valid

Operating Mode Normal Operation Normal Operation/Reset DLL All other states reserved

Micron Technology, Inc., reserves the right to change products or specifications without notice. 2004 Micron Technology, Inc. All rights reserved.

ADVANCE
128MB, 256MB, 512MB, 1GB x72, ECC, PLL, SR 200-PIN DDR SDRAM SODIMM

Table 6 Burst Definition Table

BURST LENGTH

STARTING COLUMN ADDRESS

ORDER OF ACCESSES WITHIN A BURST

TYPE =

TYPE =

SEQUENTIAL INTERLEAVED

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Datasheet ID: MT9VDDT6472PHG-40BF2 648508