MT9VDDT6472HIY-335F2

MT9VDDT6472HIY-335F2 Datasheet

MT9VDDT1672H 128MB, MT9VDDT3272H 256MB, MT9VDDT6472H 512MB, MT9VDDT12872H 1GB For the latest data sheet, please refer to the Web

Part	Datasheet
MT9VDDT6472HIY-335F2	MT9VDDT6472HIY-335F2 (pdf)

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128MB, 256MB, 512MB, 1GB x72, ECC, SR 200-PIN DDR SODIMM DDR SDRAM SMALL-OUTLINE DIMM MT9VDDT1672H 128MB, MT9VDDT3272H 256MB, MT9VDDT6472H 512MB, MT9VDDT12872H 1GB For the latest data sheet, please refer to the Web site: • 200-pin, small-outline, dual in-line memory module SODIMM • Supports ECC error detection and correction • Fast data transfer rates PC1600, PC2100, or PC2700 • Utilizes 200 MT/s, 266 MT/s, and 333 MT/s DDR SDRAM components • 128MB 16 Meg x 72 , 256MB 32 Meg x 72 , 512MB 64 Meg x 72 , and 1GB 128 Meg x 72 • VDD = VDDQ = +2.5V • VDDSPD = +2.3V to +3.6V • 2.5V I/O SSTL_2 compatible • Commands entered on each positive CK edge • DQS edge-aligned with data for READs center- aligned with data for WRITEs • Internal, pipelined double data rate DDR architecture two data accesses per clock cycle • Bidirectional data strobe DQS transmitted/ received with source-synchronous data capture • Differential clock inputs CK and CK# • Four internal device banks for concurrent operation • Programmable burst lengths 2, 4, or 8 • Auto precharge option • Auto Refresh and Self Refresh Modes • 15.625µs 128MB or 7.8125µs 256MB, 512MB, 1GB maximum average periodic refresh interval • Serial Presence Detect SPD with EEPROM • Programmable READ CAS latency • Gold edge contacts Figure 1 200-Pin SODIMM MO-224 1.25in. 31.75mm OPTIONS MARKING • Operating Temperature Range Commercial 0°C TA +70°C Industrial -40°C TA +85°C • Package None I2 200-pin SODIMM standard 200-pin SODIMM lead-free • Memory clock, Speed, CAS Latency1 6.0ns 167 MHz , 333 MT/s, CL = 7.5ns 133 MHz , 266 MT/s, CL = 2 7.5ns 133 MHz , 266 MT/s, CL = 2 -335 -2622 -26A2 7.5ns 133 MHz , 266 MT/s, CL = 10ns 100 MHz , 200 MT/s, CL = 2 -265 -2022 • PCB 1.25in. 31.75mm See page 2 note NOTE CL = Device CAS READ Latency. Consult Micron for product availability. Table 1 Address Table Refresh Count Row Addressing Device Bank Addressing Device Configuration Column Addressing Module Rank Addressing 128MB 256MB 512MB 4 BA0, BA1 4 BA0, BA1 4 BA0, BA1 128Mb 16 Meg x 8 256Mb 32 Meg x 8 512Mb 64 Meg x 8 1K 1 S0# 1K 1 S0# 2K A11 1 S0# The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 6, Burst Definition Table, on page Read Latency The READ latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The latency can be set to 2 or clocks, as shown in Figure 5, CAS Latency Diagram, on page If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available nominally coincident with clock edge n + m. Table 7, CAS Latency CL Table, indicates the operating fre- quencies at which each CAS latency setting can be used. Figure 4 Mode Register Definition Diagram 128MB Module BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mode Register Mx 0* 0* Operating Mode CAS Latency BT Burst Length * M13 and M12 BA0 and BA1 must be “0, 0” to select the base mode register vs. the extended mode register . 256MB and 512MB Modules BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mode Register Mx 0* 0* Operating Mode CAS Latency BT Burst Length * M14 and M13 BA0 and BA1 must be “0, 0” to select the base mode register vs. the extended mode register . 1GB Module BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mode Register Mx 0* 0* Operating Mode CAS Latency BT Burst Length * M15 and M14 BA1 and BA0 must be “0, 0” to select the base mode register vs. the extended mode register . Burst Length M2 M1 M0 0 00 0 01 0 10 0 11 1 00 1 01 1 10 1 11 M3 = 0 Reserved 2 4 8 Reserved Burst Type Sequential Interleaved M6 M5 M4 000 001 010 011 100 101 110 111 CAS Latency Reserved 2 Reserved M13 M12 M11 M10 M9 M8 M7 0 00 0 10 - - - - - -- M6-M0 Valid Operating Mode Normal Operation Normal Operation/Reset DLL All other states reserved Micron Technology, Inc., reserves the right to change products or specifications without notice. 2004 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB, 1GB x72, ECC, SR 200-PIN DDR SODIMM Table 6 Burst Definition Table BURST LENGTH STARTING COLUMN ADDRESS ORDER OF ACCESSES WITHIN A BURST TYPE = TYPE =

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128MB, 256MB, 512MB, 1GB x72, ECC, SR 200-PIN DDR SODIMM

DDR SDRAM SMALL-OUTLINE DIMM

MT9VDDT1672H 128MB, MT9VDDT3272H 256MB, MT9VDDT6472H 512MB, MT9VDDT12872H 1GB For the latest data sheet, please refer to the Web
site:
• 200-pin, small-outline, dual in-line memory module SODIMM
• Supports ECC error detection and correction
• Fast data transfer rates PC1600, PC2100, or PC2700
• Utilizes 200 MT/s, 266 MT/s, and 333 MT/s DDR

SDRAM components
• 128MB 16 Meg x 72 , 256MB 32 Meg x 72 , 512MB
64 Meg x 72 , and 1GB 128 Meg x 72
• VDD = VDDQ = +2.5V
• VDDSPD = +2.3V to +3.6V
• 2.5V I/O SSTL_2 compatible
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs center-
aligned with data for WRITEs
• Internal, pipelined double data rate DDR
architecture two data accesses per clock cycle
• Bidirectional data strobe DQS transmitted/
received with source-synchronous data capture
• Differential clock inputs CK and CK#
• Four internal device banks for concurrent operation
• Programmable burst lengths 2, 4, or 8
• Auto precharge option
• Auto Refresh and Self Refresh Modes
• 15.625µs 128MB or 7.8125µs 256MB, 512MB, 1GB maximum average periodic refresh interval
• Serial Presence Detect SPD with EEPROM
• Programmable READ CAS latency
• Gold edge contacts

Figure 1 200-Pin SODIMM MO-224
1.25in. 31.75mm

OPTIONS

MARKING
• Operating Temperature Range Commercial 0°C TA +70°C Industrial -40°C TA +85°C
• Package

None I2
200-pin SODIMM standard
200-pin SODIMM lead-free
• Memory clock, Speed, CAS Latency1
6.0ns 167 MHz , 333 MT/s, CL = 7.5ns 133 MHz , 266 MT/s, CL = 2 7.5ns 133 MHz , 266 MT/s, CL = 2
-335 -2622 -26A2
7.5ns 133 MHz , 266 MT/s, CL = 10ns 100 MHz , 200 MT/s, CL = 2
-265 -2022
• PCB
1.25in. 31.75mm

See page 2 note

NOTE CL = Device CAS READ Latency. Consult Micron for product availability.

Table 1 Address Table

Refresh Count Row Addressing Device Bank Addressing Device Configuration Column Addressing Module Rank Addressing
128MB
256MB
512MB
4 BA0, BA1
4 BA0, BA1
4 BA0, BA1
128Mb 16 Meg x 8 256Mb 32 Meg x 8 512Mb 64 Meg x 8
1K 1 S0#
1K 1 S0#
2K A11 1 S0#
The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 6, Burst Definition Table, on page

Read Latency

The READ latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The latency can be set to 2 or clocks, as shown in Figure 5, CAS Latency Diagram, on page

If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available nominally coincident with clock edge n + m. Table 7, CAS Latency CL Table, indicates the operating fre-
quencies at which each CAS latency setting can be used.

Figure 4 Mode Register Definition Diagram
128MB Module

BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mode Register Mx 0* 0* Operating Mode CAS Latency BT Burst Length
* M13 and M12 BA0 and BA1 must be “0, 0” to select the base mode register vs. the extended mode register .
256MB and 512MB Modules

BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mode Register Mx 0* 0* Operating Mode CAS Latency BT Burst Length
* M14 and M13 BA0 and BA1 must be “0, 0” to select the base mode register vs. the extended mode register .
1GB Module

BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mode Register Mx
0* 0*

Operating Mode

CAS Latency BT Burst Length
* M15 and M14 BA1 and BA0 must be “0, 0” to select the base mode register vs. the extended mode register .

Burst Length

M2 M1 M0 0 00 0 01 0 10 0 11 1 00 1 01 1 10 1 11

M3 = 0 Reserved
2 4 8 Reserved

Burst Type

Sequential

Interleaved

M6 M5 M4 000 001 010 011 100 101 110 111

CAS Latency Reserved 2 Reserved

M13 M12 M11 M10 M9 M8 M7 0 00 0 10 - - - - - --

M6-M0 Valid

Operating Mode Normal Operation Normal Operation/Reset DLL All other states reserved

Micron Technology, Inc., reserves the right to change products or specifications without notice. 2004 Micron Technology, Inc. All rights reserved.
128MB, 256MB, 512MB, 1GB x72, ECC, SR 200-PIN DDR SODIMM

Table 6 Burst Definition Table

BURST LENGTH

STARTING COLUMN ADDRESS

ORDER OF ACCESSES WITHIN A BURST

TYPE =

TYPE =

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Datasheet ID: MT9VDDT6472HIY-335F2 648507