MT8VDDT6464HDG-40BF2

MT8VDDT6464HDG-40BF2 Datasheet

MT8VDDT3264HD 256MB MT8VDDT6464HD 512MB

Part	Datasheet
MT8VDDT6464HDG-40BF2	MT8VDDT6464HDG-40BF2 (pdf)

Related Parts	Information
MT8VDDT6464HDG-335F2	MT8VDDT6464HDG-335F2

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256MB, 512MB x64, DR PC3200 200-PIN DDR SODIMM DDR SDRAM SMALLOUTLINE DIMM MT8VDDT3264HD 256MB MT8VDDT6464HD 512MB For the latest data sheet, please refer to the Web site: • 200-pin, small-outline, dual in-line memory module SODIMM • Fast data transfer rates PC3200 • Utilizes 400 MT/s DDR SDRAM components • 256MB 32 Meg x 64 or 512MB 64 Meg x 64 • VDD = VDDQ = +2.6V • VDDSPD = +2.3V to +3.6V • 2.6V I/O SSTL_2 compatible • Commands entered on each positive CK edge • DQS edge-aligned with data for READs center- aligned with data for WRITEs • Internal, pipelined double data rate DDR architecture two data accesses per clock cycle • Bidirectional data strobe DQS transmitted/received with source-synchronous data capture • Differential clock inputs CK and CK# • Four internal device banks for concurrent operation • Programmable burst lengths 2, 4, or 8 • Auto precharge option • Serial Presence Detect SPD with EEPROM • Programmable READ CAS latency • Auto Refresh and Self Refresh Modes • 7.8125µs maximum average periodic refresh interval • Gold edge contacts Figure 1 200-Pin SODIMM MO-224 1.25in. 31.75mm OPTIONS • Package 200-pin SODIMM standard 200-pin SODIMM lead-free 1 • Memory Clock, Speed, CAS Latency2 5ns 200 MHz , 400 MT/s, CL= 3 • PCB Standard 1.25in. 31.75mm MARKING -40B NOTE Consult Micron for product availability. CL = CAS READ Latency. Table 1 Address Table Refresh Count Row Addressing Device Bank Addressing Device Configuration Column Addressing Module Rank Addressing 256MB 8K 4 BA0, BA1 256Mb 16 Meg x 16 512 2 S0#, S1# 512MB 8K 4 BA0, BA1 512Mb 32 Meg x 16 1K 2 S0#, S1# 2004 Micron Technology, Inc. 256MB, 512MB x64, DR PC3200 200-PIN DDR SODIMM Table 2 Part Numbers and Timing Parameters MODULE CONFIGURATION MODULE MEMORY CLOCK/ LATENCY DENSITY BANDWIDTH DATA RATE CL - tRCD - tRP MT8VDDT3264HDG-40B__ MT8VDDT3264HDY-40B__ MT8VDDT6464HDG-40B__ MT8VDDT6464HDY-40B__ 256MB 512MB 32 Meg x 64 32 Meg x 64 Meg x 64 Meg x 64 GB/s GB/s GB/s GB/s 5ns/400 MT/s 5ns/400 MT/s 5ns/400 MT/s 5ns/400 MT/s The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Figure 6, Burst Definition Table, on page Read Latency The READ latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The latency can be set to 2, or 3 clocks, as shown in Figure 5, CAS Latency Diagram. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available nominally coincident with clock edge n + m. Table 7, CAS Latency CL Table, on page 9 indicates the operating frequencies at which each CAS latency setting can be used. 256MB, 512MB x64, DR PC3200 200-PIN DDR SODIMM Reserved states should not be used as unknown operation or incompatibility with future versions may result. Operating Mode The normal operating mode is selected by issuing a MODE REGISTER SET command with bits each set to zero, and bits set to the desired values. A DLL reset is initiated by issuing a MODE REGISTER SET command with bits A7 and each set to zero, bit A8 set to one, and bits set to the desired values. Although not required by the Micron device, JEDEC specifications recommend when a LOAD MODE REGISTER command is issued to reset the DLL, it should always be followed by a LOAD MODE REGISTER command to select normal operating mode. Figure 4 Mode Register Definition Diagram BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mode Register Mx 0* 0* Operating Mode CAS Latency BT Burst Length * M14 and M13 BA0 and BA1 must be “0, 0” to select the base mode register vs. the extended mode register . Burst Length M2 M1 M0 0 00 0 01 0 10 0 11 1 00 1 01 1 10 1 11 M3 = 0 Reserved 2 4 8 Reserved Burst Type Sequential Interleaved M6 M5 M4 000 001 010 011 100 101 110 111 CAS Latency Reserved 2 Reserved M13 M12 M11 M10 M9 M8 M7 0 00 0 10 - - - - - -- M6-M0 Valid Operating Mode Normal Operation Normal Operation/Reset DLL All other states reserved Micron Technology, Inc., reserves the right to change products or specifications without notice. 2004 Micron Technology, Inc. Table 6 Burst Definition Table STARTING BURST COLUMN ORDER OF ACCESSES WITHIN LENGTH ADDRESS A BURST TYPE = TYPE = SEQUENTIAL INTERLEAVED A1 A0 0-1-2-3 0-1-2-3 1-2-3-0 1-0-3-2 2-3-0-1 2-3-0-1 3-0-1-2

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256MB, 512MB x64, DR PC3200 200-PIN DDR SODIMM

DDR SDRAM SMALLOUTLINE DIMM

MT8VDDT3264HD 256MB MT8VDDT6464HD 512MB

For the latest data sheet, please refer to the Web site:
• 200-pin, small-outline, dual in-line memory module SODIMM
• Fast data transfer rates PC3200
• Utilizes 400 MT/s DDR SDRAM components
• 256MB 32 Meg x 64 or 512MB 64 Meg x 64
• VDD = VDDQ = +2.6V
• VDDSPD = +2.3V to +3.6V
• 2.6V I/O SSTL_2 compatible
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs center-
aligned with data for WRITEs
• Internal, pipelined double data rate DDR
architecture two data accesses per clock cycle
• Bidirectional data strobe DQS transmitted/received
with source-synchronous data capture
• Differential clock inputs CK and CK#
• Four internal device banks for concurrent operation
• Programmable burst lengths 2, 4, or 8
• Auto precharge option
• Serial Presence Detect SPD with EEPROM
• Programmable READ CAS latency
• Auto Refresh and Self Refresh Modes
• 7.8125µs maximum average periodic refresh
interval
• Gold edge contacts

Figure 1 200-Pin SODIMM MO-224
1.25in. 31.75mm

OPTIONS
• Package 200-pin SODIMM standard 200-pin SODIMM lead-free 1
• Memory Clock, Speed, CAS Latency2 5ns 200 MHz , 400 MT/s, CL= 3
• PCB Standard 1.25in. 31.75mm

MARKING
-40B

NOTE Consult Micron for product availability.

CL = CAS READ Latency.

Table 1 Address Table

Refresh Count Row Addressing Device Bank Addressing Device Configuration Column Addressing Module Rank Addressing
256MB
8K 4 BA0, BA1 256Mb 16 Meg x 16 512 2 S0#, S1#
512MB
8K 4 BA0, BA1 512Mb 32 Meg x 16 1K 2 S0#, S1#
2004 Micron Technology, Inc.
256MB, 512MB x64, DR PC3200 200-PIN DDR SODIMM

Table 2 Part Numbers and Timing Parameters

MODULE CONFIGURATION MODULE

MEMORY CLOCK/

LATENCY

DENSITY

BANDWIDTH

DATA RATE

CL - tRCD - tRP

MT8VDDT3264HDG-40B__ MT8VDDT3264HDY-40B__ MT8VDDT6464HDG-40B__ MT8VDDT6464HDY-40B__
256MB 512MB
32 Meg x 64 32 Meg x 64 Meg x 64 Meg x 64

GB/s GB/s GB/s GB/s
5ns/400 MT/s 5ns/400 MT/s 5ns/400 MT/s 5ns/400 MT/s
The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Figure 6, Burst Definition Table, on page

Read Latency

The READ latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The latency can be set to 2, or 3 clocks, as shown in Figure 5, CAS Latency Diagram.

If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available nominally coincident with clock edge n + m. Table 7, CAS Latency CL Table, on page 9 indicates the operating frequencies at which each CAS latency setting can be used.
256MB, 512MB x64, DR PC3200 200-PIN DDR SODIMM

Reserved states should not be used as unknown operation or incompatibility with future versions may result.

Operating Mode

The normal operating mode is selected by issuing a MODE REGISTER SET command with bits each set to zero, and bits set to the desired values. A DLL reset is initiated by issuing a MODE REGISTER SET command with bits A7 and each set to zero, bit A8 set to one, and bits set to the desired values. Although not required by the Micron device, JEDEC specifications recommend when a LOAD MODE REGISTER command is issued to reset the DLL, it should always be followed by a LOAD MODE REGISTER command to select normal operating mode.

Figure 4 Mode Register Definition Diagram

BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mode Register Mx 0* 0* Operating Mode CAS Latency BT Burst Length
* M14 and M13 BA0 and BA1 must be “0, 0” to select the base mode register vs. the extended mode register .

Burst Length

M2 M1 M0 0 00 0 01 0 10 0 11 1 00 1 01 1 10 1 11

M3 = 0 Reserved
2 4 8 Reserved

Burst Type

Sequential

Interleaved

M6 M5 M4 000 001 010 011 100 101 110 111

CAS Latency Reserved 2 Reserved

M13 M12 M11 M10 M9 M8 M7 0 00 0 10 - - - - - --

M6-M0 Valid

Operating Mode Normal Operation Normal Operation/Reset DLL All other states reserved

Micron Technology, Inc., reserves the right to change products or specifications without notice. 2004 Micron Technology, Inc.

Table 6 Burst Definition Table

STARTING

BURST COLUMN ORDER OF ACCESSES WITHIN

LENGTH ADDRESS

A BURST

TYPE =

TYPE =

SEQUENTIAL INTERLEAVED

A1 A0
0-1-2-3
0-1-2-3
1-2-3-0
1-0-3-2
2-3-0-1
2-3-0-1
3-0-1-2

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Datasheet ID: MT8VDDT6464HDG-40BF2 648490