MT8LSDT3264AY-133D2

MT8LSDT3264AY-133D2 Datasheet

MT8LSDT3264A I - 256MB MT16LSDT6464A I - 512MB

Part	Datasheet
MT8LSDT3264AY-133D2	MT8LSDT3264AY-133D2 (pdf)

Related Parts	Information
MT8LSDT3264AY-133G1	MT8LSDT3264AY-133G1
MT8LSDT3264AY-13EG1	MT8LSDT3264AY-13EG1
MT16LSDT6464AG-13ED2	MT16LSDT6464AG-13ED2
MT16LSDT6464AG-133D2	MT16LSDT6464AG-133D2
MT16LSDT6464AY-133D2	MT16LSDT6464AY-133D2
MT16LSDT6464AY-13ED2	MT16LSDT6464AY-13ED2
MT8LSDT3264AY-13ED2	MT8LSDT3264AY-13ED2

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256MB x64, SR , 512MB x64, DR 168-Pin SDRAM UDIMM Features Synchronous DRAM Module MT8LSDT3264A I - 256MB MT16LSDT6464A I - 512MB For the latest data sheet, please refer to the Web site: • PC100- and PC133-compliant • 168-pin, dual in-line memory module DIMM • Utilizes 125 MHz and 133 MHz SDRAM components • Unbuffered • 256MB 32 Meg x 64 , 512MB 64 Meg x 64 • Single +3.3V ±0.3V power supply • Fully synchronous all signals registered on positive edge of system clock • Internal pipelined operation column address can be changed every clock cycle • Internal SDRAM banks for hiding row access/ precharge • Programmable burst lengths 1, 2, 4, 8, or full page • Auto Precharge, including Concurrent Auto Precharge, and Auto Refresh Modes • 64ms, 8,192 cycle Auto Refresh cycle • Self Refresh Mode • LVTTL-compatible inputs and outputs • Serial Presence-Detect SPD • Gold edge contacts Table 1 Timing Parameters Module Marking -13E -133 -10E Clock Frequency 133 MHz 133 MHz 100 MHz Access Time CL = 2 5.4ns CL = 3 5.4ns 7.5ns Setup Time Hold Time Figure 1 168-Pin DIMM Low Profile 1.125in. 28.575mm Options • Package 168-pin DIMM standard 168-pin DIMM lead-free • Operating Temperature Range Commercial 0°C to +70°C Industrial -40°C to +85°C • Memory Clock/CAS Latency 133 MHz /CL = 2 133 MHz /CL = 3 100 MHz /CL = 2 • PCB Low profile 1.125in. 28.575mm Marking None I1, 2 -13E -133 -10E1 See page 2 note Notes Consult Micron for product availability. Industrial Temperature Option available in 133 speed only. Table 2 Address Table Refresh Count Device Banks Device Configuration Row Addressing Column Addressing Module Ranks 256MB 8K 4 BA0, BA1 256Mb 32 Meg x 8 8K 1K 1 S0,S2 512MB 8K The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 7, Burst Definitions, on page Micron Technology, Inc., reserves the right to change products or specifications without notice. 2003 Micron Technology, Inc. All rights reserved. 256MB x64, SR , 512MB x64, DR 168-Pin SDRAM UDIMM Mode Register Definition Figure 5: Mode Register Definition Diagram A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus 12 11 10 9 8 7 Reserved* WB Op Mode 6 543 CAS Latency BT 2 10 Burst Length Mode Register Mx *Should program M12, M11, M10 = “0, 0, 0” to ensure compatibility with future devices. M9 0 1 M2 M1 M0 0 00 0 01 0 10 0 11 1 00 1 01 1 10 1 11 Burst Length M3 = 0 1 2 4 8 Reserved Full Page M3 = 1 2 4 8 Reserved Burst Type Sequential Interleaved M6 M5 M4 0 00 0 01 0 10 0 11 1 00 1 01 1 10 1 11 CAS Latency Reserved 2 3 Reserved Operating Mode Defined Standard Operation All other states reserved Write Burst Mode Programmed Burst Length Single Location Access Micron Technology, Inc., reserves the right to change products or specifications without notice. 2003 Micron Technology, Inc. All rights reserved. 256MB x64, SR , 512MB x64, DR 168-Pin SDRAM UDIMM Mode Register Definition Table 7: Burst Definitions Burst Length Starting Column Address Order of Accesses Within a Burst Type = Sequential Type = Interleaved 8 Full Page n = location 0 - y The ordering of the accesses within a burst is determined by the burst length, the burst type, and the starting column adress, as shown in Table 7, Burst Definitions, The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to two or three clocks. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n + m. The DQs will start driving as a result of the clock edge one cycle earlier n + m - 1 , and provided that the relevant access times are met, the data will be valid by clock edge n + m. For example, assuming that the clock cycle time is such that all relevant access times are met, if a READ command is registered at T0 and the latency is programmed to two clocks, the DQs will start driving after T1 and the data will be valid by T2, as shown in Figure 6, CAS Latency Diagram. Table 8, CAS Latency Table, indicates the operating frequencies at which each CAS latency setting can be used. Reserved states should not be used as unknown operation or incompatibility with future versions may result. The normal operating mode is selected by setting M7 and M8 to zero the other combinations of values for M7 and M8 are reserved for future use and/or test modes. The programmed burst length applies to both READ and WRITE bursts. Micron Technology, Inc., reserves the right to change products or specifications without notice. 2003 Micron Technology, Inc. All rights reserved. 256MB x64, SR , 512MB x64, DR 168-Pin SDRAM UDIMM Commands Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. Write Burst Mode When M9 = 0, the burst length programmed via applies to both READ and WRITE bursts when M9 = 1, the programmed burst length applies to READ bursts, but write accesses are single-location nonburst accesses. Table 8 CAS Latency Table Speed -13E -133 -10E Allowable Operating Clock Frequency MHz CAS Latency = 2 133 100 CAS Latency = 3 143 133 NA Commands The Truth Table provides a quick reference of available commands. This is followed by written description of each command. For a more detailed descrip-tion of commands and operations, refer to the 256Mb SDRAM component data sheet. Table 9: Truth Table SDRAM Commands and DQMB Operation CKE is HIGH for all commands shown except SELF REFRESH notes appear following the Truth Table Name Function CS# RAS# CAS# WE# DQMB ADDR DQ Notes COMMAND INHIBIT NOP NO OPERATION NOP ACTIVE Select bank and activate row X Bank/Row X READ Select bank and column, and start READ burst L L/H Bank/Col X WRITE Select bank and column, and start WRITE burst L L/H Bank/Col Valid 2 BURST TERMINATE Active PRECHARGE Deactivate row in bank or banks Code AUTO REFRESH or SELF REFRESH Enter self refresh mode LOAD MODE REGISTER X Op-code X Write Enable/Output Enable Active 7 Write Inhibit/Output High-Z High-Z 7

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256MB x64, SR , 512MB x64, DR 168-Pin SDRAM UDIMM Features

Synchronous DRAM Module

MT8LSDT3264A I - 256MB MT16LSDT6464A I - 512MB

For the latest data sheet, please refer to the Web site:
• PC100- and PC133-compliant
• 168-pin, dual in-line memory module DIMM
• Utilizes 125 MHz and 133 MHz SDRAM
components
• Unbuffered
• 256MB 32 Meg x 64 , 512MB 64 Meg x 64
• Single +3.3V ±0.3V power supply
• Fully synchronous all signals registered on positive
edge of system clock
• Internal pipelined operation column address can
be changed every clock cycle
• Internal SDRAM banks for hiding row access/
precharge
• Programmable burst lengths 1, 2, 4, 8, or full page
• Auto Precharge, including Concurrent Auto

Precharge, and Auto Refresh Modes
• 64ms, 8,192 cycle Auto Refresh cycle
• Self Refresh Mode
• LVTTL-compatible inputs and outputs
• Serial Presence-Detect SPD
• Gold edge contacts

Table 1 Timing Parameters

Module Marking
-13E -133 -10E

Clock Frequency
133 MHz 133 MHz 100 MHz

Access Time

CL = 2
5.4ns

CL = 3
5.4ns 7.5ns

Setup Time

Hold Time

Figure 1 168-Pin DIMM

Low Profile 1.125in. 28.575mm

Options
• Package 168-pin DIMM standard 168-pin DIMM lead-free
• Operating Temperature Range Commercial 0°C to +70°C Industrial -40°C to +85°C
• Memory Clock/CAS Latency 133 MHz /CL = 2 133 MHz /CL = 3 100 MHz /CL = 2
• PCB Low profile 1.125in. 28.575mm

Marking

None I1, 2
-13E -133 -10E1

See page 2 note

Notes Consult Micron for product availability. Industrial Temperature Option available in 133 speed only.

Table 2 Address Table

Refresh Count Device Banks Device Configuration Row Addressing Column Addressing Module Ranks
256MB 8K
4 BA0, BA1 256Mb 32 Meg x 8
8K 1K
1 S0,S2
512MB 8K
The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 7, Burst Definitions, on page

Micron Technology, Inc., reserves the right to change products or specifications without notice. 2003 Micron Technology, Inc. All rights reserved.
256MB x64, SR , 512MB x64, DR 168-Pin SDRAM UDIMM Mode Register Definition

Figure 5:

Mode Register Definition Diagram

A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
12 11 10 9 8 7 Reserved* WB Op Mode
6 543 CAS Latency BT
2 10 Burst Length

Mode Register Mx
*Should program M12, M11, M10 = “0, 0, 0”
to ensure compatibility with future devices.

M9 0 1

M2 M1 M0 0 00 0 01 0 10 0 11 1 00 1 01 1 10 1 11

Burst Length

M3 = 0 1 2 4 8

Reserved Full Page

M3 = 1 2 4 8

Reserved

Burst Type

Sequential

Interleaved

M6 M5 M4 0 00 0 01 0 10 0 11 1 00 1 01 1 10 1 11

CAS Latency Reserved 2 3 Reserved

Operating Mode

Defined

Standard Operation

All other states reserved

Write Burst Mode Programmed Burst Length

Single Location Access

Micron Technology, Inc., reserves the right to change products or specifications without notice. 2003 Micron Technology, Inc. All rights reserved.
256MB x64, SR , 512MB x64, DR 168-Pin SDRAM UDIMM Mode Register Definition

Table 7:

Burst Definitions

Burst Length

Starting Column Address

Order of Accesses Within a Burst

Type = Sequential

Type = Interleaved
8 Full Page
n = location 0 - y
The ordering of the accesses within a burst is determined by the burst length, the burst type, and the starting column adress, as shown in Table 7, Burst Definitions,

The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to two or three clocks.

If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n + m. The DQs will start driving as a result of the clock edge one cycle earlier n + m - 1 , and provided that the relevant access times are met, the data will be valid by clock edge n + m. For example, assuming that the clock cycle time is such that all relevant access times are met, if a READ command is registered at T0 and the latency is programmed to two clocks, the DQs will start driving after T1 and the data will be valid by T2, as shown in Figure 6, CAS Latency Diagram. Table 8, CAS Latency Table, indicates the operating frequencies at which each CAS latency setting can be used.

Reserved states should not be used as unknown operation or incompatibility with future versions may result.

The normal operating mode is selected by setting M7 and M8 to zero the other combinations of values for M7 and M8 are reserved for future use and/or test modes. The programmed burst length applies to both READ and WRITE bursts.

Micron Technology, Inc., reserves the right to change products or specifications without notice. 2003 Micron Technology, Inc. All rights reserved.
256MB x64, SR , 512MB x64, DR 168-Pin SDRAM UDIMM Commands

Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result.

Write Burst Mode

When M9 = 0, the burst length programmed via applies to both READ and WRITE bursts when M9 = 1, the programmed burst length applies to READ bursts, but write accesses are single-location nonburst accesses.

Table 8 CAS Latency Table

Speed -13E -133 -10E

Allowable Operating Clock Frequency MHz

CAS Latency = 2
133 100

CAS Latency = 3 143 133 NA

Commands

The Truth Table provides a quick reference of available commands. This is followed by written description of each command. For a more detailed descrip-tion of commands and operations, refer to the 256Mb SDRAM component data sheet.

Table 9:

Truth Table SDRAM Commands and DQMB Operation CKE is HIGH for all commands shown except SELF REFRESH notes appear following the Truth Table

Name Function

CS# RAS# CAS# WE# DQMB ADDR DQ Notes

COMMAND INHIBIT NOP

NO OPERATION NOP

ACTIVE Select bank and activate row

X Bank/Row X

READ Select bank and column, and start READ burst L

L/H Bank/Col X

WRITE Select bank and column, and start WRITE burst L

L/H Bank/Col Valid 2

BURST TERMINATE

Active

PRECHARGE Deactivate row in bank or banks

Code

AUTO REFRESH or SELF REFRESH Enter self refresh mode

LOAD MODE REGISTER

X Op-code X

Write Enable/Output Enable

Active 7

Write Inhibit/Output High-Z

High-Z 7

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Datasheet ID: MT8LSDT3264AY-133D2 648480