MT48LC8M32B2F5-7 IT TR
MT48LC8M32B2F5-7 IT TR Datasheet
MT48LC8M32B2 - 2 MEG x 32 x 4 BANKS
| Part | Datasheet |
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MT48LC8M32B2F5-7 IT TR |
MT48LC8M32B2F5-7 IT TR (pdf) |
| Related Parts | Information |
|---|---|
MT48LC8M32B2P-7 IT TR |
MT48LC8M32B2P-7 IT TR |
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MT48LC8M32B2B5-7 TR |
MT48LC8M32B2B5-7 TR |
MT48LC8M32B2P-7 TR |
MT48LC8M32B2P-7 TR |
MT48LC8M32B2TG-6 TR |
MT48LC8M32B2TG-6 TR |
MT48LC8M32B2TG-7 IT TR |
MT48LC8M32B2TG-7 IT TR |
MT48LC8M32B2TG-7 TR |
MT48LC8M32B2TG-7 TR |
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MT48LC8M32B2B5-6 TR |
MT48LC8M32B2B5-6 TR |
MT48LC8M32B2P-6 TR |
MT48LC8M32B2P-6 TR |
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MT48LC8M32B2F5-7 TR |
MT48LC8M32B2F5-7 TR |
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MT48LC8M32B2F5-6 TR |
MT48LC8M32B2F5-6 TR |
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MT48LC8M32B2B5-7 IT TR |
MT48LC8M32B2B5-7 IT TR |
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MT48LC8M32B2B5-7 |
MT48LC8M32B2B5-7 |
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MT48LC8M32B2F5-7 IT |
MT48LC8M32B2F5-7 IT |
| PDF Datasheet Preview |
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| SYNCHRONOUS DRAM 256Mb x32 SDRAM MT48LC8M32B2 - 2 MEG x 32 x 4 BANKS For the latest data sheet, please refer to the Micron Web site: • PC100 functionality • Fully synchronous all signals registered on positive edge of system clock • Internal pipelined operation column address can be changed every clock cycle • Internal banks for hiding row access/precharge • Programmable burst lengths 1, 2, 4, 8, or full page • Auto Precharge, includes Concurrent Auto Precharge, and Auto Refresh Modes • Self Refresh Mode • 64ms, 4,096-cycle refresh 15.6µs/row • LVTTL-compatible inputs and outputs • Single +3.3V ±0.3V power supply • Supports CAS latency of 1, 2, and 3 Options Configuration • 8 Meg x 32 2 Meg x 32 x 4 banks Package • 86-pin TSOP 400 mil • 86-pin TSOP 400 mil lead-free • 90-ball FBGA 8mm x 13mm • 90-ball FBGA 8mm x 13mm leadfree Timing Cycle Time • 6ns 166 MHz • 7ns 143 MHz Operating Temperature Range • Commercial 0°C to +70°C • Industrial -40°C to +85°C Marking 8M32B2 TG P F5 B5 -6 -7 None IT1 NOTE Available on -7 only. Table 1 Key Timing Parameters SPEED CLOCK GRADE FREQUENCY 166 MHz 143 MHz ACCESS TIME CL = 3* 5.5ns 6.0ns SETUP TIME 1.5ns 2ns HOLD TIME *CL = CAS READ latency Figure 1 Pin Assignment Top View 86-Pin TSOP VDDQ VSSQ VDDQ VSSQ DQM0 CAS# RAS# DQM2 DQ16 VSSQ Accesses within a given burst may be programmed to be either sequential or interleaved this is referred to as the burst type and is selected via bit M3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table Figure 4 Mode Register Definition BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved* WB Op Mode CAS Latency BT Burst length Mode Register Mx *Should be programmed to “0” to ensure compatibility with future devices. M2 M1M0 000 001 010 011 100 101 110 111 Burst Length M3 = 0 1 2 4 8 Reserved Full Page M3 = 1 2 4 8 Reserved Burst Type Sequential Interleave M6 M5 M4 00 001 010 011 100 101 110 111 CAS Latency Reserved Reserved Reserved Reserved Reserved 256Mb x32 SDRAM Table 4 Burst Definition ORDER OF ACCESSES WITHIN A BURST STARTING BURST COLUMN LENGTH ADDRESS TYPE = TYPE = SEQUENTIAL INTERLEAVED Full Page 512 A0 0 1 A1 A0 00 01 10 11 A2 A1 A0 000 001 010 011 100 101 110 111 n = Location 0-1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 Cn, Cn + 1, Cn + 2, Cn + 3, Cn + ...Cn-1, Cn... 0-1-0 |
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