MT48H8M32LFF5-8 IT TR

MT48H8M32LFF5-8 IT TR Datasheet

MT48LC8M32LF, MT48V8M32LF, MT48H8M32LF - 2 Meg x 32 x 4 banks

Part	Datasheet
MT48H8M32LFF5-8 IT TR	MT48H8M32LFF5-8 IT TR (pdf)

Related Parts	Information
MT48H8M32LFF5-10 TR	MT48H8M32LFF5-10 TR
MT48LC8M32LFF5-8 IT	MT48LC8M32LFF5-8 IT
MT48H8M32LFF5-10 IT TR	MT48H8M32LFF5-10 IT TR
MT48LC8M32LFF5-8 TR	MT48LC8M32LFF5-8 TR
MT48LC8M32LFF5-8	MT48LC8M32LFF5-8
MT48LC8M32LFF5-8 IT TR	MT48LC8M32LFF5-8 IT TR
MT48H8M32LFF5-8	MT48H8M32LFF5-8
MT48H8M32LFF5-8 IT	MT48H8M32LFF5-8 IT
MT48H8M32LFF5-8 TR	MT48H8M32LFF5-8 TR
MT48H8M32LFF5-10	MT48H8M32LFF5-10
MT48H8M32LFF5-10 IT	MT48H8M32LFF5-10 IT
MT48V8M32LFB5-8 TR	MT48V8M32LFB5-8 TR
MT48LC8M32LFB5-8 IT TR	MT48LC8M32LFB5-8 IT TR
MT48LC8M32LFB5-8 TR	MT48LC8M32LFB5-8 TR
MT48V8M32LFB5-8 IT TR	MT48V8M32LFB5-8 IT TR

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256Mb x32 Mobile SDRAM Features Mobile SDRAM MT48LC8M32LF, MT48V8M32LF, MT48H8M32LF - 2 Meg x 32 x 4 banks For the latest data sheet, refer to Micron’s Web site: • Low voltage power supply • Partial array self refresh power-saving mode • Temperature Compensated Self Refresh TCSR • Deep power-down mode • Programmable output drive strength • Fully synchronous all signals registered on positive edge of system clock • Internal pipelined operation column address can be changed every clock cycle • Internal banks for hiding row access/precharge • Programmable burst lengths 1, 2, 4, 8, or full page • Auto precharge, includes concurrent auto precharge, and auto refresh modes • Self-refresh mode standard and low power • 64ms, 4,096-cycle refresh • LVTTL-compatible inputs and outputs • Commercial and industrial temperature ranges • Supports CAS latency of 1, 2, 3 Table 1 Addressing Configuration Refresh Count Row Addressing Bank Addressing Column Addressing 8 Meg x 32 2 Meg x 32 x 4 banks 4K 4K 4 BA0, BA1 512 Options • VDD/VDDQ • 3.3V/3.3V • 2.5V/2.5V • 1.8V/1.8V • Configurations • 8 Meg x 32 2 Meg x 32 x 4 banks • Package/Ballout • 90-ball VFBGA 8mm x 13mm Standard • 90-ball VFBGA 8mm x 13mm Lead-free • Timing Cycle Time • 7.5ns CL = 3 133 MHz • 7.5ns CL = 2 104 MHz • 8ns CL = 3 125 MHz • 8ns CL = 2 104 Mhz • 10ns CL = 3 100 MHz • 10ns CL = 2 83 Mhz • Operating Temperature Range • Commercial 0° to +70°C • Industrial -40°C to +85°C Marking LC V H 8M32 -75 -75 -8 -8 -10 -10 None IT Table 2 Key Timing Parameters CL = CAS READ latency Speed Grade -75 -8 -10 -75 -8 -10 Clock Frequency 133 MHz 125 MHz 100 MHz 133 MHz 104 MHz 83 MHz Access Time Setup Hold CL = 2 CL = 3 Time 6ns 2.5ns 1ns 7ns 2.5ns 1ns 7ns 2.5ns 1ns 2.5ns 1ns 2.5ns 1ns 2.5ns 1ns Micron Technology, Inc., reserves the right to change products or specifications without notice. 2003 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 256Mb x32 Mobile SDRAM Table of Contents Table of Contents Accesses within a given burst may be programmed to be either sequential or interleaved this is referred to as the burst type and is selected via bit M3. The ordering of accesses within a burst is determined by the burst length, the burst type, and the starting column address, as shown in Table Micron Technology, Inc., reserves the right to change products or specifications without notice. 2003 Micron Technology, Inc. All rights reserved. 256Mb x32 Mobile SDRAM Register Definition Figure 3 Mode Register Definition BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus M13 M12 M11 M10 M9 M8 M7 M6 M5 M4 M3 M2 M1 M0 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved* WB Op Mode CAS Latency BT Burst Length Mode Register Mx *Should program M10 = “0, 0” to ensure compatibility with future devices. M2 M1 M0 000 001 010 011 100 101 110 111 Burst Length M3 = 0 1 2 4 8 Reserved Full Page M3 = 1 2 4 8 Reserved Burst Type Sequential Interleaved M6 M5 M4 00 0 00 1 01 0 01 1 10 0 10 1 11 0 11 1 CAS Latency Reserved 1 2 3 Reserved M6-M0 Operating Mode Defined Standard Operation All other states reserved Write Burst Mode Programmed Burst Length Single Location Access Micron Technology, Inc., reserves the right to change products or specifications without notice. 2003 Micron Technology, Inc. All rights reserved. 256Mb x32 Mobile SDRAM Register Definition Table 5 Burst Definition Table Burst Length Starting Column Address Full Page y n = A0-A11/9/8 location 0-y Order of Accesses Within a Burst Type = Sequential Type = Interleaved 0-1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 Cn, Cn + 1, Cn + 2 Cn + 3, Cn + - 1,

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256Mb x32 Mobile SDRAM Features

Mobile SDRAM

MT48LC8M32LF, MT48V8M32LF, MT48H8M32LF - 2 Meg x 32 x 4 banks

For the latest data sheet, refer to Micron’s Web site:
• Low voltage power supply
• Partial array self refresh power-saving mode
• Temperature Compensated Self Refresh TCSR
• Deep power-down mode
• Programmable output drive strength
• Fully synchronous all signals registered on positive
edge of system clock
• Internal pipelined operation column address can
be changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths 1, 2, 4, 8, or full page
• Auto precharge, includes concurrent auto
precharge, and auto refresh modes
• Self-refresh mode standard and low power
• 64ms, 4,096-cycle refresh
• LVTTL-compatible inputs and outputs
• Commercial and industrial temperature ranges
• Supports CAS latency of 1, 2, 3

Table 1 Addressing

Configuration Refresh Count Row Addressing Bank Addressing Column Addressing
8 Meg x 32
2 Meg x 32 x 4 banks 4K
4K 4 BA0, BA1 512

Options
• VDD/VDDQ
• 3.3V/3.3V
• 2.5V/2.5V
• 1.8V/1.8V
• Configurations
• 8 Meg x 32 2 Meg x 32 x 4 banks
• Package/Ballout
• 90-ball VFBGA 8mm x 13mm

Standard
• 90-ball VFBGA 8mm x 13mm

Lead-free
• Timing Cycle Time
• 7.5ns CL = 3 133 MHz
• 7.5ns CL = 2 104 MHz
• 8ns CL = 3 125 MHz
• 8ns CL = 2 104 Mhz
• 10ns CL = 3 100 MHz
• 10ns CL = 2 83 Mhz
• Operating Temperature Range
• Commercial 0° to +70°C
• Industrial -40°C to +85°C

Marking

LC V H
8M32
-75 -75 -8 -8 -10 -10

None IT

Table 2 Key Timing Parameters

CL = CAS READ latency

Speed Grade
-75 -8 -10 -75 -8 -10

Clock Frequency
133 MHz 125 MHz 100 MHz 133 MHz 104 MHz 83 MHz

Access Time Setup Hold

CL = 2 CL = 3 Time
6ns 2.5ns 1ns
7ns 2.5ns 1ns
7ns 2.5ns 1ns
2.5ns 1ns
2.5ns 1ns
2.5ns 1ns

Micron Technology, Inc., reserves the right to change products or specifications without notice. 2003 Micron Technology, Inc. All rights reserved.

Products and specifications discussed herein are subject to change by Micron without notice.
256Mb x32 Mobile SDRAM Table of Contents

Table of Contents
Accesses within a given burst may be programmed to be either sequential or interleaved this is referred to as the burst type and is selected via bit M3. The ordering of accesses within a burst is determined by the burst length, the burst type, and the starting column address, as shown in Table

Micron Technology, Inc., reserves the right to change products or specifications without notice. 2003 Micron Technology, Inc. All rights reserved.
256Mb x32 Mobile SDRAM Register Definition

Figure 3 Mode Register Definition

BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Address Bus

M13 M12 M11 M10 M9 M8 M7 M6 M5 M4 M3 M2 M1 M0
13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved* WB Op Mode CAS Latency BT Burst Length

Mode Register Mx
*Should program M10 = “0, 0”
to ensure compatibility with future devices.

M2 M1 M0 000 001 010 011 100 101 110 111

Burst Length

M3 = 0 1 2 4 8

Reserved Full Page

M3 = 1 2 4 8

Reserved

Burst Type

Sequential

Interleaved

M6 M5 M4 00 0 00 1 01 0 01 1 10 0 10 1 11 0 11 1

CAS Latency Reserved 1 2 3 Reserved

M6-M0

Operating Mode

Defined Standard Operation

All other states reserved

Write Burst Mode

Programmed Burst Length

Single Location Access

Micron Technology, Inc., reserves the right to change products or specifications without notice. 2003 Micron Technology, Inc. All rights reserved.
256Mb x32 Mobile SDRAM Register Definition

Table 5 Burst Definition Table

Burst Length Starting Column Address

Full Page y
n = A0-A11/9/8 location 0-y

Order of Accesses Within a Burst Type = Sequential Type = Interleaved
0-1-0
0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2
0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6

Cn, Cn + 1, Cn + 2

Cn + 3, Cn + - 1,

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived MT48H8M32LFF5-8ITTR Datasheet file may be downloaded here without warranties.

Datasheet ID: MT48H8M32LFF5-8ITTR 648460