MT47H64M16BT-3:A TR

MT47H64M16BT-3:A TR Datasheet

MT47H256M4 32 Meg x 4 x 8 banks MT47H128M8 16 Meg x 8 x 8 banks MT47H64M16 8 Meg x 16 x 8 banks

Part	Datasheet
MT47H64M16BT-3:A TR	MT47H64M16BT-3:A TR (pdf)

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1Gb x4, x8, x16 DDR2 SDRAM Features DDR2 SDRAM MT47H256M4 32 Meg x 4 x 8 banks MT47H128M8 16 Meg x 8 x 8 banks MT47H64M16 8 Meg x 16 x 8 banks For the latest data sheet, refer to Micron’s Web site: • RoHS compliant • VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V • JEDEC standard 1.8V I/O SSTL_18-compatible • Differential data strobe DQS, DQS# option • 4-bit prefetch architecture • Duplicate output strobe RDQS option for x8 • DLL to align DQ and DQS transitions with CK • 8 internal banks for concurrent operation • Programmable CAS latency CL • Posted CAS additive latency AL • WRITE latency = READ latency 1 tCK • Programmable burst lengths 4 or 8 • Adjustable data-output drive strength • 64ms, 8,192-cycle refresh • On-die termination ODT • Industrial temperature IT option • Supports JEDEC clock jitter specification Options Marking • Configuration 256 Meg x 4 32 Meg x 4 x 8 banks 128 Meg x 8 16 Meg x 8 x 8 banks 64 Meg x 16 8 Meg x 16 x 8 banks • FBGA package lead-free 92-ball FBGA 11mm x 19mm :A 84-ball FBGA 10mm x 16.5mm :D 68-ball FBGA 10mm x 16.5mm :D • Timing cycle time 5.0ns CL = 3 DDR2-400 3.75ns CL = 4 DDR2-533 3.0ns CL = 5 DDR2-667 3.0ns CL = 4 DDR2-667 2.5ns CL = 6 DDR2-800 2.5ns CL = 5 DDR2-800 • Self refresh Standard Low-power • Operating temperature Commercial 0°C TC 85°C Industrial TC 95°C TA 85°C 256M4 128M8 64M16 BT B7 -5E -37E -3 -3E -25 -25E None L None IT :A/:D Table 1 Configuration Addressing Architecture 256 Meg x 4 128 Meg x 8 64 Meg x 16 Configuration 32 Meg x 4 16 Meg x 4 8 Meg x 16 x 8 banks x 8 banks x 8 banks Refresh Count Row Addr. 16K 8K Bank Addr. 8 Column Addr. 2K A11 1K Table 2 Key Timing Parameters Speed Data Rate MHz tRCD tRP tRC Grade CL = 3 CL = 4 CL = 5 CL = 6 ns -5E 400 N/A N/A 15 55 -37E 400 533 N/A N/A 15 55 -3 400 533 667 N/A 15 55 -3E N/A 667 N/A 12 54 -25 N/A N/A 667 800 15 55 -25E N/A 533 800 N/A 55 Note CL = CAS latency. Micron Technology, Inc., reserves the right to change products or specifications without notice. 2004 Micron Technology, Inc. All rights reserved. 1Gb x4, x8, x16 DDR2 SDRAM Table of Contents Table of Contents Features Part Numbers FBGA Part Marking Decoder. General Description Industrial Temperature. General Notes Ball Assignment and Description Functional Description State Diagram. Initialization Mode Register MR Burst Length Burst Type Operating Mode DLL RESET Write Recovery Power-Down Mode CAS Latency CL Extended Mode Register EMR DLL Enable/Disable Output Drive Strength DQS# Enable/Disable. RDQS Enable/Disable Output Enable/Disable On-Die Termination ODT Off-Chip Driver OCD Impedance Calibration Posted CAS Additive Latency AL Extended Mode Register Extended Mode Register Command Truth Tables. DESELECT, NOP, and LM Commands DESELECT NO OPERATION NOP . LOAD MODE LM Bank/Row Activation ACTIVE Command ACTIVE Operation READ Command READ Operation WRITE Command WRITE Operation PRECHARGE Command PRECHARGE Operation SELF REFRESH Command REFRESH Command Power-Down Mode. Precharge Power-Down Clock Frequency Change RESET Function. CKE LOW Anytime ODT Timing MRS Command to ODT Update Delay Micron Technology, Inc., reserves the right to change products or specifications without notice. 2004 Micron Technology, Inc. All rights reserved. 1Gb x4, x8, x16 DDR2 SDRAM Table of Contents Accesses within a given burst may be programmed to be either sequential or interleaved. The burst type is selected via bit M3, as shown in Figure The ordering of accesses within a burst is determined by the burst length, the burst type, and the starting column address, as shown in Table 5 on page DDR2 SDRAM supports 4-bit burst mode and 8bit burst mode only. For 8-bit burst mode, full, interleaved address ordering is supported however, sequential address ordering is nibble-based. Micron Technology, Inc., reserves the right to change products or specifications without notice. 2004 Micron Technology, Inc. All rights reserved. 1Gb x4, x8, x16 DDR2 SDRAM Mode Register MR Table 5: Burst Definition Starting Column Address Burst Length A2, A1, A0 010 011 100 101 110 111 Order of Accesses Within a Burst Burst Type = Sequential 0, 1, 2, 3 1, 2, 3, 0 2, 3, 0, 1 3, 0, 1, 2 0, 1, 2, 3, 4, 5, 6, 7 1, 2, 3, 0, 5, 6, 7, 4 2, 3, 0, 1, 6, 7, 4, 5 3, 0, 1, 2, 7, 4, 5, 6 4, 5, 6, 7, 0, 1, 2, 3 5, 6, 7, 4, 1, 2, 3, 0 6, 7, 4, 5, 2, 3, 0, 1 7, 4, 5, 6, 3, 0, 1, 2 Burst Type = Interleaved 0, 1, 2, 3 1, 0, 3, 2, 3, 0, 1 3, 2, 1, 0, 1, 2, 3, 4, 5, 6, 7 1, 0, 3, 2, 5, 4, 7, 6 2, 3, 0, 1, 6, 7, 4, 5 3, 2, 1, 0, 7, 6, 5, 4, 5, 6, 7, 0, 1, 2, 3 5, 4, 7, 6, 1, 0, 3, 2 6, 7, 4, 5, 2, 3, 0, 1 7, 6, 5, 4, 3, 2, 1, 0 Operating Mode The normal operating mode is selected by issuing a command with bit M7 set to “0,” and all other bits set to the desired values, as shown in Figure 11 on page When bit M7 is “1,” no other bits of the mode register are programmed. Programming bit M7 to “1” places the DDR2 SDRAM into a test mode that is only used by the manufacturer and should not be used. No operation or functionality is guaranteed if M7 bit is DLL RESET DLL RESET is defined by bit M8, as shown in Figure 11 on page Programming bit M8 to “1” will activate the DLL RESET function. Bit M8 is self-clearing, meaning it returns back to a value of “0” after the DLL RESET function has been issued. Anytime the DLL RESET function is used, 200 clock cycles must occur before a READ command can be issued to allow time for the internal clock to be synchronized with the external clock. Failing to wait for synchronization to occur may result in a violation of the tAC or tDQSCK parameters. Write Recovery Write recovery WR time is defined by bits as shown in Figure 11 on page The WR register is used by the DDR2 SDRAM during WRITE with auto precharge operation. During WRITE with auto precharge operation, the DDR2 SDRAM delays the internal auto precharge operation by WR clocks programmed in bits from the last data burst. An example of WRITE with auto precharge is shown in Figure 43 on page WR values of 2, 3, 4, 5, or 6 clocks may be used for programming bits The user is required to program the value of WR, which is calculated by dividing tWR in nanoseconds by tCK in nanoseconds and rounding up a noninteger value to the next integer WR [cycles] = tWR [ns] / tCK [ns]. Reserved states should not be used as unknown operation or incompatibility with future versions may result. Micron Technology, Inc., reserves the right to change products or specifications without notice. 2004 Micron Technology, Inc. All rights reserved. 1Gb x4, x8, x16 DDR2 SDRAM Mode Register MR Power-Down Mode Active power-down PD mode is defined by bit M12, as shown in Figure 11 on page PD mode allows the user to determine the active power-down mode, which determines performance versus power savings. PD mode bit M12 does not apply to precharge PD mode. When bit M12 = 0, standard active PD mode, or “fast-exit” active PD mode, is enabled. The tXARD parameter is used for fast-exit active PD exit timing. The DLL is expected to be enabled and running during this mode. When bit M12 = 1, a lower-power active PD mode, or “slow-exit” active PD mode, is enabled. The tXARDS parameter is used for slow-exit active PD exit timing. The DLL can be enabled but “frozen” during active PD mode since the exit-to-READ command timing is relaxed. The power difference expected between IDD3P normal and IDD3P low-power mode is defined in Table 45 on page CAS Latency CL The CAS latency CL is defined by bits as shown in Figure 11 on page CL is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The CL can be set to 3, 4, 5, or 6 clocks, depending on the speed grade option being used. DDR2 SDRAM does not support any half-clock latencies. Reserved states should not be used as unknown operation or incompatibility with future versions may result. DDR2 SDRAM also supports a feature called posted CAS additive latency AL . This feature allows the READ command to be issued prior to tRCD MIN by delaying the internal command to the DDR2 SDRAM by AL clocks. The AL feature is described in more detail in “Posted CAS Additive Latency AL ” on page Examples of CL = 3 and CL = 4 are shown in Figure 12 on page 28 both assume AL = If a READ command is registered at clock edge n, and the CL is m clocks, the data will be available nominally coincident with clock edge n + m this assumes AL = Micron Technology, Inc., reserves the right to change products or specifications without notice. 2004 Micron Technology, Inc. All rights reserved. Figure 12 CAS Latency CL COMMAND READ DQS, DQS# DQ CL = 3 AL = 0 CK# CK COMMAND DQS, DQS#

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1Gb x4, x8, x16 DDR2 SDRAM Features

DDR2 SDRAM

MT47H256M4 32 Meg x 4 x 8 banks MT47H128M8 16 Meg x 8 x 8 banks MT47H64M16 8 Meg x 16 x 8 banks

For the latest data sheet, refer to Micron’s Web site:
• RoHS compliant
• VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V
• JEDEC standard 1.8V I/O SSTL_18-compatible
• Differential data strobe DQS, DQS# option
• 4-bit prefetch architecture
• Duplicate output strobe RDQS option for x8
• DLL to align DQ and DQS transitions with CK
• 8 internal banks for concurrent operation
• Programmable CAS latency CL
• Posted CAS additive latency AL
• WRITE latency = READ latency 1 tCK
• Programmable burst lengths 4 or 8
• Adjustable data-output drive strength
• 64ms, 8,192-cycle refresh
• On-die termination ODT
• Industrial temperature IT option
• Supports JEDEC clock jitter specification

Options

Marking
• Configuration 256 Meg x 4 32 Meg x 4 x 8 banks 128 Meg x 8 16 Meg x 8 x 8 banks 64 Meg x 16 8 Meg x 16 x 8 banks
• FBGA package lead-free 92-ball FBGA 11mm x 19mm :A 84-ball FBGA 10mm x 16.5mm :D 68-ball FBGA 10mm x 16.5mm :D
• Timing cycle time 5.0ns CL = 3 DDR2-400 3.75ns CL = 4 DDR2-533 3.0ns CL = 5 DDR2-667 3.0ns CL = 4 DDR2-667 2.5ns CL = 6 DDR2-800 2.5ns CL = 5 DDR2-800
• Self refresh Standard Low-power
• Operating temperature Commercial 0°C TC 85°C Industrial TC 95°C TA 85°C
256M4 128M8 64M16

BT B7
-5E -37E
-3 -3E -25 -25E

None L

None IT
:A/:D

Table 1 Configuration Addressing

Architecture 256 Meg x 4 128 Meg x 8 64 Meg x 16

Configuration 32 Meg x 4 16 Meg x 4 8 Meg x 16 x 8 banks x 8 banks x 8 banks

Refresh Count

Row Addr. 16K 8K

Bank Addr. 8

Column Addr. 2K A11 1K

Table 2 Key Timing Parameters

Speed

Data Rate MHz
tRCD tRP tRC

Grade CL = 3 CL = 4 CL = 5 CL = 6 ns
-5E 400 N/A N/A 15 55 -37E 400 533 N/A N/A 15 55
-3 400 533 667 N/A 15 55 -3E N/A 667 N/A 12 54 -25 N/A N/A 667 800 15 55 -25E N/A 533 800 N/A 55

Note CL = CAS latency.

Micron Technology, Inc., reserves the right to change products or specifications without notice. 2004 Micron Technology, Inc. All rights reserved.
1Gb x4, x8, x16 DDR2 SDRAM Table of Contents

Table of Contents

Features Part Numbers FBGA Part Marking Decoder. General Description

Industrial Temperature. General Notes Ball Assignment and Description Functional Description State Diagram. Initialization Mode Register MR Burst Length Burst Type Operating Mode DLL RESET Write Recovery Power-Down Mode CAS Latency CL Extended Mode Register EMR DLL Enable/Disable Output Drive Strength DQS# Enable/Disable. RDQS Enable/Disable Output Enable/Disable On-Die Termination ODT Off-Chip Driver OCD Impedance Calibration Posted CAS Additive Latency AL Extended Mode Register Extended Mode Register Command Truth Tables. DESELECT, NOP, and LM Commands DESELECT NO OPERATION NOP . LOAD MODE LM Bank/Row Activation ACTIVE Command ACTIVE Operation READ Command READ Operation WRITE Command WRITE Operation PRECHARGE Command PRECHARGE Operation SELF REFRESH Command REFRESH Command Power-Down Mode. Precharge Power-Down Clock Frequency Change RESET Function. CKE LOW Anytime ODT Timing MRS Command to ODT Update Delay

Micron Technology, Inc., reserves the right to change products or specifications without notice. 2004 Micron Technology, Inc. All rights reserved.
1Gb x4, x8, x16 DDR2 SDRAM Table of Contents
Accesses within a given burst may be programmed to be either sequential or interleaved. The burst type is selected via bit M3, as shown in Figure The ordering of accesses within a burst is determined by the burst length, the burst type, and the starting column address, as shown in Table 5 on page DDR2 SDRAM supports 4-bit burst mode and 8bit burst mode only. For 8-bit burst mode, full, interleaved address ordering is supported however, sequential address ordering is nibble-based.

Micron Technology, Inc., reserves the right to change products or specifications without notice. 2004 Micron Technology, Inc. All rights reserved.
1Gb x4, x8, x16 DDR2 SDRAM Mode Register MR

Table 5:

Burst Definition

Starting Column Address

Burst Length A2, A1, A0
010 011 100 101 110 111

Order of Accesses Within a Burst

Burst Type = Sequential
0, 1, 2, 3 1, 2, 3, 0 2, 3, 0, 1 3, 0, 1, 2 0, 1, 2, 3, 4, 5, 6, 7 1, 2, 3, 0, 5, 6, 7, 4 2, 3, 0, 1, 6, 7, 4, 5 3, 0, 1, 2, 7, 4, 5, 6 4, 5, 6, 7, 0, 1, 2, 3 5, 6, 7, 4, 1, 2, 3, 0 6, 7, 4, 5, 2, 3, 0, 1 7, 4, 5, 6, 3, 0, 1, 2

Burst Type = Interleaved
0, 1, 2, 3 1, 0, 3, 2, 3, 0, 1 3, 2, 1, 0, 1, 2, 3, 4, 5, 6, 7 1, 0, 3, 2, 5, 4, 7, 6 2, 3, 0, 1, 6, 7, 4, 5 3, 2, 1, 0, 7, 6, 5, 4, 5, 6, 7, 0, 1, 2, 3 5, 4, 7, 6, 1, 0, 3, 2 6, 7, 4, 5, 2, 3, 0, 1 7, 6, 5, 4, 3, 2, 1, 0

Operating Mode

The normal operating mode is selected by issuing a command with bit M7 set to “0,” and all other bits set to the desired values, as shown in Figure 11 on page When bit M7 is “1,” no other bits of the mode register are programmed. Programming bit M7 to “1” places the DDR2 SDRAM into a test mode that is only used by the manufacturer and should not be used. No operation or functionality is guaranteed if M7 bit is

DLL RESET

DLL RESET is defined by bit M8, as shown in Figure 11 on page Programming bit M8 to “1” will activate the DLL RESET function. Bit M8 is self-clearing, meaning it returns back to a value of “0” after the DLL RESET function has been issued.

Anytime the DLL RESET function is used, 200 clock cycles must occur before a READ command can be issued to allow time for the internal clock to be synchronized with the external clock. Failing to wait for synchronization to occur may result in a violation of the tAC or tDQSCK parameters.

Write Recovery

Write recovery WR time is defined by bits as shown in Figure 11 on page The WR register is used by the DDR2 SDRAM during WRITE with auto precharge operation. During WRITE with auto precharge operation, the DDR2 SDRAM delays the internal auto precharge operation by WR clocks programmed in bits from the last data burst. An example of WRITE with auto precharge is shown in Figure 43 on page

WR values of 2, 3, 4, 5, or 6 clocks may be used for programming bits The user is required to program the value of WR, which is calculated by dividing tWR in nanoseconds by tCK in nanoseconds and rounding up a noninteger value to the next integer WR [cycles] = tWR [ns] / tCK [ns]. Reserved states should not be used as unknown operation or incompatibility with future versions may result.

Micron Technology, Inc., reserves the right to change products or specifications without notice. 2004 Micron Technology, Inc. All rights reserved.
1Gb x4, x8, x16 DDR2 SDRAM Mode Register MR

Power-Down Mode

Active power-down PD mode is defined by bit M12, as shown in Figure 11 on page PD mode allows the user to determine the active power-down mode, which determines performance versus power savings. PD mode bit M12 does not apply to precharge PD mode.

When bit M12 = 0, standard active PD mode, or “fast-exit” active PD mode, is enabled. The tXARD parameter is used for fast-exit active PD exit timing. The DLL is expected to be enabled and running during this mode.

When bit M12 = 1, a lower-power active PD mode, or “slow-exit” active PD mode, is enabled. The tXARDS parameter is used for slow-exit active PD exit timing. The DLL can be enabled but “frozen” during active PD mode since the exit-to-READ command timing is relaxed. The power difference expected between IDD3P normal and IDD3P low-power mode is defined in Table 45 on page

CAS Latency CL

The CAS latency CL is defined by bits as shown in Figure 11 on page CL is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The CL can be set to 3, 4, 5, or 6 clocks, depending on the speed grade option being used.

DDR2 SDRAM does not support any half-clock latencies. Reserved states should not be used as unknown operation or incompatibility with future versions may result.

DDR2 SDRAM also supports a feature called posted CAS additive latency AL . This feature allows the READ command to be issued prior to tRCD MIN by delaying the internal command to the DDR2 SDRAM by AL clocks. The AL feature is described in more detail in “Posted CAS Additive Latency AL ” on page

Examples of CL = 3 and CL = 4 are shown in Figure 12 on page 28 both assume AL = If a READ command is registered at clock edge n, and the CL is m clocks, the data will be available nominally coincident with clock edge n + m this assumes AL =

Micron Technology, Inc., reserves the right to change products or specifications without notice. 2004 Micron Technology, Inc. All rights reserved.

Figure 12 CAS Latency CL

COMMAND

READ

DQS, DQS#

DQ CL = 3 AL = 0

CK# CK

COMMAND

DQS, DQS#

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Datasheet ID: MT47H64M16BT-3:ATR 648455