MT47H64M8CB-25:B TR

MT47H64M8CB-25:B TR Datasheet

MT47H128M4 32 Meg x 4 x 4 banks MT47H64M8 16 Meg x 8 x 4 banks MT47H32M16 8 Meg x 16 x 4 banks

Part	Datasheet
MT47H64M8CB-25:B TR	MT47H64M8CB-25:B TR (pdf)

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PDF Datasheet Preview
512Mb x4, x8, x16 DDR2 SDRAM Features DDR2 SDRAM MT47H128M4 32 Meg x 4 x 4 banks MT47H64M8 16 Meg x 8 x 4 banks MT47H32M16 8 Meg x 16 x 4 banks • Vdd = +1.8V ±0.1V, VddQ = +1.8V ±0.1V • JEDEC-standard 1.8V I/O SSTL_18-compatible • Differential data strobe DQS, DQS# option • 4n-bit prefetch architecture • Duplicate output strobe RDQS option for x8 • DLL to align DQ and DQS transitions with CK • 4 internal banks for concurrent operation • Programmable CAS latency CL • Posted CAS additive latency AL • WRITE latency = READ latency - 1 tCK • Selectable burst lengths 4 or 8 • Adjustable data-output drive strength • 64ms, 8,192-cycle refresh • On-die termination ODT • Industrial temperature IT option • Automotive temperature AT option • RoHS compliant • Supports JEDEC clock jitter specification Options1 Marking • Configuration 256 Meg x 4 32 Meg x 4 x 4 banks 128 Meg x 8 16 Meg x 8 x 4 banks 64 Meg x 16 8 Meg x 16 x 4 banks • Timing cycle time 2.5ns CL = 5 DDR2-800 2.5ns CL = 6 DDR2-800 3.0ns CL = 4 DDR2-667 3.0ns CL = 5 DDR2-667 3.75ns CL = 4 DDR2-533 5.0ns CL = 3 DDR2-400 • Self refresh Standard Low-power • Operating temperature Commercial 0°C TC 85°C Industrial TC 95°C; 128M4 64M8 32M16 CC BN HR CB B6 CF GC FN HW GB F6 JN -25E -25 -3E -3 -37E -5E None L None IT :B/:D/:F Note: Not all options listed can be combined to define an offered product. Use the Part Catalog Search on for product offerings and availability. Micron Technology, Inc. reserves the right to change products or specifications without notice. 2004 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 512Mb x4, x8, x16 DDR2 SDRAM Features Table 1 Key Timing Parameters Speed Grade -25E -25 -3E -3 -37E -5E CL = 3 400 Data Rate MT/s CL = 4 CL = 5 CL = 6 800 800 n/a n/a n/a n/a tRC ns 55 54 55 Table 2 Addressing Parameter Configuration Refresh count Row address Bank address Column address 128 Meg x 4 32 Meg x 4 x 4 banks 8K A[13:0] 16K Accesses within a given burst may be programmed to be either sequential or interleaved. The burst type is selected via bit M3, as shown in Figure 38 page The ordering of accesses within a burst is determined by the burst length, the burst type, Micron Technology, Inc. reserves the right to change products or specifications without notice. 2004 Micron Technology, Inc. All rights reserved. 512Mb x4, x8, x16 DDR2 SDRAM Mode Register MR and the starting column address, as shown in Table 40 page DDR2 SDRAM supports 4-bit burst mode and 8-bit burst mode only. For 8-bit burst mode, full interleaved address ordering is supported however, sequential address ordering is nibble-based. Micron Technology, Inc. reserves the right to change products or specifications without notice. 2004 Micron Technology, Inc. All rights reserved. 512Mb x4, x8, x16 DDR2 SDRAM Mode Register MR Table 40 Burst Definition Burst Length 4 Starting Column Address A2, A1, A0 00 01 10 11 000 001 010 011 100 101 110 111 Order of Accesses Within a Burst Burst Type = Sequential Burst Type = Interleaved 0, 1, 2, 3 0, 1, 2, 3 1, 2, 3, 0 1, 0, 3, 2 2, 3, 0, 1 2, 3, 0, 1 3, 0, 1, 2 3, 2, 1, 0 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 1, 2, 3, 0, 5, 6, 7, 4 1, 0, 3, 2, 5, 4, 7, 6 2, 3, 0, 1, 6, 7, 4, 5 2, 3, 0, 1, 6, 7, 4, 5 3, 0, 1, 2, 7, 4, 5, 6 3, 2, 1, 0, 7, 6, 5, 4 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 5, 6, 7, 4, 1, 2, 3, 0 5, 4, 7, 6, 1, 0, 3, 2 6, 7, 4, 5, 2, 3, 0, 1 6, 7, 4, 5, 2, 3, 0, 1 7, 4, 5, 6, 3, 0, 1, 2 7, 6, 5, 4, 3, 2, 1, 0 Operating Mode The normal operating mode is selected by issuing a command with bit M7 set to “0,” and all other bits set to the desired values, as shown in Figure 38 page When bit M7 is “1,” no other bits of the mode register are programmed. Programming bit M7 to “1” places the DDR2 SDRAM into a test mode that is only used by the manufacturer and should not be used. No operation or functionality is guaranteed if M7 bit is DLL RESET DLL RESET is defined by bit M8, as shown in Figure 38 page Programming bit M8 to “1” will activate the DLL RESET function. Bit M8 is self-clearing, meaning it returns back to a value of “0” after the DLL RESET function has been issued. Anytime the DLL RESET function is used, 200 clock cycles must occur before a READ command can be issued to allow time for the internal clock to be synchronized with the external clock. Failing to wait for synchronization to occur may result in a violation of the tAC or tDQSCK parameters. Micron Technology, Inc. reserves the right to change products or specifications without notice. 2004 Micron Technology, Inc. All rights reserved. 512Mb x4, x8, x16 DDR2 SDRAM Mode Register MR

PDF Datasheet Preview

512Mb x4, x8, x16 DDR2 SDRAM Features

DDR2 SDRAM

MT47H128M4 32 Meg x 4 x 4 banks MT47H64M8 16 Meg x 8 x 4 banks MT47H32M16 8 Meg x 16 x 4 banks
• Vdd = +1.8V ±0.1V, VddQ = +1.8V ±0.1V
• JEDEC-standard 1.8V I/O SSTL_18-compatible
• Differential data strobe DQS, DQS# option
• 4n-bit prefetch architecture
• Duplicate output strobe RDQS option for x8
• DLL to align DQ and DQS transitions with CK
• 4 internal banks for concurrent operation
• Programmable CAS latency CL
• Posted CAS additive latency AL
• WRITE latency = READ latency - 1 tCK
• Selectable burst lengths 4 or 8
• Adjustable data-output drive strength
• 64ms, 8,192-cycle refresh
• On-die termination ODT
• Industrial temperature IT option
• Automotive temperature AT option
• RoHS compliant
• Supports JEDEC clock jitter specification

Options1

Marking
• Configuration 256 Meg x 4 32 Meg x 4 x 4 banks 128 Meg x 8 16 Meg x 8 x 4 banks 64 Meg x 16 8 Meg x 16 x 4 banks
• Timing cycle time 2.5ns CL = 5 DDR2-800 2.5ns CL = 6 DDR2-800 3.0ns CL = 4 DDR2-667 3.0ns CL = 5 DDR2-667 3.75ns CL = 4 DDR2-533 5.0ns CL = 3 DDR2-400
• Self refresh Standard Low-power
• Operating temperature

Commercial 0°C TC 85°C Industrial TC 95°C;
128M4 64M8 32M16

CC BN HR

CB B6 CF

GC FN HW

GB F6 JN
-25E -25 -3E -3 -37E -5E

None L

None IT
:B/:D/:F

Note:

Not all options listed can be combined to define an offered product. Use the Part Catalog Search on for product offerings and availability.

Micron Technology, Inc. reserves the right to change products or specifications without notice. 2004 Micron Technology, Inc. All rights reserved.

Products and specifications discussed herein are subject to change by Micron without notice.
512Mb x4, x8, x16 DDR2 SDRAM Features

Table 1 Key Timing Parameters

Speed Grade
-25E -25 -3E -3 -37E -5E

CL = 3 400

Data Rate MT/s

CL = 4

CL = 5

CL = 6 800
800 n/a n/a n/a n/a
tRC ns
55 54 55

Table 2 Addressing

Parameter

Configuration Refresh count Row address Bank address Column address
128 Meg x 4 32 Meg x 4 x 4 banks
8K A[13:0] 16K
Accesses within a given burst may be programmed to be either sequential or interleaved. The burst type is selected via bit M3, as shown in Figure 38 page The ordering of accesses within a burst is determined by the burst length, the burst type,

Micron Technology, Inc. reserves the right to change products or specifications without notice. 2004 Micron Technology, Inc. All rights reserved.
512Mb x4, x8, x16 DDR2 SDRAM Mode Register MR
and the starting column address, as shown in Table 40 page DDR2 SDRAM supports 4-bit burst mode and 8-bit burst mode only. For 8-bit burst mode, full interleaved address ordering is supported however, sequential address ordering is nibble-based.

Micron Technology, Inc. reserves the right to change products or specifications without notice. 2004 Micron Technology, Inc. All rights reserved.
512Mb x4, x8, x16 DDR2 SDRAM Mode Register MR

Table 40 Burst Definition

Burst Length 4

Starting Column Address A2, A1, A0
00 01 10 11 000 001 010 011 100 101 110 111

Order of Accesses Within a Burst

Burst Type = Sequential

Burst Type = Interleaved
0, 1, 2, 3
0, 1, 2, 3
1, 2, 3, 0
1, 0, 3, 2
2, 3, 0, 1
2, 3, 0, 1
3, 0, 1, 2
3, 2, 1, 0
0, 1, 2, 3, 4, 5, 6, 7
0, 1, 2, 3, 4, 5, 6, 7
1, 2, 3, 0, 5, 6, 7, 4
1, 0, 3, 2, 5, 4, 7, 6
2, 3, 0, 1, 6, 7, 4, 5
2, 3, 0, 1, 6, 7, 4, 5
3, 0, 1, 2, 7, 4, 5, 6
3, 2, 1, 0, 7, 6, 5, 4
4, 5, 6, 7, 0, 1, 2, 3
4, 5, 6, 7, 0, 1, 2, 3
5, 6, 7, 4, 1, 2, 3, 0
5, 4, 7, 6, 1, 0, 3, 2
6, 7, 4, 5, 2, 3, 0, 1
6, 7, 4, 5, 2, 3, 0, 1
7, 4, 5, 6, 3, 0, 1, 2
7, 6, 5, 4, 3, 2, 1, 0

Operating Mode

The normal operating mode is selected by issuing a command with bit M7 set to “0,” and all other bits set to the desired values, as shown in Figure 38 page When bit M7 is “1,” no other bits of the mode register are programmed. Programming bit M7 to “1” places the DDR2 SDRAM into a test mode that is only used by the manufacturer and should not be used. No operation or functionality is guaranteed if M7 bit is

DLL RESET

DLL RESET is defined by bit M8, as shown in Figure 38 page Programming bit M8 to “1” will activate the DLL RESET function. Bit M8 is self-clearing, meaning it returns back to a value of “0” after the DLL RESET function has been issued.

Anytime the DLL RESET function is used, 200 clock cycles must occur before a READ command can be issued to allow time for the internal clock to be synchronized with the external clock. Failing to wait for synchronization to occur may result in a violation of the tAC or tDQSCK parameters.

Micron Technology, Inc. reserves the right to change products or specifications without notice. 2004 Micron Technology, Inc. All rights reserved.
512Mb x4, x8, x16 DDR2 SDRAM Mode Register MR

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Datasheet ID: MT47H64M8CB-25:BTR 648451