MT47H32M16BT-3:A TR

MT47H32M16BT-3:A TR Datasheet

Example Part Number MT47H64M8FT-37E

Part	Datasheet
MT47H32M16BT-3:A TR	MT47H32M16BT-3:A TR (pdf)

Related Parts	Information
MT47H128M4BT-37E:A TR	MT47H128M4BT-37E:A TR
MT47H32M16BT-37E:A TR	MT47H32M16BT-37E:A TR

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DDR2 SDRAM 512Mb x4, x8, x16 DDR2 SDRAM MEG X 4 X 4 BANKS MEG X 8 X 4 BANKS MEG X 16 X 4 BANKS For the latest data sheet, please refer to the Micron Web site: • VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V • JEDEC standard 1.8V I/O SSTL_18-compatible • Differential data strobe DQS, DQS# option • Four-bit prefetch architecture • Duplicate output strobe RDQS option for x8 configuration • DLL to align DQ and DQS transitions with CK • Four internal banks for concurrent operation • Programmable CAS Latency CL 3 and 4 • Posted CAS additive latency AL 0, 1, 2, 3, and 4 • WRITE latency = READ latency - 1 tCK • Programmable burst lengths 4 or 8 • Adjustable data-output drive strength • 64ms, 8,192-cycle refresh • On-die termination ODT Options • Configuration 128 Meg x 4 32 Meg x 4 x 4 banks 64 Meg x 8 16 Meg x 8 x 4 banks 32 Meg x 16 8 Meg x 16 x 4 banks • FBGA Package Lead-Free 92-ball FBGA 11mm x 19mm • Timing Cycle Time 5.0ns CL = 3 DDR2-400 3.75ns CL = 4 DDR2-533 Designation 128M4 64M8 32M16 -5E -37E ARCHITECTURE 128 MEG X 4 64 MEG X 8 32 MEG X 16 Configuration 32 Meg x 4 x 4 16 Meg x 8 x 4 8 Meg x 16 x 4 banks banks banks Refresh Count Row Addressing 16K A0-A12 16K A0-A13 8K A0-A12 Bank Addressing 4 BA0 - BA1 4 BA0 - BA1 4 BA0 - BA1 Column Addressing 2K A0-A9, A11 1K A0-A9 1K A0-A9 Table 1 Key Timing Parameters DATA RATE SPEED tRCD tRP GRADE CL = 3 CL = 4 ns -37E 2003 Micron Technology, Inc. All rights reserved. AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS. 512Mb x4, x8, x16 DDR2 SDRAM Table of Contents Features Options Part Numbers FBGA Part Marking Decoder. General Description Functional Description Initialization Mode Register MR Burst Length Burst Type Operating Mode DLL Reset Write Recovery Power-Down Mode CAS Latency CL Extended Mode Register EMR DLL Enable/Disable Output Drive Strength DQS# Enable/Disable. RDQS Enable/Disable Output Enable/Disable On Die Termination ODT Off-Chip Driver OCD Impedance Calibration Posted CAS Additive Latency AL Extended Mode Register 2 EMR2 Extended Mode Register 3 EMR3 Command Truth Tables. DESELECT, NOP, and LOAD MODE Commands DESELECT NO OPERATION NOP . LOAD MODE LM Bank/Row Activation ACTIVE Command ACTIVE Operation READs READ Command READ Operation WRITEs WRITE Command WRITE Operation Precharge Command PRECHARGE Operation Self Refresh SELF REFRESH Command REFRESH. REFRESH Command Power-Down Mode. Precharge Power-Down Clock Frequency Change RESET Function CKE LOW Anytime ODT Timing Micron Technology, Inc., reserves the right to change products or specifications without notice. 2003 Micron Technology, Inc. All rights reserved. 512Mb x4, x8, x16 DDR2 SDRAM Absolute Maximum Ratings AC and DC Operating Conditions Input Electrical Characteristics and Operating Conditions. Input Slew Rate Derating. Data Slew Rating Power and Ground Clamp Characteristics AC Overshoot/Undershoot Specification Output Electrical Characteristics and Operating Conditions Full Strength Pull-Down Driver Characteristics Full Strength Pull-Up Driver Characteristics FBGA Package Capacitance IDD Specifications and Conditions IDD7 Conditions Notes 100 Data Sheet Designation 102 Micron Technology, Inc., reserves the right to change products or specifications without notice. 2003 Micron Technology, Inc. All rights reserved. Accesses within a given burst may be programmed to be either sequential or interleaved. The burst type is selected via bit M3 as shown in Figure The ordering of accesses within a burst is determined by the burst length, the burst type, and the starting column address as shown in Table DDR2 SDRAM supports 4-bit burst and 8-bit burst modes only. For 8-bit burst mode, full interleave address ordering is supported however, sequential address ordering is nibble-based. Micron Technology, Inc., reserves the right to change products or specifications without notice. 2003 Micron Technology, Inc. All rights reserved. Table 3 Burst Definition STARTING COLUMN ADDRESS BURST A2, A1, LENGTH A0 ORDER OF ACCESSES WITHIN A BURST BURST TYPE = SEQUENTIAL 0,1,2,3 1,2,3,0 2,3,0,1 3,0,1,2 0,1,2,3,4,5,6,7 1,2,3,0,5,6,7,4 2,3,0,1,6,7,4,5 3,0,1,2,7,4,5,6 4,5,6,7,0,1,2,3 5,6,7,4,1,2,3,0 6,7,4,5,2,3,0,1 7,4,5,6,3,0,1,2 BURST TYPE = INTERLEAVED 0,1,2,3 1,0,3,2,3,0,1 3,2,1,0,1,2,3,4,5,6,7 1,0,3,2,5,4,7,6 2,3,0,1,6,7,4,5 3,2,1,0,7,6,5,4,5,6,7,0,1,2,3 5,4,7,6,1,0,3,2 6,7,4,5,2,3,0,1 7,6,5,4,3,2,1,0 Operating Mode The normal operating mode is selected by issuing a LOAD MODE command with bit M7 set to zero, and all other bits set to the desired values as shown in Figure When bit M7 is ‘1,’ no other bits of the mode register are programmed. Programming bit M7 to ‘1’ places the DDR2 SDRAM into a test mode that is only used by the Manufacturer and should NOT be used. No operation or functionality is guaranteed if M7 bit is DLL Reset DLL reset is defined by bit M8 as shown in Figure Programming bit M8 to ‘1’ will activate the DLL RESET function. Bit M8 is self-clearing, meaning it returns back to a value of ‘0’ after the DLL RESET function has been issued. Anytime the DLL RESET function is used, 200 clock cycles must occur before a READ command can be issued to allow time for the internal clock to be synchronized with the external clock. Failing to wait for synchronization to occur may result in a violation of the tAC or tDQSCK parameters. Write Recovery Write recovery WR time is defined by bits as shown in Figure The WR Register is used by the DDR2 SDRAM during WRITE with AUTO PRECHARGE operation. During WRITE with AUTO PRECHARGE operation, the DDR2 SDRAM delays the internal AUTO PRECHARGE operation by WR clocks programmed in 512Mb x4, x8, x16 DDR2 SDRAM bits from the last data burst. An example of Write with AUTO PRECHARGE is shown in Figure 26 on page Write Recovery WR values of 2, 3, 4, 5, or 6 clocks may be used for programming bits The user is required to program the value of write recovery, which is calculated by dividing tWR in ns by tCK in ns and rounding up a noninteger value to the next integer WR [cycles] = tWR [ns] / tCK [ns]. Reserved states should not be used as unknown operation or incompatibility with future versions may result. Power-Down Mode Active power-down PD mode is defined by bit M12 as shown in Figure PD mode allows the user to determine the active power-down mode, which determines performance vs. power savings. PD mode bit M12 does not apply to precharge power-down mode. When bit M12 = 0, standard Active Power-down mode or ‘fast-exit’ active power-down mode is enabled. The tXARD parameter is used for ‘fast-exit’ active power-down exit timing. The DLL is expected to be enabled and running during this mode. When bit M12 = 1, a lower power active power-down mode or ‘slow-exit’ active power-down mode is enabled. The tXARDS parameter is used for ‘slow-exit’ active power-down exit timing. The DLL can be enabled, but ‘frozen’ during active power-down mode since the exit-to-READ command timing is relaxed. The power difference expected between PD ‘normal’ and PD ‘low-power’ mode is defined in the IDD table. CAS Latency CL The CAS Latency CL is defined by bits as shown in Figure CAS Latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The CAS Latency can be set to 3 or 4 clocks. CAS Latency of 2 or 5 clocks are JEDEC optional features and may be enabled in future speed grades. DDR2 SDRAM does not support any half clock latencies. Reserved states should not be used as unknown operation or incompatibility with future versions may result. DDR2 SDRAM also supports a feature called Posted CAS additive latency AL . This feature allows the READ command to be issued prior to tRCD MIN by delaying the internal command to the DDR2 SDRAM by AL clocks. The AL feature is described in more detail in the Extended Mode Register EMR and Operational sections. Micron Technology, Inc., reserves the right to change products or specifications without notice. 2003 Micron Technology, Inc. All rights reserved. 512Mb x4, x8, x16 DDR2 SDRAM Examples of CL = 3 and CL = 4 are shown in Figure 10 both assume AL = If a READ command is registered at clock edge n, and the CAS Latency is m clocks, the data will be available nominally coincident with clock edge n + m this assumes AL = Figure 10 CAS Latency CL COMMAND READ DQS, DQS# DOUT n DOUT n+1 DOUT n+2 DOUT n+3 CL = 3 AL = 0 CK# CK COMMAND DQS, DQS#

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DDR2 SDRAM
512Mb x4, x8, x16 DDR2 SDRAM

MEG X 4 X 4 BANKS MEG X 8 X 4 BANKS MEG X 16 X 4 BANKS

For the latest data sheet, please refer to the Micron Web site:
• VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V
• JEDEC standard 1.8V I/O SSTL_18-compatible
• Differential data strobe DQS, DQS# option
• Four-bit prefetch architecture
• Duplicate output strobe RDQS option for x8
configuration
• DLL to align DQ and DQS transitions with CK
• Four internal banks for concurrent operation
• Programmable CAS Latency CL 3 and 4
• Posted CAS additive latency AL 0, 1, 2, 3, and 4
• WRITE latency = READ latency - 1 tCK
• Programmable burst lengths 4 or 8
• Adjustable data-output drive strength
• 64ms, 8,192-cycle refresh
• On-die termination ODT

Options
• Configuration
128 Meg x 4 32 Meg x 4 x 4 banks 64 Meg x 8 16 Meg x 8 x 4 banks 32 Meg x 16 8 Meg x 16 x 4 banks
• FBGA Package Lead-Free 92-ball FBGA 11mm x 19mm
• Timing Cycle Time 5.0ns CL = 3 DDR2-400 3.75ns CL = 4 DDR2-533

Designation
128M4 64M8 32M16
-5E -37E

ARCHITECTURE 128 MEG X 4 64 MEG X 8 32 MEG X 16

Configuration
32 Meg x 4 x 4 16 Meg x 8 x 4 8 Meg x 16 x 4
banks
banks
banks

Refresh Count

Row Addressing 16K A0-A12 16K A0-A13 8K A0-A12

Bank Addressing 4 BA0 - BA1 4 BA0 - BA1 4 BA0 - BA1

Column Addressing
2K A0-A9, A11 1K A0-A9
1K A0-A9

Table 1 Key Timing Parameters

DATA RATE

SPEED
tRCD tRP

GRADE CL = 3 CL = 4 ns
-37E
2003 Micron Technology, Inc. All rights reserved.

AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS.
512Mb x4, x8, x16 DDR2 SDRAM

Table of Contents

Features Options

Part Numbers FBGA Part Marking Decoder. General Description Functional Description Initialization Mode Register MR

Burst Length Burst Type Operating Mode DLL Reset Write Recovery Power-Down Mode CAS Latency CL Extended Mode Register EMR DLL Enable/Disable Output Drive Strength DQS# Enable/Disable. RDQS Enable/Disable Output Enable/Disable On Die Termination ODT Off-Chip Driver OCD Impedance Calibration Posted CAS Additive Latency AL Extended Mode Register 2 EMR2 Extended Mode Register 3 EMR3 Command Truth Tables. DESELECT, NOP, and LOAD MODE Commands DESELECT NO OPERATION NOP . LOAD MODE LM Bank/Row Activation ACTIVE Command ACTIVE Operation READs READ Command READ Operation WRITEs WRITE Command WRITE Operation Precharge Command PRECHARGE Operation Self Refresh SELF REFRESH Command REFRESH. REFRESH Command Power-Down Mode. Precharge Power-Down Clock Frequency Change RESET Function CKE LOW Anytime ODT Timing

Micron Technology, Inc., reserves the right to change products or specifications without notice. 2003 Micron Technology, Inc. All rights reserved.
512Mb x4, x8, x16 DDR2 SDRAM

Absolute Maximum Ratings AC and DC Operating Conditions Input Electrical Characteristics and Operating Conditions. Input Slew Rate Derating. Data Slew Rating Power and Ground Clamp Characteristics AC Overshoot/Undershoot Specification Output Electrical Characteristics and Operating Conditions Full Strength Pull-Down Driver Characteristics Full Strength Pull-Up Driver Characteristics FBGA Package Capacitance IDD Specifications and Conditions

IDD7 Conditions Notes 100 Data Sheet Designation 102

Micron Technology, Inc., reserves the right to change products or specifications without notice. 2003 Micron Technology, Inc. All rights reserved.
Accesses within a given burst may be programmed to be either sequential or interleaved. The burst type is selected via bit M3 as shown in Figure The ordering of accesses within a burst is determined by the burst length, the burst type, and the starting column address as shown in Table DDR2 SDRAM supports 4-bit burst and 8-bit burst modes only. For 8-bit burst mode, full interleave address ordering is supported however, sequential address ordering is nibble-based.

Micron Technology, Inc., reserves the right to change products or specifications without notice. 2003 Micron Technology, Inc. All rights reserved.

Table 3 Burst Definition

STARTING COLUMN ADDRESS BURST A2, A1, LENGTH A0

ORDER OF ACCESSES WITHIN A BURST

BURST TYPE = SEQUENTIAL
0,1,2,3 1,2,3,0 2,3,0,1 3,0,1,2 0,1,2,3,4,5,6,7 1,2,3,0,5,6,7,4 2,3,0,1,6,7,4,5 3,0,1,2,7,4,5,6 4,5,6,7,0,1,2,3 5,6,7,4,1,2,3,0 6,7,4,5,2,3,0,1 7,4,5,6,3,0,1,2

BURST TYPE = INTERLEAVED
0,1,2,3 1,0,3,2,3,0,1 3,2,1,0,1,2,3,4,5,6,7 1,0,3,2,5,4,7,6 2,3,0,1,6,7,4,5 3,2,1,0,7,6,5,4,5,6,7,0,1,2,3 5,4,7,6,1,0,3,2 6,7,4,5,2,3,0,1 7,6,5,4,3,2,1,0

Operating Mode

The normal operating mode is selected by issuing a LOAD MODE command with bit M7 set to zero, and all other bits set to the desired values as shown in Figure When bit M7 is ‘1,’ no other bits of the mode register are programmed. Programming bit M7 to ‘1’ places the DDR2 SDRAM into a test mode that is only used by the Manufacturer and should NOT be used. No operation or functionality is guaranteed if M7 bit is

DLL Reset

DLL reset is defined by bit M8 as shown in Figure Programming bit M8 to ‘1’ will activate the DLL RESET function. Bit M8 is self-clearing, meaning it returns back to a value of ‘0’ after the DLL RESET function has been issued.

Anytime the DLL RESET function is used, 200 clock cycles must occur before a READ command can be issued to allow time for the internal clock to be synchronized with the external clock. Failing to wait for synchronization to occur may result in a violation of the tAC or tDQSCK parameters.

Write Recovery

Write recovery WR time is defined by bits as shown in Figure The WR Register is used by the DDR2 SDRAM during WRITE with AUTO PRECHARGE operation. During WRITE with AUTO PRECHARGE operation, the DDR2 SDRAM delays the internal AUTO PRECHARGE operation by WR clocks programmed in
512Mb x4, x8, x16 DDR2 SDRAM
bits from the last data burst. An example of Write with AUTO PRECHARGE is shown in Figure 26 on page

Write Recovery WR values of 2, 3, 4, 5, or 6 clocks may be used for programming bits The user is required to program the value of write recovery, which is calculated by dividing tWR in ns by tCK in ns and rounding up a noninteger value to the next integer WR [cycles] = tWR [ns] / tCK [ns]. Reserved states should not be used as unknown operation or incompatibility with future versions may result.

Power-Down Mode

Active power-down PD mode is defined by bit M12 as shown in Figure PD mode allows the user to determine the active power-down mode, which determines performance vs. power savings. PD mode bit M12 does not apply to precharge power-down mode.

When bit M12 = 0, standard Active Power-down mode or ‘fast-exit’ active power-down mode is enabled. The tXARD parameter is used for ‘fast-exit’ active power-down exit timing. The DLL is expected to be enabled and running during this mode.

When bit M12 = 1, a lower power active power-down mode or ‘slow-exit’ active power-down mode is enabled. The tXARDS parameter is used for ‘slow-exit’ active power-down exit timing. The DLL can be enabled, but ‘frozen’ during active power-down mode since the exit-to-READ command timing is relaxed. The power difference expected between PD ‘normal’ and PD ‘low-power’ mode is defined in the IDD table.

CAS Latency CL

The CAS Latency CL is defined by bits as shown in Figure CAS Latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The CAS Latency can be set to 3 or 4 clocks. CAS Latency of 2 or 5 clocks are JEDEC optional features and may be enabled in future speed grades. DDR2 SDRAM does not support any half clock latencies. Reserved states should not be used as unknown operation or incompatibility with future versions may result.

DDR2 SDRAM also supports a feature called Posted CAS additive latency AL . This feature allows the READ command to be issued prior to tRCD MIN by delaying the internal command to the DDR2 SDRAM by AL clocks. The AL feature is described in more detail in the Extended Mode Register EMR and Operational sections.

Micron Technology, Inc., reserves the right to change products or specifications without notice. 2003 Micron Technology, Inc. All rights reserved.
512Mb x4, x8, x16 DDR2 SDRAM

Examples of CL = 3 and CL = 4 are shown in Figure 10 both assume AL = If a READ command is registered at clock edge n, and the CAS Latency is m clocks, the data will be available nominally coincident with clock edge n + m this assumes AL =

Figure 10 CAS Latency CL

COMMAND

READ

DQS, DQS#

DOUT n

DOUT n+1

DOUT n+2

DOUT n+3

CL = 3 AL = 0

CK# CK

COMMAND

DQS, DQS#

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Datasheet ID: MT47H32M16BT-3:ATR 648449