MT46V8M16TG-75:D TR

MT46V8M16TG-75:D TR Datasheet

MT46V32M4 8 Meg x 4 x 4 Banks MT46V16M8 4 Meg x 8 x 4 Banks MT46V8M16 2 Meg x 16 x 4 Banks

Part	Datasheet
MT46V8M16TG-75:D TR	MT46V8M16TG-75:D TR (pdf)

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MT46V8M16TG-6T IT:D TR	MT46V8M16TG-6T IT:D TR
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MT46V8M16P-6T L:D TR	MT46V8M16P-6T L:D TR
MT46V32M4TG-5B:D TR	MT46V32M4TG-5B:D TR
MT46V16M8P-6T:DTR	MT46V16M8P-6T:DTR
MT46V16M8P-6TL:DTR	MT46V16M8P-6TL:DTR

PDF Datasheet Preview
128Mb x4, x8, x16 DDR SDRAM Features Double Data Rate DDR SDRAM MT46V32M4 8 Meg x 4 x 4 Banks MT46V16M8 4 Meg x 8 x 4 Banks MT46V8M16 2 Meg x 16 x 4 Banks • VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V • VDD = +2.6V ±0.1V, VDDQ = +2.6V ±0.1V DDR400 • Bidirectional data strobe DQS transmitted/ received with data, i.e., source-synchronous data capture x16 has two one per byte • Internal, pipelined double-data-rate DDR architecture two data accesses per clock cycle • Differential clock inputs CK and CK# • Commands entered on each positive CK edge • DQS edge-aligned with data for READs centeraligned with data for WRITEs • DLL to align DQ and DQS transitions with CK • Four internal banks for concurrent operation • Data mask DM for masking write data x16 has two one per byte • Programmable burst lengths 2, 4, or 8 • Auto refresh and self refresh modes • Longer lead TSOP for improved reliability OCPL • 2.5V I/O SSTL_2 compatible • Concurrent auto precharge option is supported • tRAS lockout supported tRAP = tRCD Options • Configuration 32 Meg x 4 8 Meg x 4 x 4 banks 16 Meg x 8 4 Meg x 8 x 4 banks 8 Meg x 16 2 Meg x 16 x 4 banks • Plastic package OCPL 66-pin TSOP 66-pin TSOP Pb-free • Timing cycle time 5ns CL = 3 DDR400 6ns CL = DDR333 TSOP only 7.5ns CL = 2 DDR266 1 7.5ns CL = 2 DDR266A 7.5ns CL = DDR266B • Self refresh Standard Low-power self refresh • Temperature rating Commercial 0°C to 70°C Industrial to +85°C Marking 32M4 16M8 8M16 -5B -6T -75E -75Z -75 None L None IT :D Notes Not recommended for new designs Table 1: Key Timing Parameters CL = CAS READ latency MIN clock rate with 50% duty cycle at CL = 2 -75E, -75Z , CL = -6, -6T, -75 , and CL = 3 -5B Speed Grade -5B -6T -75E/-75Z -75 CL = 2 133 100 Clock Rate MHz CL = 167 133 CL = 3 200 n/a n/a n/a Data Out Window 1.6ns 2.0ns 2.5ns 2.5ns Access Window ±0.70ns ±0.70ns ±0.75ns ±0.75ns Skew +0.40ns +0.45ns +0.50ns +0.50ns Micron Technology, Inc., reserves the right to change products or specifications without notice. 2004 Micron Technology, Inc. All rights reserved. 128Mb x4, x8, x16 DDR SDRAM Features Table 2 Addressing Parameter Configuration Refresh count Row address Bank address Column address 32 Meg x 4 8 Meg x 4 x 4 banks 4K 4K 4 BA0, BA1 2K A11 The ordering of accesses within a burst is determined by the burst length, the burst type, and the starting column address, as shown in Table Table 31 Burst Definition Burst Length 2 4 Starting Column Address Order of Accesses Within a Burst Type = Sequential Type = Interleaved 0-1-0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 0-1-0-1-2-3 1-0-3-2-3-0-1 3-2-1-0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 Micron Technology, Inc., reserves the right to change products or specifications without notice. 2004 Micron Technology, Inc. All rights reserved. 128Mb x4, x8, x16 DDR SDRAM Operations CAS Latency CL The CL is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The latency can be set to 2, or 3 -5B only clocks, as shown in Figure Reserved states should not be used, as unknown operation or incompatibility with future versions may result. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available nominally coincident with clock edge n + m. Table 32 on page 48 indicates the operating frequencies at which each CL setting can be used. Figure 22 CAS Latency CK# CK COMMAND T0 READ NOP CL = 2 T2 T2n T3 T3n CK# CK COMMAND T0 READ DQS DQ T2 T2n T3 T3n T0 CK# T3 T3n COMMAND READ CL = 3 DQS Note: TRANSITIONING DATA DON’T CARE BL = 4 in the cases shown with nominal tAC, tDQSCK, and tDQSQ. Micron Technology, Inc., reserves the right to change products or specifications without notice. 2004 Micron Technology, Inc. All rights reserved. 128Mb x4, x8, x16 DDR SDRAM Operations Table 32 CAS Latency Speed -5B -6/-6T -75E -75Z -75 CL = 2 75 f 133 75 f 133 75 f 133 75 f 133 75 f 100 Allowable Operating Clock Frequency MHz

PDF Datasheet Preview

128Mb x4, x8, x16 DDR SDRAM Features

Double Data Rate DDR SDRAM

MT46V32M4 8 Meg x 4 x 4 Banks MT46V16M8 4 Meg x 8 x 4 Banks MT46V8M16 2 Meg x 16 x 4 Banks
• VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V
• VDD = +2.6V ±0.1V, VDDQ = +2.6V ±0.1V DDR400
• Bidirectional data strobe DQS transmitted/
received with data, i.e., source-synchronous data capture x16 has two one per byte
• Internal, pipelined double-data-rate DDR architecture two data accesses per clock cycle
• Differential clock inputs CK and CK#
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs centeraligned with data for WRITEs
• DLL to align DQ and DQS transitions with CK
• Four internal banks for concurrent operation
• Data mask DM for masking write data x16 has two one per byte
• Programmable burst lengths 2, 4, or 8
• Auto refresh and self refresh modes
• Longer lead TSOP for improved reliability OCPL
• 2.5V I/O SSTL_2 compatible
• Concurrent auto precharge option is supported
• tRAS lockout supported tRAP = tRCD

Options
• Configuration 32 Meg x 4 8 Meg x 4 x 4 banks 16 Meg x 8 4 Meg x 8 x 4 banks 8 Meg x 16 2 Meg x 16 x 4 banks
• Plastic package OCPL 66-pin TSOP 66-pin TSOP Pb-free
• Timing cycle time 5ns CL = 3 DDR400 6ns CL = DDR333 TSOP only 7.5ns CL = 2 DDR266 1 7.5ns CL = 2 DDR266A 7.5ns CL = DDR266B
• Self refresh Standard Low-power self refresh
• Temperature rating Commercial 0°C to 70°C Industrial to +85°C

Marking
32M4 16M8 8M16
-5B -6T
-75E -75Z -75

None L

None IT :D

Notes Not recommended for new designs

Table 1:

Key Timing Parameters CL = CAS READ latency MIN clock rate with 50% duty cycle at CL = 2 -75E, -75Z , CL = -6, -6T, -75 , and CL = 3 -5B

Speed Grade
-5B -6T -75E/-75Z -75

CL = 2
133 100

Clock Rate MHz

CL = 167 133

CL = 3
200 n/a n/a n/a

Data Out Window
1.6ns 2.0ns 2.5ns 2.5ns

Access Window
±0.70ns ±0.70ns ±0.75ns ±0.75ns

Skew
+0.40ns +0.45ns +0.50ns +0.50ns

Micron Technology, Inc., reserves the right to change products or specifications without notice. 2004 Micron Technology, Inc. All rights reserved.
128Mb x4, x8, x16 DDR SDRAM Features

Table 2 Addressing

Parameter Configuration Refresh count Row address Bank address Column address
32 Meg x 4
8 Meg x 4 x 4 banks 4K
4K 4 BA0, BA1 2K A11
The ordering of accesses within a burst is determined by the burst length, the burst type, and the starting column address, as shown in Table

Table 31 Burst Definition

Burst Length 2 4

Starting Column Address

Order of Accesses Within a Burst

Type = Sequential

Type = Interleaved
0-1-0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6
0-1-0-1-2-3 1-0-3-2-3-0-1 3-2-1-0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0

Micron Technology, Inc., reserves the right to change products or specifications without notice. 2004 Micron Technology, Inc. All rights reserved.
128Mb x4, x8, x16 DDR SDRAM Operations

CAS Latency CL

The CL is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The latency can be set to 2, or 3 -5B only clocks, as shown in Figure Reserved states should not be used, as unknown operation or incompatibility with future versions may result.

If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available nominally coincident with clock edge n + m. Table 32 on page 48 indicates the operating frequencies at which each CL setting can be used.

Figure 22 CAS Latency

CK# CK

COMMAND

T0 READ

NOP CL = 2

T2 T2n T3 T3n

CK# CK

COMMAND

T0 READ

DQS DQ

T2 T2n T3 T3n

T0 CK#

T3 T3n

COMMAND

READ

CL = 3 DQS

Note:

TRANSITIONING DATA

DON’T CARE

BL = 4 in the cases shown with nominal tAC, tDQSCK, and tDQSQ.

Micron Technology, Inc., reserves the right to change products or specifications without notice. 2004 Micron Technology, Inc. All rights reserved.
128Mb x4, x8, x16 DDR SDRAM Operations

Table 32 CAS Latency

Speed -5B
-6/-6T -75E -75Z -75

CL = 2 75 f 133 75 f 133 75 f 133 75 f 133 75 f 100

Allowable Operating Clock Frequency MHz

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Datasheet ID: MT46V8M16TG-75:DTR 648447