MT46V16M16TG-75 IT:F

MT46V16M16TG-75 IT:F Datasheet

MT46V64M4 16 Meg x 4 x 4 banks MT46V32M8 8 Meg x 8 x 4 banks MT46V16M16 4 Meg x 16 x 4 banks

Part	Datasheet
MT46V16M16TG-75 IT:F	MT46V16M16TG-75 IT:F (pdf)

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MT46V32M8FG-6 IT:G TR	MT46V32M8FG-6 IT:G TR
MT46V16M16TG-75:F	MT46V16M16TG-75:F
MT46V16M16TG-75:F TR	MT46V16M16TG-75:F TR
MT46V32M8FG-75 L:G	MT46V32M8FG-75 L:G
MT46V32M8FG-75 L:G TR	MT46V32M8FG-75 L:G TR
MT46V32M8FG-75E:G TR	MT46V32M8FG-75E:G TR
MT46V32M8FG-75E:G	MT46V32M8FG-75E:G
MT46V16M16BG-6:F	MT46V16M16BG-6:F
MT46V16M16TG-75 L:F	MT46V16M16TG-75 L:F
MT46V16M16FG-75:F	MT46V16M16FG-75:F
MT46V32M8FG-75:G TR	MT46V32M8FG-75:G TR
MT46V32M8FG-6 L:G	MT46V32M8FG-6 L:G
MT46V16M16TG-75 IT:F TR	MT46V16M16TG-75 IT:F TR
MT46V16M16P-6T:F	MT46V16M16P-6T:F
MT46V16M16TG-5G:F TR	MT46V16M16TG-5G:F TR
MT46V16M16FG-75:F TR	MT46V16M16FG-75:F TR
MT46V32M8TG-75 IT:G	MT46V32M8TG-75 IT:G
MT46V32M8FG-75:G	MT46V32M8FG-75:G
MT46V16M16TG-5G:F	MT46V16M16TG-5G:F
MT46V16M16P-75:F	MT46V16M16P-75:F
MT46V16M16TG-75 L:F TR	MT46V16M16TG-75 L:F TR
MT46V32M8BG-75:G	MT46V32M8BG-75:G
MT46V64M4TG-75:G	MT46V64M4TG-75:G
MT46V32M8BG-75:G TR	MT46V32M8BG-75:G TR
MT46V32M8BG-6:G TR	MT46V32M8BG-6:G TR
MT46V32M8TG-6T:G TR	MT46V32M8TG-6T:G TR
MT46V64M4TG-5B:G TR	MT46V64M4TG-5B:G TR
MT46V64M4FG-6:G TR	MT46V64M4FG-6:G TR
MT46V64M4FG-5B:G TR	MT46V64M4FG-5B:G TR
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MT46V16M16TG-6T IT:F TR	MT46V16M16TG-6T IT:F TR
MT46V16M16P-75:F TR	MT46V16M16P-75:F TR
MT46V16M16P-5B:K TR	MT46V16M16P-5B:K TR
MT46V16M16FG-6 L:F	MT46V16M16FG-6 L:F
MT46V16M16P-6T:F TR	MT46V16M16P-6T:F TR
MT46V32M8BG-5B:GTR	MT46V32M8BG-5B:GTR
MT46V16M16P-6T IT:F TR	MT46V16M16P-6T IT:F TR
MT46V32M8BG-6:GTR	MT46V32M8BG-6:GTR
MT46V16M16P-5B:F TR	MT46V16M16P-5B:F TR
MT46V32M8P-5B:GTR	MT46V32M8P-5B:GTR
MT46V16M16BG-6:F TR	MT46V16M16BG-6:F TR
MT46V64M4BG-5B:GTR	MT46V64M4BG-5B:GTR
MT46V32M8P-6TL:GTR	MT46V32M8P-6TL:GTR
MT46V32M8P-6T:GTR	MT46V32M8P-6T:GTR
MT46V16M16P-6T L:F TR	MT46V16M16P-6T L:F TR
MT46V16M16FG-6 L:F TR	MT46V16M16FG-6 L:F TR
MT46V64M4P-6T:GTR	MT46V64M4P-6T:GTR
MT46V32M8BG-6 IT:G TR	MT46V32M8BG-6 IT:G TR
MT46V32M8P-6T IT:G	MT46V32M8P-6T IT:G
MT46V64M4P-5B:G	MT46V64M4P-5B:G
MT46V16M16P-6T L:F	MT46V16M16P-6T L:F
MT46V64M4BG-6:GTR	MT46V64M4BG-6:GTR
MT46V32M8P-6T IT:G TR	MT46V32M8P-6T IT:G TR
MT46V16M16BG-5B:F TR	MT46V16M16BG-5B:F TR
MT46V64M4P-5B:G TR	MT46V64M4P-5B:G TR
MT46V64M4P-5B:K	MT46V64M4P-5B:K
MT46V64M4P-6T:K	MT46V64M4P-6T:K

PDF Datasheet Preview
256Mb x4, x8, x16 DDR SDRAM Features Double Data Rate DDR SDRAM MT46V64M4 16 Meg x 4 x 4 banks MT46V32M8 8 Meg x 8 x 4 banks MT46V16M16 4 Meg x 16 x 4 banks • VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V • VDD = +2.6V ±0.1V, VDDQ = +2.6V ±0.1V DDR400 • Bidirectional data strobe DQS transmitted/ received with data, that is, source-synchronous data capture x16 has two one per byte • Internal, pipelined double-data-rate DDR architecture two data accesses per clock cycle • Differential clock inputs CK and CK# • Commands entered on each positive CK edge • DQS edge-aligned with data for READs centeraligned with data for WRITEs • DLL to align DQ and DQS transitions with CK • Four internal banks for concurrent operation • Data mask DM for masking write data x16 has two one per byte • Programmable burst lengths BL 2, 4, or 8 • Auto refresh 64ms, 8192-cycle Commercial & Industrial 16ms, 8192-cycle Automotive • Self refresh not available on AT devices • Longer-lead TSOP for improved reliability OCPL • 2.5V I/O SSTL_2-compatible • Concurrent auto precharge option supported • tRAS lockout supported tRAP = tRCD Options Marking • Configuration 64 Meg x 4 16 Meg x 4 x 4 banks 32 Meg x 8 Meg x 8 x 4 banks 16 Meg x 16 4 Meg x 16 x 4 banks • Plastic package OCPL 66-pin TSOP 66-pin TSOP Pb-free • Plastic package 60-ball FBGA 8mm x 14mm 60-ball FBGA 8mm x 14mm Pb-free 60-ball FBGA 8mm x 12.5mm 60-ball FBGA 8mm x 12.5mm Pb-free • Timing cycle time 64M4 32M8 16M16 FG1 BG1 CV2 CY2 -5B -6 -6T -75E1 -75Z1 -751 None L None IT AT4 :G3 :F3 :K Not recommended for new designs. Contact Micron for availability. Micron Technology, Inc., reserves the right to change products or specifications without notice. 2003 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 256Mb x4, x8, x16 DDR SDRAM Features Table 1: Key Timing Parameters CL = CAS READ latency MIN clock rate with 50% duty cycle at CL = 2 -75E, -75Z , CL = -6, -6T, -75 , and CL = 3 -5B Clock Rate MHz Speed Grade -5B -6 6T -75E/-75Z -75 CL = 2 133 100 167 133 CL = 3 200 n/a n/a n/a n/a Data-Out Window Access Window Skew 1.6ns 2.1ns 2.0ns 2.5ns 2.5ns ±0.70ns ±0.70ns ±0.70ns ±0.75ns ±0.75ns +0.40ns +0.40ns +0.45ns +0.50ns +0.50ns Table 2 Addressing Parameter Configuration Refresh count Row address Bank address Column address 64 Meg x 4 16 Meg x 4 x 4 banks 8K 8K 4 BA0, BA1 2K A11 The ordering of accesses within a burst is determined by the burst length, the burst type, and the starting column address, as shown in Table Table 34 Burst Definition Burst Length 2 4 Starting Column Address Order of Accesses Within a Burst Type = Sequential Type = Interleaved 0-1-0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 0-1-0-1-2-3 1-0-3-2-3-0-1 3-2-1-0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 Micron Technology, Inc., reserves the right to change products or specifications without notice. 2003 Micron Technology, Inc. All rights reserved. 256Mb x4, x8, x16 DDR SDRAM Operations CAS Latency CL The CL is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The latency can be set to 2, or 3 -5B only clocks, as shown in Figure Reserved states should not be used, as unknown operation or incompatibility with future versions may result. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available nominally coincident with clock edge n + m. Table 35 on page 58 indicates the operating frequencies at which each CL setting can be used. Figure 24 CAS Latency CK# CK Command T0 READ T1 NOP CL = 2 CK# CK Command T0 READ DQS DQ NOP CL = CK# CK Command T0 READ T1 NOP T2 NOP CL = 3 Note: Transitioning Data Don’t Care BL = 4 in the cases shown with nominal tAC, tDQSCK, and tDQSQ. Micron Technology, Inc., reserves the right to change products or specifications without notice. 2003 Micron Technology, Inc. All rights reserved. 256Mb x4, x8, x16 DDR SDRAM Operations Table 35 CAS Latency Speed -5B -6/-6T -75E -75Z -75 CL = 2 75 f 133 75 f 133 75 f 133 75 f 133 75 f 100

PDF Datasheet Preview

256Mb x4, x8, x16 DDR SDRAM Features

Double Data Rate DDR SDRAM

MT46V64M4 16 Meg x 4 x 4 banks MT46V32M8 8 Meg x 8 x 4 banks MT46V16M16 4 Meg x 16 x 4 banks
• VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V
• VDD = +2.6V ±0.1V, VDDQ = +2.6V ±0.1V DDR400
• Bidirectional data strobe DQS transmitted/
received with data, that is, source-synchronous data capture x16 has two one per byte
• Internal, pipelined double-data-rate DDR architecture two data accesses per clock cycle
• Differential clock inputs CK and CK#
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs centeraligned with data for WRITEs
• DLL to align DQ and DQS transitions with CK
• Four internal banks for concurrent operation
• Data mask DM for masking write data x16 has two one per byte
• Programmable burst lengths BL 2, 4, or 8
• Auto refresh 64ms, 8192-cycle Commercial & Industrial 16ms, 8192-cycle Automotive
• Self refresh not available on AT devices
• Longer-lead TSOP for improved reliability OCPL
• 2.5V I/O SSTL_2-compatible
• Concurrent auto precharge option supported
• tRAS lockout supported tRAP = tRCD

Options

Marking
• Configuration 64 Meg x 4 16 Meg x 4 x 4 banks 32 Meg x 8 Meg x 8 x 4 banks 16 Meg x 16 4 Meg x 16 x 4 banks
• Plastic package OCPL 66-pin TSOP 66-pin TSOP Pb-free
• Plastic package 60-ball FBGA 8mm x 14mm 60-ball FBGA 8mm x 14mm Pb-free 60-ball FBGA 8mm x 12.5mm 60-ball FBGA 8mm x 12.5mm

Pb-free
• Timing cycle time
64M4 32M8 16M16

FG1 BG1 CV2 CY2
-5B -6 -6T -75E1 -75Z1 -751

None L

None IT AT4
:G3 :F3 :K

Not recommended for new designs.

Contact Micron for availability.

Micron Technology, Inc., reserves the right to change products or specifications without notice. 2003 Micron Technology, Inc. All rights reserved.

Products and specifications discussed herein are subject to change by Micron without notice.
256Mb x4, x8, x16 DDR SDRAM Features

Table 1:

Key Timing Parameters CL = CAS READ latency MIN clock rate with 50% duty cycle at CL = 2 -75E, -75Z , CL = -6, -6T, -75 , and CL = 3 -5B

Clock Rate MHz

Speed Grade
-5B -6 6T -75E/-75Z -75

CL = 2
133 100
167 133

CL = 3
200 n/a n/a n/a n/a

Data-Out Window Access Window Skew
1.6ns 2.1ns 2.0ns 2.5ns 2.5ns
±0.70ns ±0.70ns ±0.70ns ±0.75ns ±0.75ns
+0.40ns +0.40ns +0.45ns +0.50ns +0.50ns

Table 2 Addressing

Parameter Configuration Refresh count Row address Bank address Column address
64 Meg x 4
16 Meg x 4 x 4 banks 8K
8K 4 BA0, BA1 2K A11
The ordering of accesses within a burst is determined by the burst length, the burst type, and the starting column address, as shown in Table

Table 34 Burst Definition

Burst Length 2 4

Starting Column Address

Order of Accesses Within a Burst

Type = Sequential

Type = Interleaved
0-1-0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6
0-1-0-1-2-3 1-0-3-2-3-0-1 3-2-1-0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0

Micron Technology, Inc., reserves the right to change products or specifications without notice. 2003 Micron Technology, Inc. All rights reserved.
256Mb x4, x8, x16 DDR SDRAM Operations

CAS Latency CL

The CL is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The latency can be set to 2, or 3 -5B only clocks, as shown in Figure Reserved states should not be used, as unknown operation or incompatibility with future versions may result.

If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available nominally coincident with clock edge n + m. Table 35 on page 58 indicates the operating frequencies at which each CL setting can be used.

Figure 24 CAS Latency

CK# CK

Command

T0 READ

T1 NOP

CL = 2

CK# CK

Command

T0 READ

DQS DQ

NOP CL =

CK# CK

Command

T0 READ

T1 NOP

T2 NOP

CL = 3

Note:

Transitioning Data

Don’t Care

BL = 4 in the cases shown with nominal tAC, tDQSCK, and tDQSQ.

Micron Technology, Inc., reserves the right to change products or specifications without notice. 2003 Micron Technology, Inc. All rights reserved.
256Mb x4, x8, x16 DDR SDRAM Operations

Table 35 CAS Latency

Speed -5B
-6/-6T -75E -75Z -75

CL = 2 75 f 133 75 f 133 75 f 133 75 f 133 75 f 100

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived MT46V16M16TG-75IT:F Datasheet file may be downloaded here without warranties.

Datasheet ID: MT46V16M16TG-75IT:F 648445