MT46H8M16LF 2 Meg x 16 x 4 Banks MT46H4M32LF 1 Meg x 32 x 4 Banks
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MT46H8M16LFBF-6 AT:K (pdf) |
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MT46H4M32LFB5-6 AT:K TR |
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MT46H8M16LFBF-6 AT:K TR |
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MT46H4M32LFB5-6 AT:K |
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128Mb x16, x32 Mobile LPDDR SDRAM Features Mobile Low-Power DDR SDRAM MT46H8M16LF 2 Meg x 16 x 4 Banks MT46H4M32LF 1 Meg x 32 x 4 Banks • VDD/VDDQ = • Bidirectional data strobe per byte of data DQS • Internal, pipelined double data rate DDR architec- ture two data accesses per clock cycle • Differential clock inputs CK and CK# • Commands entered on each positive CK edge • DQS edge-aligned with data for READs center- aligned with data for WRITEs • 4 internal banks for concurrent operation • Data masks DM for masking write data one mask per byte • Programmable burst lengths BL 2, 4, 8, or 16 • Concurrent auto precharge option is supported • Auto refresh and self refresh modes • 1.8V LVCMOS-compatible inputs • Temperature-compensated self refresh TCSR • Partial-array self refresh PASR • Deep power-down DPD • Status read register SRR • Selectable output drive strength DS • Clock stop capability • 64ms refresh Options • VDD/VDDQ 1.8V/1.8V • Configuration 8 Meg x 16 2 Meg x 16 x 4 banks 4 Meg x 32 1 Meg x 32 x 4 banks • Row size option JEDEC-standard option • Plastic "green" package 60-ball VFBGA 8mm x 9mm 1 90-ball VFBGA 8mm x 13mm 2 • Timing cycle time 5ns CL = 3 200 MHz 5.4ns CL = 3 185 MHz 6ns CL = 3 166 MHz 7.5ns CL = 3 133 MHz • Operating temperature range Commercial to Industrial to Marking 8M16 4M32 BF B5 -5 -54 -6 -75 None IT :K Notes Only available for x16 configuration. Only available for x32 configuration. Table 1 Key Timing Parameters CL = 3 Speed Grade -5 -54 -6 -75 Clock Rate 200 MHz 185 MHz 166 MHz 133 MHz Access Time 5.0ns 5.0ns 5.0ns 6.0ns Micron Technology, Inc. reserves the right to change products or specifications without notice. 2007 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 128Mb x16, x32 Mobile LPDDR SDRAM Features Table 2 Configuration Addressing Architecture Configuration Refresh count Row addressing Column addressing 8 Meg x 16 2 Meg x 16 x 4 banks 4K A[11:0] 512 A[8:0] Figure 1 128Mb Mobile LPDDR Part Numbering Micron Technology Product Family 46 = Mobile LPDDR Operating Voltage H = 1.8/1.8V MT 46 H 8M16 LF BF -6 IT :K The ordering of accesses within a burst is determined by the burst length, the burst type, and the starting column address. Table 19 Burst Definition Table Burst Length Starting Column Address Order of Accesses Within a Burst Type = Sequential Type = Interleaved 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3 1-0-3-2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2007 Micron Technology, Inc. All rights reserved. 128Mb x16, x32 Mobile LPDDR SDRAM Standard Mode Register Table 19 Burst Definition Table Continued Burst Length Starting Column Address Order of Accesses Within a Burst Type = Sequential Type = Interleaved 0-1-2-3-4-5-6-7-8-9-A-B-C-D-E-F 0-1-2-3-4-5-6-7-8-9-A-B-C-D-E-F 1-2-3-4-5-6-7-8-9-A-B-C-D-E-F-0 1-0-3-2-5-4-7-6-9-8-B-A-D-C-F-E 2-3-4-5-6-7-8-9-A-B-C-D-E-F-0-1 2-3-0-1-6-7-4-5-A-B-8-9-E-F-C-D 3-4-5-6-7-8-9-A-B-C-D-E-F-0-1-2 3-2-1-0-7-6-5-4-B-A-9-8-F-E-D-C 4-5-6-7-8-9-A-B-C-D-E-F-0-1-2-3 4-5-6-7-0-1-2-3-C-D-E-F-8-9-A-B 5-6-7-8-9-A-B-C-D-E-F-0-1-2-3-4 5-4-7-6-1-0-3-2-D-C-F-E-9-8-B-A 6-7-8-9-A-B-C-D-E-F-0-1-2-3-4-5 6-7-4-5-2-3-0-1-E-F-C-D-A-B-8-9 7-8-9-A-B-C-D-E-F-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0-F-E-D-C-B-A-9-8 8-9-A-B-C-D-E-F-0-1-2-3-4-5-6-7 8-9-A-B-C-D-E-F-0-1-2-3-4-5-6-7 9-A-B-C-D-E-F-0-1-2-3-4-5-6-7-8 9-8-B-A-D-C-F-E-1-0-3-2-5-4-7-6 A-B-C-D-E-F-0-1-2-3-4-5-6-7-8-9 A-B-8-9-E-F-C-D-2-3-0-1-6-7-4-5 |
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