MT46H256M32L4JV-5 IT:A
MT46H256M32L4JV-5 IT:A Datasheet
MT46H128M16LF 32 Meg x 16 x 4 Banks MT46H64M32LF 16 Meg x 32 x 4 Banks MT46H128M32L2 16 Meg x 32 x 4 Banks x 2 MT46H256M32L4 32 Meg x 16 x 4 Banks x 4 MT46H256M32R4 32 Meg x 16 x 4 Banks x 4
| Part | Datasheet |
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MT46H256M32L4JV-5 IT:A |
MT46H256M32L4JV-5 IT:A (pdf) |
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MT46H128M32L2MC-6 IT:A |
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MT46H64M32LFMA-5 IT:A TR |
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MT46H64M32LFMA-5 IT:A |
MT46H64M32LFMA-5 IT:A |
| PDF Datasheet Preview |
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| 2Gb x16, x32 Mobile LPDDR SDRAM Features Mobile Low-Power DDR SDRAM MT46H128M16LF 32 Meg x 16 x 4 Banks MT46H64M32LF 16 Meg x 32 x 4 Banks MT46H128M32L2 16 Meg x 32 x 4 Banks x 2 MT46H256M32L4 32 Meg x 16 x 4 Banks x 4 MT46H256M32R4 32 Meg x 16 x 4 Banks x 4 • VDD/VDDQ = • Bidirectional data strobe per byte of data DQS • Internal, pipelined double data rate DDR architecture two data accesses per clock cycle • Differential clock inputs CK and CK# • Commands entered on each positive CK edge • DQS edge-aligned with data for READs center- aligned with data for WRITEs • 4 internal banks for concurrent operation • Data masks DM for masking write data one mask per byte • Programmable burst lengths BL 2, 4, 8, or 16 • Concurrent auto precharge option is supported • Auto refresh and self refresh modes • 1.8V LVCMOS-compatible inputs • Temperature-compensated self refresh TCSR • Partial-array self refresh PASR • Deep power-down DPD • Status read register SRR • Selectable output drive strength DS • Clock stop capability • 64ms refresh 32ms for the automotive temperature range Table 1 Key Timing Parameters CL = 3 Speed Grade -5 -54 -6 -75 Clock Rate 200 MHz 185 MHz 166 MHz 133 MHz Access Time 5.0ns 5.0ns 5.0ns 6.0ns Options Marking • VDD/VDDQ 1.8V/1.8V • Configuration 128 Meg x 16 32 Meg x 16 x 4 banks 64 Meg x 32 16 Meg x 32 x 4 banks • Addressing JEDEC-standard Reduced page-size1 4-die stack reduced page-size2 2-die stack standard 4-die stack standard • Plastic "green" package 60-ball VFBGA 10mm x 11.5mm 3 90-ball VFBGA 10mm x 13mm 4 • PoP plastic "green" package 168-ball VFBGA 12mm x 12mm 4 168-ball WFBGA 12mm x 12mm 4 168-ball WFBGA 12mm x 12mm 4 240-ball WFBGA 14mm x 14mm 4 • Timing cycle time 5ns CL = 3 200 MHz 5.4ns CL = 3 185 MHz 6ns CL = 3 166 MHz 7.5ns CL = 3 133 MHz • Power Standard IDD2/IDD6 • Operating temperature range Commercial to Industrial to Automotive to 128M16 64M32 LF LG R4 L2 L4 CK CM JV KQ MA MC -5 -54 -6 -75 None None IT AT :A Contact factory for availability. Available in the 168-ball JV package only. Available only for x16 configuration. Available only for x32 configuration. Micron Technology, Inc. reserves the right to change products or specifications without notice. 2009 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 2Gb x16, x32 Mobile LPDDR SDRAM Features Table 2 Configuration Addressing 2Gb Architecture Configuration Refresh count Row addressing Column addressing 128 Meg x 16 64 Meg x 32 32 Meg x 16 x 4 banks 16 Meg x 32 x 4 banks The ordering of accesses within a burst is determined by the burst length, the burst type, and the starting column address. Table 21 Burst Definition Table Burst Length Starting Column Address Order of Accesses Within a Burst Type = Sequential Type = Interleaved 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3 1-0-3-2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2009 Micron Technology, Inc. All rights reserved. 2Gb x16, x32 Mobile LPDDR SDRAM Standard Mode Register Table 21 Burst Definition Table Continued Burst Length Starting Column Address Order of Accesses Within a Burst Type = Sequential Type = Interleaved 0-1-2-3-4-5-6-7-8-9-A-B-C-D-E-F 0-1-2-3-4-5-6-7-8-9-A-B-C-D-E-F 1-2-3-4-5-6-7-8-9-A-B-C-D-E-F-0 1-0-3-2-5-4-7-6-9-8-B-A-D-C-F-E 2-3-4-5-6-7-8-9-A-B-C-D-E-F-0-1 2-3-0-1-6-7-4-5-A-B-8-9-E-F-C-D 3-4-5-6-7-8-9-A-B-C-D-E-F-0-1-2 3-2-1-0-7-6-5-4-B-A-9-8-F-E-D-C 4-5-6-7-8-9-A-B-C-D-E-F-0-1-2-3 4-5-6-7-0-1-2-3-C-D-E-F-8-9-A-B 5-6-7-8-9-A-B-C-D-E-F-0-1-2-3-4 5-4-7-6-1-0-3-2-D-C-F-E-9-8-B-A 6-7-8-9-A-B-C-D-E-F-0-1-2-3-4-5 6-7-4-5-2-3-0-1-E-F-C-D-A-B-8-9 7-8-9-A-B-C-D-E-F-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0-F-E-D-C-B-A-9-8 8-9-A-B-C-D-E-F-0-1-2-3-4-5-6-7 8-9-A-B-C-D-E-F-0-1-2-3-4-5-6-7 9-A-B-C-D-E-F-0-1-2-3-4-5-6-7-8 9-8-B-A-D-C-F-E-1-0-3-2-5-4-7-6 A-B-C-D-E-F-0-1-2-3-4-5-6-7-8-9 A-B-8-9-E-F-C-D-2-3-0-1-6-7-4-5 |
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