MT41K512M8RH-125 M AIT:E

MT41K512M8RH-125 M AIT:E Datasheet

MT41K512M8 64 Meg x 8 x 8 banks MT41K256M16 32 Meg x 16 x 8 banks

Part	Datasheet
MT41K512M8RH-125 M AIT:E	MT41K512M8RH-125 M AIT:E (pdf)

Related Parts	Information
MT41K512M8RH-125 M AIT:E TR	MT41K512M8RH-125 M AIT:E TR

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4Gb x8, x16 Automotive DDR3L-RS SDRAM Description Automotive DDR3L-RS SDRAM MT41K512M8 64 Meg x 8 x 8 banks MT41K256M16 32 Meg x 16 x 8 banks The 1.35V DDR3L-RS SDRAM device is a low-current self refresh version of the 1.35V DDR3L SDRAM device via the TCSR feature. Unless stated otherwise, the DDR3L-RS SDRAM device meets the functional and timing specifications listed in the equivalent density standard or automotive DDR3L SDRAM data sheet located on • VDD = VDDQ = 1.35V • Backward-compatible to VDD = VDDQ = 1.5V ±0.075V • Differential bidirectional data strobe • 8n-bit prefetch architecture • Differential clock inputs CK, CK# • 8 internal banks • Nominal and dynamic on-die termination ODT for data, strobe, and mask signals • Programmable CAS READ latency CL • Programmable posted CAS additive latency AL • Programmable CAS WRITE latency CWL • Fixed burst length BL of 8 and burst chop BC of 4 via the mode register set [MRS] • Selectable BC4 or BL8 on-the-fly OTF • Write leveling • Output driver calibration • Multipurpose register • TC of to +95°C 64ms, 8192-cycle refresh at to +85°C 32ms at +85°C to +95°C • Self refresh temperature SRT • Automatic self refresh ASR • Temperature-compensated self refresh TCSR mode • Very low current self refresh mode when room tem- perature Options • Configuration 512 Meg x 8 256 Meg x 16 • Timing Cycle time 1.071ns CL = 13 DDR3-1866 1.25ns CL = 11 DDR3-1600 1.5ns CL = 9 DDR3-1333 1.875ns CL = 7 DDR3-1066 • Product certification Automotive • Temperature Industrial TC +95°C Automotive TC +105°C • Power savings TCSR Marking 512M8 256M16 -107 -125 -15E -187E IT AT Table 1 Key Timing Parameters Speed Grade -1071, 2, 3 -1251, 2 -15E1 -187E Data Rate MT/s 1866 1600 1333 1066 Target tRCD-tRP-CL 13-13-13 11-11-11 9-9-9 7-7-7 Backward compatible to 1066, CL = 7 -187E . Backward compatible to 1333, CL = 9 -15E . Backward compatible to 1600, CL =11 tRCD ns tRP ns CL ns Micron Technology, Inc. reserves the right to change products or specifications without notice. 2014 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 4Gb x8, x16 Automotive DDR3L-RS SDRAM Description Table 2 Addressing Parameter Configuration Refresh count Row address Bank address Column address Page size 512 Meg x 8 64 Meg x 8 x 8 banks 8K 64K A[15:0] 8 BA[2:0] 1K A[9:0] 256 Meg x 16 32 Meg x 16 x 8 banks 8K 32K A[14:0] 8 BA[2:0] 1K A[9:0] Figure 1 DDR3L-RS Part Numbers

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4Gb x8, x16 Automotive DDR3L-RS SDRAM Description

Automotive DDR3L-RS SDRAM

MT41K512M8 64 Meg x 8 x 8 banks MT41K256M16 32 Meg x 16 x 8 banks

The 1.35V DDR3L-RS SDRAM device is a low-current self refresh version of the 1.35V DDR3L SDRAM device via the TCSR feature. Unless stated otherwise, the DDR3L-RS SDRAM device meets the functional and timing specifications listed in the equivalent density standard or automotive DDR3L SDRAM data sheet located on
• VDD = VDDQ = 1.35V
• Backward-compatible to VDD = VDDQ = 1.5V ±0.075V
• Differential bidirectional data strobe
• 8n-bit prefetch architecture
• Differential clock inputs CK, CK#
• 8 internal banks
• Nominal and dynamic on-die termination ODT
for data, strobe, and mask signals
• Programmable CAS READ latency CL
• Programmable posted CAS additive latency AL
• Programmable CAS WRITE latency CWL
• Fixed burst length BL of 8 and burst chop BC of 4
via the mode register set [MRS]
• Selectable BC4 or BL8 on-the-fly OTF
• Write leveling
• Output driver calibration
• Multipurpose register
• TC of to +95°C
64ms, 8192-cycle refresh at to +85°C 32ms at +85°C to +95°C
• Self refresh temperature SRT
• Automatic self refresh ASR
• Temperature-compensated self refresh TCSR
mode
• Very low current self refresh mode when room tem-
perature

Options
• Configuration 512 Meg x 8 256 Meg x 16
• Timing Cycle time 1.071ns CL = 13 DDR3-1866 1.25ns CL = 11 DDR3-1600 1.5ns CL = 9 DDR3-1333 1.875ns CL = 7 DDR3-1066
• Product certification Automotive
• Temperature Industrial TC +95°C Automotive TC +105°C
• Power savings TCSR

Marking
512M8 256M16
-107 -125 -15E -187E

IT AT

Table 1 Key Timing Parameters

Speed Grade -1071, 2, 3 -1251, 2 -15E1 -187E

Data Rate MT/s 1866 1600 1333 1066

Target tRCD-tRP-CL 13-13-13 11-11-11 9-9-9 7-7-7

Backward compatible to 1066, CL = 7 -187E . Backward compatible to 1333, CL = 9 -15E . Backward compatible to 1600, CL =11
tRCD ns
tRP ns

CL ns

Micron Technology, Inc. reserves the right to change products or specifications without notice. 2014 Micron Technology, Inc. All rights reserved.

Products and specifications discussed herein are subject to change by Micron without notice.
4Gb x8, x16 Automotive DDR3L-RS SDRAM Description

Table 2 Addressing

Parameter Configuration Refresh count Row address Bank address Column address Page size
512 Meg x 8 64 Meg x 8 x 8 banks
8K 64K A[15:0]
8 BA[2:0] 1K A[9:0]
256 Meg x 16 32 Meg x 16 x 8 banks
8K 32K A[14:0]
8 BA[2:0] 1K A[9:0]

Figure 1 DDR3L-RS Part Numbers

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived MT41K512M8RH-125MAIT:E Datasheet file may be downloaded here without warranties.

Datasheet ID: MT41K512M8RH-125MAIT:E 648394