MT41K128M16HA-15E:D

MT41K128M16HA-15E:D Datasheet

MT41K512M4 64 Meg x 4 x 8 banks MT41K256M8 32 Meg x 8 x 8 banks MT41K128M16 16 Meg x 16 x 8 banks

Part	Datasheet
MT41K128M16HA-15E:D	MT41K128M16HA-15E:D (pdf)

Related Parts	Information
MT41K128M16HA-15E IT:D	MT41K128M16HA-15E IT:D
MT41K128M16HA-187E:D	MT41K128M16HA-187E:D
MT41K256M8HX-15E:D	MT41K256M8HX-15E:D
MT41K256M8HX-187E:D	MT41K256M8HX-187E:D
MT41K512M4HX-15E:D	MT41K512M4HX-15E:D
MT41K512M4HX-187E:D	MT41K512M4HX-187E:D

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2Gb x4, x8, x16 DDR3L SDRAM Addendum Description 1.35V DDR3L SDRAM Addendum MT41K512M4 64 Meg x 4 x 8 banks MT41K256M8 32 Meg x 8 x 8 banks MT41K128M16 16 Meg x 16 x 8 banks DDR3L SDRAM 1.35V is a low voltage version of the DDR3 SDRAM 1.5V . Unless stated otherwise, DDR3L SDRAM meet the functional and timing specifications listed in the equivalent density DDR3 SDRAM data sheet located on • VDD = VDDQ = +1.35V 1.283V to 1.45V • Backward-compatible to VDD = VDDQ = +1.5V ±0.075V • Differential bidirectional data strobe • 8n-bit prefetch architecture • Differential clock inputs CK, CK# • 8 internal banks • Nominal and dynamic on-die termination ODT for data, strobe, and mask signals • Programmable CAS READ latency CL • Programmable posted CAS additive latency AL • Programmable CAS WRITE latency CWL • Fixed burst length BL of 8 and burst chop BC of 4 via the mode register set [MRS] • Selectable BC4 or BL8 on-the-fly OTF • Self refresh mode • TC of 0°C to +95°C 64ms, 8192-cycle refresh at 0°C to +85°C 32ms at +85°C to +95°C • Self refresh temperature SRT • Automatic self refresh ASR • Write leveling • Multipurpose register • Output driver calibration Options • Configuration 512 Meg x 4 256 Meg x 8 128 Meg x 16 • Timing cycle time 1.25ns CL = 11 DDR3-1600 1.5ns CL = 9 DDR3-1333 1.875ns CL = 7 DDR3-1066 Marking 512M4 256M8 128M16 DA HX -125 -15E -187E :D/ :H/ :M Table 1 Key Timing Parameters Speed Grade -1251, 2 -15E1 -187E Data Rate MT/s 1600 1333 1066 Target tRCD-tRP-CL 11-11-11 9-9-9 7-7-7 Notes Backward compatible to 1066, CL = 7 -187E . Backward compatible to 1333, CL = 9 -15E . tRCD ns tRP ns CL ns Micron Technology, Inc. reserves the right to change products or specifications without notice. 2010 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. Table 2 Addressing Parameter Configuration Refresh count Row address Bank address Column address 2Gb x4, x8, x16 DDR3L SDRAM Addendum Description 512 Meg x 4 64 Meg x 4 x 8 banks 8K 32K A[14:0] 8 BA[2:0] 2K A[11, 9:0] 256 Meg x 8 32 Meg x 8 x 8 banks 8K 32K A[14:0] 8 BA[2:0] 1K A[9:0] 128 Meg x 16 Meg x 16 x 8 banks 8K 16K A[13:0] 8 BA[2:0] 1K A[9:0] Micron Technology, Inc. reserves the right to change products or specifications without notice. 2010 Micron Technology, Inc. All rights reserved. 2Gb x4, x8, x16 DDR3L SDRAM Addendum Ball Assignments and Descriptions Ball Assignments and Descriptions

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2Gb x4, x8, x16 DDR3L SDRAM Addendum Description
1.35V DDR3L SDRAM Addendum

MT41K512M4 64 Meg x 4 x 8 banks MT41K256M8 32 Meg x 8 x 8 banks MT41K128M16 16 Meg x 16 x 8 banks

DDR3L SDRAM 1.35V is a low voltage version of the DDR3 SDRAM 1.5V . Unless stated otherwise, DDR3L SDRAM meet the functional and timing specifications listed in the equivalent density DDR3 SDRAM data sheet located on
• VDD = VDDQ = +1.35V 1.283V to 1.45V
• Backward-compatible to VDD = VDDQ = +1.5V ±0.075V
• Differential bidirectional data strobe
• 8n-bit prefetch architecture
• Differential clock inputs CK, CK#
• 8 internal banks
• Nominal and dynamic on-die termination ODT
for data, strobe, and mask signals
• Programmable CAS READ latency CL
• Programmable posted CAS additive latency AL
• Programmable CAS WRITE latency CWL
• Fixed burst length BL of 8 and burst chop BC of 4
via the mode register set [MRS]
• Selectable BC4 or BL8 on-the-fly OTF
• Self refresh mode
• TC of 0°C to +95°C 64ms, 8192-cycle refresh at 0°C to +85°C 32ms at +85°C to +95°C
• Self refresh temperature SRT
• Automatic self refresh ASR
• Write leveling
• Multipurpose register
• Output driver calibration

Options
• Configuration 512 Meg x 4 256 Meg x 8 128 Meg x 16
• Timing cycle time 1.25ns CL = 11 DDR3-1600 1.5ns CL = 9 DDR3-1333 1.875ns CL = 7 DDR3-1066

Marking
512M4 256M8 128M16

DA HX
-125 -15E -187E :D/ :H/ :M

Table 1 Key Timing Parameters

Speed Grade -1251, 2 -15E1 -187E

Data Rate MT/s 1600 1333 1066

Target tRCD-tRP-CL 11-11-11 9-9-9 7-7-7

Notes Backward compatible to 1066, CL = 7 -187E . Backward compatible to 1333, CL = 9 -15E .
tRCD ns
tRP ns

CL ns

Micron Technology, Inc. reserves the right to change products or specifications without notice. 2010 Micron Technology, Inc. All rights reserved.

Products and specifications discussed herein are subject to change by Micron without notice.

Table 2 Addressing

Parameter Configuration Refresh count Row address Bank address Column address
2Gb x4, x8, x16 DDR3L SDRAM Addendum Description
512 Meg x 4 64 Meg x 4 x 8 banks
8K 32K A[14:0]
8 BA[2:0] 2K A[11, 9:0]
256 Meg x 8 32 Meg x 8 x 8 banks
8K 32K A[14:0]
8 BA[2:0] 1K A[9:0]
128 Meg x 16 Meg x 16 x 8 banks
8K 16K A[13:0]
8 BA[2:0] 1K A[9:0]

Micron Technology, Inc. reserves the right to change products or specifications without notice. 2010 Micron Technology, Inc. All rights reserved.
2Gb x4, x8, x16 DDR3L SDRAM Addendum Ball Assignments and Descriptions

Ball Assignments and Descriptions

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived MT41K128M16HA-15E:D Datasheet file may be downloaded here without warranties.

Datasheet ID: MT41K128M16HA-15E:D 648392