MT28F128J3, MT28F640J3, MT28F320J3
Part | Datasheet |
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MT28F320J3BS-11 MET (pdf) |
Related Parts | Information |
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MT28F320J3FS-11 ET TR |
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MT28F128J3FS-12 ET TR |
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MT28F128J3RG-12 ET TR |
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MT28F320J3RG-11 ET TR |
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MT28F640J3FS-115 ET TR |
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MT28F640J3RG-115 ET TR |
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MT28F320J3FS-11 MET TR |
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MT28F320J3RG-11 MET |
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MT28F320J3RG-11 GMET TR |
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MT28F320J3RG-11 GMET |
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MT28F640J3RG-115 GMET |
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MT28F320J3FS-11 MET |
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MT28F640J3FS-115 XMET TR |
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MT28F640J3FS-115 XMET |
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MT28F640J3FS-115 MET TR |
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MT28F640J3FS-115 MET |
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MT28F640J3FS-115 GMET TR |
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MT28F640J3FS-115 GMET |
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MT28F640J3BS-115 MET TR |
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MT28F640J3BS-115 MET |
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MT28F640J3RG-115 MET |
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MT28F640J3BS-115 GMET |
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MT28F640J3RG-115 XMET TR |
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MT28F640J3BS-115 ET TR |
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MT28F640J3BS-115 ET |
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MT28F640J3BS-115 GMET TR |
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MT28F128J3RP-12 ET TR |
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MT28F640J3RP-115 MET TR |
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MT28F640J3RP-115 MET |
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MT28F128J3BS-12 ET |
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MT28F128J3BS-12 ET TR |
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MT28F640J3RP-115 ET TR |
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MT28F320J3BS-11 ET |
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MT28F128J3BS-12 MET |
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MT28F128J3BS-12 MET TR |
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MT28F128J3FS-12 MET |
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MT28F128J3FS-12 MET TR |
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MT28F128J3RG-12 MET |
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MT28F320J3BS-11 GMET TR |
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MT28F128J3RP-12 ET |
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MT28F640J3RG-115 MET TR |
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MT28F128J3RP-12 MET |
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MT28F640J3RP-115 ET |
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MT28F128J3RP-12 MET TR |
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MT28F640J3RG-115 GMET TR |
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MT28F320J3BS-11 ET TR |
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MT28F320J3BS-11 GMET |
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MT28F640J3RG-115 XMET |
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MT28F320J3BS-11 MET TR |
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MT28F320J3FS-11 GMET |
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MT28F320J3FS-11 GMET TR |
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MT28F128J3RG-12 MET TR |
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MT28F320J3RP-11 MET TR |
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MT28F320J3RP-11 MET |
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MT28F320J3RP-11 ET TR |
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MT28F320J3RG-11 MET TR |
PDF Datasheet Preview |
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MEMORY 128Mb, 64Mb, 32Mb Q-FLASH MEMORY MT28F128J3, MT28F640J3, MT28F320J3 Memory Organization • x8/x16 • One hundred twenty-eight 128KB erase blocks 128Mb • Sixty-four 128KB erase blocks 64Mb • Thirty-two 128KB erase blocks 32Mb VCC, VCCQ, and VPEN voltages: • 2.7V to 3.6V VCC operation • 2.7V to 3.6V application programming Interface Asynchronous Page Mode Reads: • 120ns/25ns read access time 128Mb • 115ns/25ns read access time 64Mb • 110ns/25ns read access time 32Mb Manufacturer’s Identification Code ManID • 0x2Ch • 0x89h Industry-standard pinout Inputs and outputs are fully TTL-compatible Common Flash Interface CFI and Scalable Command Set Automatic write and erase algorithm 5.6µs-per-byte effective programming time using write buffer 128-bit protection register • 64-bit unique device identifier • 64-bit user-programmable OTP cells Enhanced data protection feature with VPEN = VSS • Flexible sector locking • Sector erase/program lockout during power transition Security block features Contact factory for availability 100,000 ERASE cycles per block Automatic suspend options: • Block Erase Suspend-to-Read • Block Erase Suspend-to-Program • Program Suspend-to-Read Figure 1 56-Pin TSOP Type I Figure 2 64-Ball FBGA Options Timing • 110ns 32Mb • 115ns 64Mb • 120ns 128Mb Operating Temperature Range • Extended Temperature -40°C to +85°C Packages • 56-pin standard TSOP Type I • 56-pin lead-free TSOP Type I • 64-ball standard FBGA 1.00mm pitch • 64-ball lead-free FBGA 1.00mm pitch Manufacturer’s Identification Code ManID • Micron 0x2Ch • Intel 0x89h Mark -11 -115 -12 RG RP FS BS Part Number Example: MT28F640J3RG-115ET 2000 Micron Technology, Inc. AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. 128Mb, 64Mb, 32Mb Q-FLASH MEMORY Table of Contents Features Options Mark General Description 56-Pin TSOP Type I 64-Ball FBGA Part Numbering Information Valid Part Number Combinations Device Marking Memory Architecture Read Output Disable. Standby Reset/Power-Down. Read Query Read Identifier Codes Write. Bus Operation Command Definitions READ ARRAY Command READ QUERY MODE Command Query Structure Output Query Structure Overview CFI Query Identification String System Interface Information. Device Geometry Definition Primary Vendor-Specific Extended-Query Table READ IDENTIFIER CODES Command. READ STATUS REGISTER Command. CLEAR STATUS REGISTER Command. BLOCK ERASE Command BLOCK ERASE SUSPEND Command WRITE-to-BUFFER Command. BYTE/WORD PROGRAM Commands. PROGRAM SUSPEND Command SET READ CONFIGURATION Command READ Configuration STS CONFIGURATION Command SET BLOCK LOCK BITS Command CLEAR BLOCK LOCK BITS Command PROTECTION REGISTER PROGRAM Command Reading the Protection Register Programming the Protection Register Locking the Protection Register Design Considerations Five-Line Output Control STS and Block Erase, Program, and Lock Bit Configuration Polling Power Supply Decoupling Reducing Overshoots and Undershoots When Using Buffers or Transceivers Vcc, Vpen, and RP# Transitions Micron Technology, Inc., reserves the right to change products or specifications without notice. 2000 Micron Technology. Inc. |
Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived MT28F320J3BS-11MET Datasheet file may be downloaded here without warranties.