MT18VDDT6472G-262G3

MT18VDDT6472G-262G3 Datasheet

MT18VDDT3272 256MB MT18VDDT6472 512MB MT18VDDT12872 1GB MT18VDDT25672 2GB

Part	Datasheet
MT18VDDT6472G-262G3	MT18VDDT6472G-262G3 (pdf)

Related Parts	Information
MT18VDDT6472AG-26AG4	MT18VDDT6472AG-26AG4
MT18VDDT6472G-265G3	MT18VDDT6472G-265G3
MT18VDDT12872Y-265D2	MT18VDDT12872Y-265D2
MT18VDDT25672G-265A2	MT18VDDT25672G-265A2
MT18VDDT6472AG-335G4	MT18VDDT6472AG-335G4
MT18VDDT6472AG-265G4	MT18VDDT6472AG-265G4
MT18VDDT6472AG-262G4	MT18VDDT6472AG-262G4

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256MB, 512MB, 1GB, 2GB x72, ECC, SR 184-PIN DDR SDRAM RDIMM DDR SDRAM REGISTERED DIMM MT18VDDT3272 256MB MT18VDDT6472 512MB MT18VDDT12872 1GB MT18VDDT25672 2GB For the latest data sheet, please refer to the Web site: • 184-pin, dual in-line memory module DIMM • Fast data transfer rates PC1600 or PC2100 • Utilizes 200 MT/s, 266 MT/s DDR SDRAM components • Registered inputs with one-clock delay • Phase-lock loop PLL clock driver to reduce loading • Supports ECC error detection and correction • 256MB 32 Meg x 72 , 512MB 64 Meg x 72 , 1GB 128 Meg x 72 , or 2GB 256 Meg x 72 • VDD = VDDQ = +2.5V • VDDSPD = +2.3V to +3.6V • 2.5V I/O SSTL_2 compatible • Commands entered on each positive CK edge • DQS edge-aligned with data for READs center- aligned with data for WRITEs • Internal, pipelined double data rate DDR architecture two data accesses per clock cycle • Bidirectional data strobe DQS transmitted/received with source-synchronous data capture • Differential clock inputs CK and CK# • Four internal device banks for concurrent operation • Programmable burst lengths 2, 4, or 8 • Auto precharge option • Auto Refresh and Self Refresh Modes • 15.625µs 256MB , 7.8125µs 512MB ,1GB, and 2GB maximum average periodic refresh interval • Serial Presence Detect SPD with EEPROM • Programmable READ CAS latency • Gold edge contacts Figure 1 184-Pin DIMM MO-206 Standard 1.70in. 43.18mm Low Profile 1.20in. 30.48mm OPTIONS MARKING • Package 184-pin DIMM standard 184-pin DIMM lead-free 1 • Memory clock/Speed, CAS Latency2 7.5ns 133 MHz 266 MT/s, CL = 2 7.5ns 133 MHz 266 MT/s, CL = 2 -2621 -26A1 7.5ns 133 MHz 266 MT/s, CL = -265 10ns 100 MHz 200 MT/s, CL = 2 -202 • PCB Standard 1.75in. 44.45mm See Table 2 note Low-Profile 1.20in. 30.48mm See Table 2 note NOTE Contact Micron for product availability. CL = CAS READ latency registered mode adds one clock cycle to CL. Table 1 Address Table Refresh Count Row Addressing Device Bank Addressing Device Configuration Column Addressing Module Rank Addressing 256MB 4K 4 BA0, BA1 128Mb 32 Meg x 4 2K A11 1 S0# 512MB 8K 4 BA0, BA1 256Mb 64 Meg x 4 2K A11 1 S0# The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 6, Burst Definition Table, on page Figure 5 Mode Register Definition Diagram 256MB Module BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mode Register Mx 0* 0* Operating Mode CAS Latency BT Burst Length * M13 and M12 BA0 and BA1 must be “0, 0” to select the base mode register vs. the extended mode register . 512MB and 1GB Modules BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mode Register Mx 0* 0* Operating Mode CAS Latency BT Burst Length * M14 and M13 BA0 and BA1 must be “0, 0” to select the base mode register vs. the extended mode register . 2GB Module BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mode Register Mx 0* 0* Operating Mode CAS Latency BT Burst Length * M15 and M14 BA1 and BA0 must be “0, 0” to select the base mode register vs. the extended mode register . Burst Length M2 M1 M0 0 00 0 01 0 10 0 11 1 00 1 01 1 10 1 11 M3 = 0 Reserved 2 4 8 Reserved Burst Type Sequential Interleaved M6 M5 M4 000 001 010 011 100 101 110 111 CAS Latency Reserved 2 Reserved M13 M12 M11 M10 M9 M8 M7 0 00 0 10 - - - - - -- M6-M0 Valid Operating Mode Normal Operation Normal Operation/Reset DLL All other states reserved Micron Technology, Inc., reserves the right to change products or specifications without notice. 2004 Micron Technology, Inc. All rights reserved. 256MB, 512MB, 1GB, 2GB x72, ECC, SR 184-PIN DDR SDRAM RDIMM Table 6 Burst Definition Table BURST LENGTH STARTING COLUMN ADDRESS ORDER OF ACCESSES WITHIN A BURST TYPE = TYPE = SEQUENTIAL INTERLEAVED A1 A0 0-1-2-3 0-1-2-3

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256MB, 512MB, 1GB, 2GB x72, ECC, SR 184-PIN DDR SDRAM RDIMM

DDR SDRAM REGISTERED DIMM

MT18VDDT3272 256MB MT18VDDT6472 512MB MT18VDDT12872 1GB MT18VDDT25672 2GB

For the latest data sheet, please refer to the Web
site:
• 184-pin, dual in-line memory module DIMM
• Fast data transfer rates PC1600 or PC2100
• Utilizes 200 MT/s, 266 MT/s DDR SDRAM
components
• Registered inputs with one-clock delay
• Phase-lock loop PLL clock driver to reduce loading
• Supports ECC error detection and correction
• 256MB 32 Meg x 72 , 512MB 64 Meg x 72 ,
1GB 128 Meg x 72 , or 2GB 256 Meg x 72
• VDD = VDDQ = +2.5V
• VDDSPD = +2.3V to +3.6V
• 2.5V I/O SSTL_2 compatible
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs center-
aligned with data for WRITEs
• Internal, pipelined double data rate DDR
architecture two data accesses per clock cycle
• Bidirectional data strobe DQS transmitted/received
with source-synchronous data capture
• Differential clock inputs CK and CK#
• Four internal device banks for concurrent operation
• Programmable burst lengths 2, 4, or 8
• Auto precharge option
• Auto Refresh and Self Refresh Modes
• 15.625µs 256MB , 7.8125µs 512MB ,1GB, and 2GB
maximum average periodic refresh interval
• Serial Presence Detect SPD with EEPROM
• Programmable READ CAS latency
• Gold edge contacts

Figure 1 184-Pin DIMM MO-206

Standard 1.70in. 43.18mm

Low Profile 1.20in. 30.48mm

OPTIONS

MARKING
• Package
184-pin DIMM standard
184-pin DIMM lead-free 1
• Memory clock/Speed, CAS Latency2
7.5ns 133 MHz 266 MT/s, CL = 2
7.5ns 133 MHz 266 MT/s, CL = 2
-2621 -26A1
7.5ns 133 MHz 266 MT/s, CL =
-265
10ns 100 MHz 200 MT/s, CL = 2
-202
• PCB Standard 1.75in. 44.45mm

See Table 2 note

Low-Profile 1.20in. 30.48mm

See Table 2 note

NOTE Contact Micron for product availability. CL = CAS READ latency registered mode adds one clock cycle to CL.

Table 1 Address Table

Refresh Count Row Addressing Device Bank Addressing Device Configuration Column Addressing Module Rank Addressing
256MB
4K 4 BA0, BA1 128Mb 32 Meg x 4 2K A11
1 S0#
512MB
8K 4 BA0, BA1 256Mb 64 Meg x 4 2K A11
1 S0#
The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 6, Burst Definition Table, on page

Figure 5 Mode Register Definition Diagram
256MB Module

BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mode Register Mx 0* 0* Operating Mode CAS Latency BT Burst Length
* M13 and M12 BA0 and BA1 must be “0, 0” to select the base mode register vs. the extended mode register .
512MB and 1GB Modules

BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mode Register Mx 0* 0* Operating Mode CAS Latency BT Burst Length
* M14 and M13 BA0 and BA1 must be “0, 0” to select the base mode register vs. the extended mode register .
2GB Module

BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mode Register Mx
0* 0*

Operating Mode

CAS Latency BT Burst Length
* M15 and M14 BA1 and BA0 must be “0, 0” to select the base mode register vs. the extended mode register .

Burst Length

M2 M1 M0 0 00 0 01 0 10 0 11 1 00 1 01 1 10 1 11

M3 = 0 Reserved
2 4 8 Reserved

Burst Type

Sequential

Interleaved

M6 M5 M4 000 001 010 011 100 101 110 111

CAS Latency Reserved 2 Reserved

M13 M12 M11 M10 M9 M8 M7 0 00 0 10 - - - - - --

M6-M0 Valid

Operating Mode Normal Operation Normal Operation/Reset DLL All other states reserved

Micron Technology, Inc., reserves the right to change products or specifications without notice. 2004 Micron Technology, Inc. All rights reserved.
256MB, 512MB, 1GB, 2GB x72, ECC, SR 184-PIN DDR SDRAM RDIMM

Table 6 Burst Definition Table

BURST LENGTH

STARTING COLUMN ADDRESS

ORDER OF ACCESSES WITHIN A BURST

TYPE =

TYPE =

SEQUENTIAL INTERLEAVED

A1 A0
0-1-2-3
0-1-2-3

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Datasheet ID: MT18VDDT6472G-262G3 648355