MT18VDDT12872AY-40BD1

MT18VDDT12872AY-40BD1 Datasheet

MT18VDDT3272A 256MB

Part	Datasheet
MT18VDDT12872AY-40BD1	MT18VDDT12872AY-40BD1 (pdf)

Related Parts	Information
MT18VDDT12872AY-40BF1	MT18VDDT12872AY-40BF1
MT18VDDT12872AG-40BF1	MT18VDDT12872AG-40BF1
MT18VDDT12872AY-335F1	MT18VDDT12872AY-335F1
MT18VDDT6472AY-40BG4	MT18VDDT6472AY-40BG4
MT18VDDT12872AG-335D1	MT18VDDT12872AG-335D1
MT18VDDT12872AG-40BD1	MT18VDDT12872AG-40BD1
MT18VDDT12872AG-335F1	MT18VDDT12872AG-335F1
MT18VDDT12872AY-335D1	MT18VDDT12872AY-335D1
MT18VDDT6472AG-40BG4	MT18VDDT6472AG-40BG4

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256MB, 512MB, 1GB x72, ECC, DR , PC3200 184-PIN DDR SDRAM UDIMM DDR SDRAM UNBUFFERED DIMM MT18VDDT3272A 256MB MT18VDDT6472A 512MB MT18VDDT12872A 1GB For the latest data sheet, please refer to the Web site: • 184-pin dual in-line memory module DIMM • Fast data transfer rates PC3200 • CAS Latency 3 • Utilizes 400 MT/s DDR SDRAM components • Supports ECC error detection and correction • 256MB 32 Meg x 72 , 512MB 64 Meg x 72 , and 1GB 128 Meg x 72 • VDD = VDDQ = +2.6V • VDDSPD = +2.3V to +3.6V • 2.6V I/O SSTL_2 compatible • Commands entered on each positive CK edge • DQS edge-aligned with data for READs center- aligned with data for WRITEs • Internal, pipelined double data rate DDR architecture two data accesses per clock cycle • Bidirectional data strobe DQS transmitted/received with source-synchronous data capture • Differential clock inputs CK and CK# • Four internal device banks for concurrent operation • Programmable burst lengths 2, 4, or 8 • Auto precharge option • Auto Refresh and Self Refresh Modes • 15.6µs 256MB , 7.8125µs 512MB, 1GB maximum average periodic refresh interval • Serial Presence Detect SPD with EEPROM • Programmable READ CAS latency • Gold edge contacts Figure 1 184-Pin DIMM MO-206 1.25in. 31.75mm OPTIONS • Package 184-pin DIMM Standard 184-pin DIMM Lead-free • Memory Clock/Speed, CAS Latency 5ns 200MHz , 400MT/s, CL = 3 • PCB Standard 1.25in. 31.75mm MARKING -40B Table 1 Address Table Refresh Count Row Addressing Device Bank Addressing Device Configuration Column Addressing Module Rank Addressing 256MB 4K 4 BA0, BA1 128Mb 16 Meg x 8 1K 2 S0#, S1# 512MB 8K 4 BA0, BA1 256Mb 32 Meg x 8 1K 2 S0#, S1# 8K 4 BA0, BA1 512Mb 64 Meg x 8 2K A11 2 S0#, S1# 2004 Micron Technology, Inc. PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. 256MB, 512MB, 1GB x72, ECC, DR , PC3200 184-PIN DDR SDRAM UDIMM Table 2 Part Numbers and Timing Parameters MT18VDDT3272AG-40B__ MT18VDDT3272AY-40B__ MT18VDDT6472AG-40B__ MT18VDDT6472AY-40B__ MT18VDDT12872AG-40B__ MT18VDDT12872AY-40B__ MODULE DENSITY 256MB 512MB CONFIGURATION MODULE MEMORY CLOCK/ BANDWIDTH DATA BIT RATE 32 Meg x 72 32 Meg x 72 GB/s GB/s 5ns/400 MT/s 5ns/400 MT/s 64 Meg x 72 64 Meg x 72 128 Meg x 72 GB/s GB/s GB/s 5ns/400 MT/s 5ns/400 MT/s 5ns/400 MT/s The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 6, Burst Definition Table, on page Read Latency The READ latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The latency can be set to 3, or 2 clocks, as shown in Figure 5, CAS Latency Diagram, on page If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available nominally coincident with clock edge n + m. Table 7, CAS Latency CL Table, on page 9, indicates the operating frequencies at which each CAS latency setting can be used. Reserved states should not be used as unknown operation or incompatibility with future versions may result. Figure 4 Mode Register Definition Diagram 256MB Module BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mode Register Mx 0* 0* Operating Mode CAS Latency BT Burst Length * M13 and M12 BA1and BA0 must be “0, 0” to select the base mode register vs. the extended mode register . 512MB, 1GB Modules BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mode Register Mx 0* 0* Operating Mode CAS Latency BT Burst Length * M14 and M13 BA1 and BA0 must be “0, 0” to select the base mode register vs. the extended mode register . M2 M1 M0 0 00 0 01 0 10 0 11 1 00 1 01 1 10 1 11 Burst Length M3 = 0 Reserved 2 4 8 Reserved M3 = 1 Reserved 2 4 8 Reserved Burst Type Sequential Interleaved M6 M5 M4 000 001 010 011 100 101 110 111 CAS Latency Reserved 2 3 Reserved M12 M11 M10 M9 M8 M7 0 00 0 10 - - - - -- M6-M0 Valid Operating Mode Normal Operation Normal Operation/Reset DLL All other states reserved Micron Technology, Inc., reserves the right to change products or specifications without notice. 2004 Micron Technology, Inc. 256MB, 512MB, 1GB x72, ECC, DR , PC3200 184-PIN DDR SDRAM UDIMM Table 6 Burst Definition Table BURST LENGTH STARTING COLUMN ADDRESS ORDER OF ACCESSES WITHIN A BURST TYPE = TYPE = SEQUENTIAL INTERLEAVED A1 A0 0-1-2-3 0-1-2-3 1-2-3-0

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256MB, 512MB, 1GB x72, ECC, DR , PC3200 184-PIN DDR SDRAM UDIMM

DDR SDRAM UNBUFFERED DIMM

MT18VDDT3272A 256MB

MT18VDDT6472A 512MB

MT18VDDT12872A 1GB

For the latest data sheet, please refer to the Web site:
• 184-pin dual in-line memory module DIMM
• Fast data transfer rates PC3200
• CAS Latency 3
• Utilizes 400 MT/s DDR SDRAM components
• Supports ECC error detection and correction
• 256MB 32 Meg x 72 , 512MB 64 Meg x 72 , and 1GB
128 Meg x 72
• VDD = VDDQ = +2.6V
• VDDSPD = +2.3V to +3.6V
• 2.6V I/O SSTL_2 compatible
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs center-
aligned with data for WRITEs
• Internal, pipelined double data rate DDR
architecture two data accesses per clock cycle
• Bidirectional data strobe DQS transmitted/received
with source-synchronous data capture
• Differential clock inputs CK and CK#
• Four internal device banks for concurrent operation
• Programmable burst lengths 2, 4, or 8
• Auto precharge option
• Auto Refresh and Self Refresh Modes
• 15.6µs 256MB , 7.8125µs 512MB, 1GB maximum
average periodic refresh interval
• Serial Presence Detect SPD with EEPROM
• Programmable READ CAS latency
• Gold edge contacts

Figure 1 184-Pin DIMM MO-206
1.25in. 31.75mm

OPTIONS
• Package 184-pin DIMM Standard 184-pin DIMM Lead-free
• Memory Clock/Speed, CAS Latency 5ns 200MHz , 400MT/s, CL = 3
• PCB Standard 1.25in. 31.75mm

MARKING
-40B

Table 1 Address Table

Refresh Count Row Addressing Device Bank Addressing Device Configuration Column Addressing Module Rank Addressing
256MB
4K 4 BA0, BA1 128Mb 16 Meg x 8 1K 2 S0#, S1#
512MB
8K 4 BA0, BA1 256Mb 32 Meg x 8 1K 2 S0#, S1#
8K 4 BA0, BA1 512Mb 64 Meg x 8 2K A11 2 S0#, S1#
2004 Micron Technology, Inc.

PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
256MB, 512MB, 1GB x72, ECC, DR , PC3200 184-PIN DDR SDRAM UDIMM

Table 2 Part Numbers and Timing Parameters

MT18VDDT3272AG-40B__ MT18VDDT3272AY-40B__ MT18VDDT6472AG-40B__ MT18VDDT6472AY-40B__ MT18VDDT12872AG-40B__ MT18VDDT12872AY-40B__

MODULE DENSITY
256MB 512MB

CONFIGURATION MODULE MEMORY CLOCK/ BANDWIDTH DATA BIT RATE
32 Meg x 72 32 Meg x 72

GB/s GB/s
5ns/400 MT/s 5ns/400 MT/s
64 Meg x 72 64 Meg x 72 128 Meg x 72

GB/s GB/s GB/s
5ns/400 MT/s 5ns/400 MT/s 5ns/400 MT/s
The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 6, Burst Definition Table, on page

Read Latency

The READ latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The latency can be set to 3, or 2 clocks, as shown in Figure 5, CAS Latency Diagram, on page

If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available nominally coincident with clock edge n + m. Table 7, CAS Latency CL Table, on page 9, indicates the operating frequencies at which each CAS latency setting can be used.

Reserved states should not be used as unknown operation or incompatibility with future versions may result.

Figure 4 Mode Register Definition Diagram
256MB Module

BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mode Register Mx 0* 0* Operating Mode CAS Latency BT Burst Length
* M13 and M12 BA1and BA0 must be “0, 0” to select the base mode register vs. the extended mode register .
512MB, 1GB Modules

BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mode Register Mx 0* 0* Operating Mode CAS Latency BT Burst Length
* M14 and M13 BA1 and BA0 must be “0, 0” to select the base mode register vs. the extended mode register .

M2 M1 M0 0 00 0 01 0 10 0 11 1 00 1 01 1 10 1 11

Burst Length

M3 = 0 Reserved
2 4 8 Reserved

M3 = 1 Reserved
2 4 8 Reserved

Burst Type

Sequential

Interleaved

M6 M5 M4 000 001 010 011 100 101 110 111

CAS Latency Reserved 2 3 Reserved

M12 M11 M10 M9 M8 M7 0 00 0 10 - - - - --

M6-M0 Valid

Operating Mode Normal Operation Normal Operation/Reset DLL All other states reserved

Micron Technology, Inc., reserves the right to change products or specifications without notice. 2004 Micron Technology, Inc.
256MB, 512MB, 1GB x72, ECC, DR , PC3200 184-PIN DDR SDRAM UDIMM

Table 6 Burst Definition Table

BURST LENGTH

STARTING COLUMN ADDRESS

ORDER OF ACCESSES WITHIN A BURST

TYPE =

TYPE =

SEQUENTIAL INTERLEAVED

A1 A0
0-1-2-3
0-1-2-3
1-2-3-0

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Datasheet ID: MT18VDDT12872AY-40BD1 648354