MT18HVS25672 P K 2GB MT18HVS51272 P K 4GB
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MT18HVS51272PKY-667A1 (pdf) |
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2GB, 4GB x72, DR 244-Pin DDR2 VLP Mini-RDIMM Features DDR2 SDRAM VLP Mini-RDIMM MT18HVS25672 P K 2GB MT18HVS51272 P K 4GB For component data sheets, refer to Micron’s Web site: • 244-pin, very low profile mini registered dual in-line memory module VLP Mini-RDIMM • Fast data transfer rates PC2-4200, PC2-5300, or PC2-6400 • 2GB 256 Meg x 8 , 4GB 512 Meg x 8 • Supports ECC error detection and correction • VDD = VDDQ = +1.8V • VDDSPD = +1.7V to +3.6V • JEDEC-standard 1.8V I/O SSTL_18-compatible • Differential data strobe DQS, DQS# option • 4n-bit prefetch architecture • Multiple internal device banks for concurrent operation • Supports redundant output strobe RDQS/RDQS# • Programmable CAS# latency CL • Posted CAS# additive latency AL • WRITE latency = READ latency - 1 tCK • Programmable burst lengths BL 4 or 8 • Adjustable data-output drive strength • 64ms, 8,192-cycle refresh • On-die termination ODT • Serial presence-detect SPD with EEPROM • Gold edge contacts • Dual rank, TwinDieTM 2COB DRAM devices Figure 1 244-Pin VLP Mini-RDIMM PCB height 18.2mm 0.72in Options • Parity • Operating temperature1 Commercial 0°C TA +70°C Industrial TA +85°C • Package 244-pin DIMM Pb-free • Frequency/CAS latency2 2.5ns CL = 5 DDR2-800 3 3.0ns CL = 5 DDR2-667 3.75ns CL = 4 DDR2-533 Marking None I -80E -667 -53E Notes Contact Micron for industrial temperature module offerings. CL = CAS READ latency registered mode will add one clock cycle to CL. Not available in 4GB module density. Table 1 Key Timing Parameters Speed Data Rate MT/s tRCD Grade Industry Nomenclature CL = 5 CL = 4 CL = 3 -80E -667 -53E PC2-6400 PC2-5300 PC2-4200 Micron Technology, Inc., reserves the right to change products or specifications without notice. 2007 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 2GB, 4GB x72, DR 244-Pin DDR2 VLP Mini-RDIMM Features Table 2 Addressing Parameter Refresh count Row address Device bank address Device page size per bank Device configuration Column address Module rank address 8K 16K 8 BA0, BA1 1KB 2Gb TwinDie 256 Meg x 8 1K 2 S0#, S1# |
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