MT18LSDT12872AG-133C1

MT18LSDT12872AG-133C1 Datasheet

MT9LSDT6472A - 512MB MT18LSDT12872A - 1GB

Part	Datasheet
MT18LSDT12872AG-133C1	MT18LSDT12872AG-133C1 (pdf)

Related Parts	Information
MT18LSDT12872AG-13EC1	MT18LSDT12872AG-13EC1
MT9LSDT6472AG-133C1	MT9LSDT6472AG-133C1

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512MB SR , 1GB DR x72, ECC 168-Pin SDRAM UDIMM Features Synchronous DRAM Module MT9LSDT6472A - 512MB MT18LSDT12872A - 1GB For the latest data sheet, refer to Micron’s Web site: • PC100- and PC133-compliant • 168-pin, dual in-line memory module DIMM • Unbuffered, ECC-optimized pinout • 512MB 64 Meg x 72 and 1GB 128 Meg x 72 • Single +3.3V power supply • Fully synchronous all signals registered on positive edge of system clock • Internal pipelined operation column address can be changed every clock cycle • Internal SDRAM banks for hiding row access/ precharge • Programmable burst lengths 1, 2, 4, 8, or full page • Auto precharge, includes concurrent auto precharge, and auto refresh modes • Self refresh mode • 64ms, 8,192-cycle refresh • LVTTL-compatible inputs and outputs • Serial presence-detect SPD • Gold edge contacts Table 1: Timing Parameters CL = CAS READ latency Access Time Module Clock Setup Marking Frequency CL = 2 CL = 3 Time -13E -133 133 MHz 5.4ns 133 MHz 5.4ns Hold Time Figure 1 168-Pin DIMM MO-161 Standard 1.375in./34.93mm Low Profile 1.125in./28.58mm Options • Package 168-pin DIMM standard 168-pin DIMM lead-free • Frequency/CAS latency 7.5ns 133 MHz /CL = 2 7.5ns 133 MHz /CL = 3 • PCB Standard 1.375in./34.93mm Low-Profile 1.125in./28.58mm Marking -13E -133 See note 1 on page 2 See note 1 on page 2 Notes Contact Micron for product availability. Table 2 Address Table Parameter Refresh Count Device Banks Device Configuration Row Addressing Column Addressing Module Ranks 512MB 8K 4 BA0, BA1 512Mb 64 Meg x 8 8K 2K A11 1 S0#, S2# 8K 4 BA0, BA1 512Mb 64 Meg x 8 8K 2K A11 2 S0#, S2# S1#, S3# Micron Technology, Inc., reserves the right to change products or specifications without notice. 2002 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 512MB SR , 1GB DR x72, ECC 168-Pin SDRAM UDIMM Features The ordering of accesses within a burst is determined by the burst length, the burst type, and the starting column address, as shown in Table 6 on page Micron Technology, Inc., reserves the right to change products or specifications without notice. 2002 Micron Technology, Inc. All rights reserved. 512MB SR , 1GB DR x72, ECC 168-Pin SDRAM UDIMM Mode Register Definition Figure 5: Mode Register Definition Diagram A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus 12 11 10 9 8 7 Reserved WB Op Mode 6 543 CAS Latency BT 2 10 Burst Length Mode Register Mx Program M12, M11, M10 = “0, 0, 0” to ensure compatibility with future devices. M9 0 1 M2 M1 M0 000 001 010 011 100 101 110 111 Burst Length M3 = 0 1 2 4 8 Reserved Full Page M3 = 1 2 4 8 Reserved Burst Type Sequential Interleaved M6 M5 M4 00 0 00 1 01 0 01 1 10 0 10 1 11 0 11 1 CAS Latency Reserved 2 3 Reserved Operating Mode Defined Standard Operation All Other States Reserved Write Burst Mode Programmed Burst Length Single Location Access Micron Technology, Inc., reserves the right to change products or specifications without notice. 2002 Micron Technology, Inc. All rights reserved. 512MB SR , 1GB DR x72, ECC 168-Pin SDRAM UDIMM Mode Register Definition Table 6 Burst Definition Table Burst Length Full Page y Starting Column Address n = A11 location 0-y Order of Accesses Within a Burst Type = Sequential Type = Interleaved 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3 1-0-3-2-3-0-1 3-2-1-0

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512MB SR , 1GB DR x72, ECC 168-Pin SDRAM UDIMM Features

Synchronous DRAM Module

MT9LSDT6472A - 512MB MT18LSDT12872A - 1GB

For the latest data sheet, refer to Micron’s Web site:
• PC100- and PC133-compliant
• 168-pin, dual in-line memory module DIMM
• Unbuffered, ECC-optimized pinout
• 512MB 64 Meg x 72 and 1GB 128 Meg x 72
• Single +3.3V power supply
• Fully synchronous all signals registered on positive
edge of system clock
• Internal pipelined operation column address can
be changed every clock cycle
• Internal SDRAM banks for hiding row access/
precharge
• Programmable burst lengths 1, 2, 4, 8, or full page
• Auto precharge, includes concurrent auto
precharge, and auto refresh modes
• Self refresh mode
• 64ms, 8,192-cycle refresh
• LVTTL-compatible inputs and outputs
• Serial presence-detect SPD
• Gold edge contacts

Table 1:

Timing Parameters CL = CAS READ latency

Access Time

Module Clock

Setup

Marking Frequency CL = 2 CL = 3 Time
-13E -133
133 MHz 5.4ns
133 MHz
5.4ns

Hold Time

Figure 1 168-Pin DIMM MO-161

Standard 1.375in./34.93mm

Low Profile 1.125in./28.58mm

Options
• Package 168-pin DIMM standard 168-pin DIMM lead-free
• Frequency/CAS latency 7.5ns 133 MHz /CL = 2 7.5ns 133 MHz /CL = 3
• PCB Standard 1.375in./34.93mm

Low-Profile 1.125in./28.58mm

Marking
-13E -133

See note 1 on page 2

See note 1 on page 2

Notes Contact Micron for product availability.

Table 2 Address Table

Parameter Refresh Count Device Banks Device Configuration Row Addressing Column Addressing Module Ranks
512MB
8K 4 BA0, BA1 512Mb 64 Meg x 8 8K 2K A11 1 S0#, S2#
8K 4 BA0, BA1 512Mb 64 Meg x 8 8K 2K A11 2 S0#, S2# S1#, S3#

Micron Technology, Inc., reserves the right to change products or specifications without notice. 2002 Micron Technology, Inc. All rights reserved.

Products and specifications discussed herein are subject to change by Micron without notice.
512MB SR , 1GB DR x72, ECC 168-Pin SDRAM UDIMM Features
The ordering of accesses within a burst is determined by the burst length, the burst type, and the starting column address, as shown in Table 6 on page

Micron Technology, Inc., reserves the right to change products or specifications without notice. 2002 Micron Technology, Inc. All rights reserved.
512MB SR , 1GB DR x72, ECC 168-Pin SDRAM UDIMM Mode Register Definition

Figure 5:

Mode Register Definition Diagram

A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
12 11 10 9 8 7 Reserved WB Op Mode
6 543 CAS Latency BT
2 10 Burst Length

Mode Register Mx

Program M12, M11, M10 = “0, 0, 0”
to ensure compatibility with future devices.

M9 0 1

M2 M1 M0 000 001 010 011 100 101 110 111

Burst Length

M3 = 0 1 2 4 8

Reserved Full Page

M3 = 1 2 4 8

Reserved

Burst Type

Sequential

Interleaved

M6 M5 M4 00 0 00 1 01 0 01 1 10 0 10 1 11 0 11 1

CAS Latency Reserved 2 3 Reserved

Operating Mode

Defined

Standard Operation

All Other States Reserved

Write Burst Mode Programmed Burst Length

Single Location Access

Micron Technology, Inc., reserves the right to change products or specifications without notice. 2002 Micron Technology, Inc. All rights reserved.
512MB SR , 1GB DR x72, ECC 168-Pin SDRAM UDIMM Mode Register Definition

Table 6 Burst Definition Table

Burst Length

Full Page y

Starting Column Address
n = A11
location 0-y

Order of Accesses Within a Burst Type = Sequential Type = Interleaved
0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2
0-1-2-3 1-0-3-2-3-0-1 3-2-1-0

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Datasheet ID: MT18LSDT12872AG-133C1 648304