M58LT256KST7ZA6E

M58LT256KST7ZA6E Datasheet

M58LT256KST M58LT256KSB

Part	Datasheet
M58LT256KST7ZA6E	M58LT256KST7ZA6E (pdf)

Related Parts	Information
M58LT256KSB7ZA6F TR	M58LT256KSB7ZA6F TR
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M58LT256KSB8ZA6E	M58LT256KSB8ZA6E
M58LT256KST8ZA6E	M58LT256KST8ZA6E
M58LT256KST8ZA6F TR	M58LT256KST8ZA6F TR
M58LT256KSB8ZA6F TR	M58LT256KSB8ZA6F TR
M58LT256KST7ZA6F TR	M58LT256KST7ZA6F TR

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M58LT256KST M58LT256KSB 256 Mbit 16 Mb x 16, multiple bank, multilevel, burst V supply, secure Flash memories - Supply voltage VDD = V to V for program, erase and read VDDQ = V to V for I/O buffers VPP = 9 V for fast program - Synchronous/asynchronous read Synchronous burst read mode 52 MHz Random access 85ns, 70ns Asynchronous page read mode - Synchronous burst read suspend - Programming time 5 µs typical word program time using Buffer Enhanced Factory Program command - Memory organization Multiple bank memory array 16 Mbit banks Parameter blocks top or bottom location - Dual operations Program/erase in one bank while read in others No delay between read and write operations - Block protection All blocks protected at power-up Any combination of blocks can be protected with zero latency Absolute write protection with VPP = VSS - Security Software security features 64 bit unique device number 2112 bit user programmable OTP Cells - CFI common Flash interface - 100 000 program/erase cycles per block TBGA64 ZA 10 x 13 mm - Electronic signature Manufacturer code 20h Top device codes M58LT256KST 885Eh Bottom device codes M58LT256KSB 885Fh - TBGA64 package RoHS compliant July 2010 1/108 Contents Contents M58LT256KST, M58LT256KSB 2/108 Description 8 Signal descriptions 13 Address inputs A0-A23 13 Data input/output DQ0-DQ15 13 Chip Enable E 13 Output Enable G 13 Write Enable W 13 Reset RP 13 Latch Enable L 14 Clock K 14 Wait 14 VDD supply voltage 14 VDDQ supply voltage 14 VPP program supply voltage 14 VSS ground 15 VSSQ ground 15 Bus operations 16 Bus read 16 Bus write 16 Address latch 16 Output disable 16 Standby 17 Reset 17 Command interface 18 Read Array command 19 Read Status Register command 19 Read Electronic Signature command 20 Read CFI Query command 20 Clear Status Register command 21 M58LT256KST, M58LT256KSB Contents Block Erase command 21 The Blank Check command 22 Program command 23 Buffer Program command 24 Buffer Enhanced Factory Program command 25 Setup phase 25 Program and verify phase 26 Exit phase 26 Program/Erase Suspend command 27 Program/Erase Resume command 28 Protection Register Program command 28 Set Configuration Register command 29 Block Protect command 29 Block Unprotect command 29 Status Register 34 Program/Erase Controller status bit SR7 34 Erase suspend status bit SR6 34 Erase/blank check status bit SR5 35 Program status bit SR4 35 VPP status bit SR3 35 Program suspend status bit SR2 36 Block protection status bit SR1 36 Bank write/multiple word program status bit SR0 36 Configuration Register 38 Signal names 10 Bank architecture 12 Bus operations 17 Command codes. 18 Standard commands. 30 Factory commands 31 Electronic signature codes 31 Protection Register locks 33 Status Register bits. 37 X latency settings 38 Configuration Register 41 Burst type definition 42 Dual operations allowed in other banks 48 Dual operations allowed in same bank 48 Dual operation limitations 49 Program/erase times and endurance cycles, 52 Absolute maximum ratings 53 Operating and AC measurement conditions 54 Capacitance 55 DC characteristics - currents 56 DC characteristics - voltages 57 Asynchronous read AC characteristics 60 Synchronous read AC characteristics 64 Write AC characteristics, Write Enable controlled 66 Write AC characteristics, Chip Enable controlled 68 Reset and power-up AC characteristics 69 TBGA64 10 x 13 mm - 8 x 8 active ball array, 1 mm pitch, package mechanical data 71 Ordering information scheme 72 M58LT256KST - parameter bank block addresses 74 M58LT256KST - main bank base addresses 75 M58LT256KST - block addresses in main banks 75 M58LT256KSB - parameter bank block addresses 76 M58LT256KSB - main bank base addresses 77 M58LT256KSB - block addresses in main banks 77 Query structure overview 78 CFI query identification string 79 CFI query system interface information 80 Device geometry definition 81 Primary algorithm-specific extended query table 82 Protection register information 83 Burst read information 84 Bank and erase block region information 85 Bank and erase block region 1 information 85 Bank and erase block region 2 information 87 Command interface states - modify table, next state 98 Command Interface states - modify table, next output state 101 Command interface states - lock table, next state 103 5/108 List of tables M58LT256KST, M58LT256KSB 6/108 M58LT256KST, M58LT256KSB List of figures List of figures Figure Figure Logic diagram 9 TBGA64 package connections top view through package 11 Memory map 12 Protection Register memory map 32 X latency and data output configuration example 43 Wait configuration example 43 AC measurement I/O waveform 54 AC measurement load circuit 55 Asynchronous random access read AC waveforms 58 Asynchronous page read AC waveforms 59 Synchronous burst read AC waveforms 61 Single synchronous read AC waveforms 62 Synchronous burst read suspend AC waveforms. 63 Clock input AC waveform 64 Write AC waveforms, Write Enable controlled 65 Write AC waveforms, Chip Enable controlled 67 Reset and power-up AC waveforms 69 TBGA64 10 x 13 mm - 8 x 8 active ball array, 1 mm pitch, bottom view package outline. 70 Program flowchart and pseudocode 89 Blank check flowchart and pseudocode 90 Buffer program flowchart and pseudocode 91 Program suspend and resume flowchart and pseudocode 92 Block erase flowchart and pseudocode 93 Erase suspend and resume flowchart and pseudocode 94 Protect/unprotect operation flowchart and pseudocode 95 Protection Register program flowchart and pseudocode 96 Buffer enhanced factory program flowchart and pseudocode 97 7/108 M58LT256KST, M58LT256KSB The M58LT256KST/B are 256 Mbit 16 Mbit x 16 non-volatile secure Flash memories. They may be erased electrically at block level and programmed in-system on a word-by-word basis using a V to V VDD supply for the circuitry and a V to V VDDQ supply for the input/output pins. An optional 9 V VPP power supply is provided to speed up factory programming. The devices feature an asymmetrical block architecture. The M58LT256KST/B have an array of 259 blocks, and are divided into 16 Mbit banks. There are 15 banks each containing 16 main blocks of 64 Kwords, and one parameter bank containing 4 parameter blocks of 16 KWords and 15 main blocks of 64 KWords. The multiple bank architecture allows dual operations. While programming or erasing in one bank, read operations are possible in other banks. Only one bank at a time is allowed to be in program or erase mode. It is possible to perform burst reads that cross bank boundaries. The bank architecture is summarized in Table 2, and the memory map is shown in Figure The parameter blocks are located at the top of the memory address space for the M58LT256KST, and at the bottom for the M58LT256KSB. Each block can be erased separately. Erase can be suspended to perform a program or read operation in any other block, and then resumed. Program can be suspended to read data at any memory location except for the one being programmed, and then resumed. Each block can be programmed and erased over 100 000 cycles using the supply voltage VDD. There is a buffer enhanced factory programming command available to speed up programming. Program and erase commands are written to the command interface of the memory. An internal Program/Erase Controller manages the timings necessary for program and erase operations. The end of a program or erase operation can be detected and any error conditions identified in the Status Register. The command set required to control the memory is consistent with JEDEC standards. The device supports synchronous burst read and asynchronous read from all blocks of the memory array. At power-up the device is configured for asynchronous read. In synchronous burst read mode, data is output on each clock cycle at frequencies of up to 52 MHz. The synchronous burst read operation can be suspended and resumed. The device features an automatic standby mode. When the bus is inactive during asynchronous read operations, the device automatically switches to the automatic standby mode. In this condition the power consumption is reduced to the standby value and the outputs are still driven. The M58LT256KST/B features an instant, individual block protection scheme that allows any block to be protected or unprotected with no latency, enabling instant code and data protection. They can be protected individually preventing any accidental programming or erasure. There is an additional hardware protection against program and erase. When VPP VPPLK all blocks are protected against program or erase. All blocks are protected at power-up. 8/108 M58LT256KST, M58LT256KSB The device includes 17 Protection Registers and 2 Protection Register locks, one for the first Protection Register and the other for the 16 OTP one-time-programmable Protection Registers of 128 bits each. The first Protection Register is divided into two segments a 64 bit segment containing a unique device number written by Numonyx, and a 64 bit segment OTP by the user. The user programmable segment can be permanently protected. Figure 4, shows the Protection Register Memory map. The M58LT256KST/B also has a full set of software security features that are not described in this datasheet, but are documented in a dedicated application note. For further information please contact Numonyx. The M58LT256KST/B are offered in a TBGA64, 10 x 13 mm, 1 mm pitch package, and are supplied with all the bits erased set to Figure Logic diagram VDD VDDQ VPP A0-A23 16 DQ0-DQ15 WAIT VSS VSSQ AI13299 9/108 M58LT256KST, M58LT256KSB Table Signal names Signal name Function A0-A23 DQ0-DQ15 Address inputs Data input/outputs, command inputs E G W RP K L WAIT VDD VDDQ VPP VSS VSSQ NC DU Table Ordering information scheme Example: M58LT256KST 8 ZA 6 E Device type M58 Architecture L = multilevel, multiple bank, burst mode Operating voltage T = VDD = V to V, VDDQ = V to V Density 256 = 256 Mbit x 16 Technology K = 65 nm technology, multilevel design Security S = Secure Parameter location T = top boot B = bottom boot Speed 8 = 85ns 7 = 70ns Package ZA = TBGA64, 10 x 13 mm, 1 mm pitch Temperature range 6 = to 85 °C Packing option E = RoHS-compliant package, standard packing F = RoHS-compliant package, tape and reel packing T = tape and reel packing Blank = standard packing Devices are shipped from the factory with the memory content bits erased to For a list of available options speed, package, etc. or for further information on any aspect of this device, please contact the Numonyx sales office nearest to you. 72/108 M58LT256KST, M58LT256KSB Appendix A Block address tables Block address tables The following set of equations can be used to calculate a complete set of block addresses using the information contained in Tables 29 to To calculate the block base address from the block number: First it is necessary to calculate the bank number and the block number offset. This can be achieved using the following formulas: Bank_Number = Block_Number − 3 / 16 Block_Number_Offset = Block_Number − 3 − Bank_Number x 16 If Bank_Number = 0, the block base address can be directly read from Tables 29 and 32 parameter bank block addresses in the block number offset row. Otherwise: Block_Base_Address = Bank_Base_Address + Block_Base_Address_Offset To calculate the bank number and the block number from the block base address: If the address is in the range of the parameter bank, the bank number is 0 and the block number can be directly read from tables 29 and 32 parameter bank block addresses , in the row that corresponds to the address given. Otherwise, the block number can be calculated using the formulas below: For the top configuration M58LT256KST Block_Number = NOT address / 216 + 3 For the bottom configuration M58LT256KSB Block_Number = address / 216 + 3 For both configurations the bank number and the block number offset can be calculated using the following formulas: Bank_Number = Block_Number − 3 / 16 Block_Number_Offset = Block_Number − 3 − Bank_Number x 16 73/108 Block address tables M58LT256KST, M58LT256KSB Table M58LT256KST - parameter bank block addresses Block number Size KWords Address range FF8000-FFBFFF FF4000-FF7FFF FF0000-FF3FFF FE0000-FEFFFF FD0000-FDFFFF FC0000-FCFFFF FB0000-FBFFFF FA0000-FAFFFF F90000-F9FFFF F80000-F8FFFF F70000-F7FFFF F60000-F6FFFF F50000-F5FFFF F40000-F4FFFF

PDF Datasheet Preview

M58LT256KST M58LT256KSB
256 Mbit 16 Mb x 16, multiple bank, multilevel, burst V supply, secure Flash memories
- Supply voltage VDD = V to V for program, erase and read VDDQ = V to V for I/O buffers VPP = 9 V for fast program
- Synchronous/asynchronous read Synchronous burst read mode 52 MHz Random access 85ns, 70ns Asynchronous page read mode
- Synchronous burst read suspend - Programming time
5 µs typical word program time using Buffer Enhanced Factory Program command
- Memory organization Multiple bank memory array 16 Mbit banks Parameter blocks top or bottom location
- Dual operations Program/erase in one bank while read in others No delay between read and write operations
- Block protection All blocks protected at power-up Any combination of blocks can be protected with zero latency Absolute write protection with VPP = VSS
- Security Software security features 64 bit unique device number 2112 bit user programmable OTP Cells
- CFI common Flash interface - 100 000 program/erase cycles per block

TBGA64 ZA 10 x 13 mm
- Electronic signature Manufacturer code 20h Top device codes M58LT256KST 885Eh Bottom device codes M58LT256KSB 885Fh
- TBGA64 package RoHS compliant

July 2010
1/108

Contents

Contents

M58LT256KST, M58LT256KSB
2/108

Description 8

Signal descriptions 13

Address inputs A0-A23 13 Data input/output DQ0-DQ15 13 Chip Enable E 13 Output Enable G 13 Write Enable W 13 Reset RP 13 Latch Enable L 14 Clock K 14 Wait 14 VDD supply voltage 14 VDDQ supply voltage 14 VPP program supply voltage 14 VSS ground 15 VSSQ ground 15

Bus operations 16

Bus read 16 Bus write 16 Address latch 16 Output disable 16 Standby 17 Reset 17

Command interface 18

Read Array command 19 Read Status Register command 19 Read Electronic Signature command 20 Read CFI Query command 20 Clear Status Register command 21

M58LT256KST, M58LT256KSB

Contents

Block Erase command 21 The Blank Check command 22 Program command 23 Buffer Program command 24 Buffer Enhanced Factory Program command 25

Setup phase 25 Program and verify phase 26 Exit phase 26

Program/Erase Suspend command 27 Program/Erase Resume command 28 Protection Register Program command 28 Set Configuration Register command 29 Block Protect command 29 Block Unprotect command 29

Status Register 34

Program/Erase Controller status bit SR7 34

Erase suspend status bit SR6 34

Erase/blank check status bit SR5 35

Program status bit SR4 35

VPP status bit SR3 35 Program suspend status bit SR2 36

Block protection status bit SR1 36

Bank write/multiple word program status bit SR0 36

Configuration Register 38
Signal names 10 Bank architecture 12 Bus operations 17 Command codes. 18 Standard commands. 30 Factory commands 31 Electronic signature codes 31 Protection Register locks 33 Status Register bits. 37 X latency settings 38 Configuration Register 41 Burst type definition 42 Dual operations allowed in other banks 48 Dual operations allowed in same bank 48 Dual operation limitations 49 Program/erase times and endurance cycles, 52 Absolute maximum ratings 53 Operating and AC measurement conditions 54 Capacitance 55 DC characteristics - currents 56 DC characteristics - voltages 57 Asynchronous read AC characteristics 60 Synchronous read AC characteristics 64 Write AC characteristics, Write Enable controlled 66 Write AC characteristics, Chip Enable controlled 68 Reset and power-up AC characteristics 69 TBGA64 10 x 13 mm - 8 x 8 active ball array, 1 mm pitch, package mechanical data 71 Ordering information scheme 72 M58LT256KST - parameter bank block addresses 74 M58LT256KST - main bank base addresses 75 M58LT256KST - block addresses in main banks 75 M58LT256KSB - parameter bank block addresses 76 M58LT256KSB - main bank base addresses 77 M58LT256KSB - block addresses in main banks 77 Query structure overview 78 CFI query identification string 79 CFI query system interface information 80 Device geometry definition 81 Primary algorithm-specific extended query table 82 Protection register information 83 Burst read information 84 Bank and erase block region information 85 Bank and erase block region 1 information 85 Bank and erase block region 2 information 87 Command interface states - modify table, next state 98 Command Interface states - modify table, next output state 101 Command interface states - lock table, next state 103
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List of tables

M58LT256KST, M58LT256KSB
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M58LT256KST, M58LT256KSB

List of figures

List of figures

Figure

Figure

Logic diagram 9 TBGA64 package connections top view through package 11 Memory map 12 Protection Register memory map 32 X latency and data output configuration example 43 Wait configuration example 43 AC measurement I/O waveform 54 AC measurement load circuit 55 Asynchronous random access read AC waveforms 58 Asynchronous page read AC waveforms 59 Synchronous burst read AC waveforms 61 Single synchronous read AC waveforms 62 Synchronous burst read suspend AC waveforms. 63 Clock input AC waveform 64 Write AC waveforms, Write Enable controlled 65 Write AC waveforms, Chip Enable controlled 67 Reset and power-up AC waveforms 69 TBGA64 10 x 13 mm - 8 x 8 active ball array, 1 mm pitch, bottom view package outline. 70 Program flowchart and pseudocode 89 Blank check flowchart and pseudocode 90 Buffer program flowchart and pseudocode 91 Program suspend and resume flowchart and pseudocode 92 Block erase flowchart and pseudocode 93 Erase suspend and resume flowchart and pseudocode 94 Protect/unprotect operation flowchart and pseudocode 95 Protection Register program flowchart and pseudocode 96 Buffer enhanced factory program flowchart and pseudocode 97
7/108

M58LT256KST, M58LT256KSB

The M58LT256KST/B are 256 Mbit 16 Mbit x 16 non-volatile secure Flash memories. They may be erased electrically at block level and programmed in-system on a word-by-word basis using a V to V VDD supply for the circuitry and a V to V VDDQ supply for the input/output pins. An optional 9 V VPP power supply is provided to speed up factory programming.

The devices feature an asymmetrical block architecture. The M58LT256KST/B have an array of 259 blocks, and are divided into 16 Mbit banks. There are 15 banks each containing 16 main blocks of 64 Kwords, and one parameter bank containing 4 parameter blocks of 16 KWords and 15 main blocks of 64 KWords.

The multiple bank architecture allows dual operations. While programming or erasing in one bank, read operations are possible in other banks. Only one bank at a time is allowed to be in program or erase mode. It is possible to perform burst reads that cross bank boundaries. The bank architecture is summarized in Table 2, and the memory map is shown in Figure The parameter blocks are located at the top of the memory address space for the M58LT256KST, and at the bottom for the M58LT256KSB.

Each block can be erased separately. Erase can be suspended to perform a program or read operation in any other block, and then resumed. Program can be suspended to read data at any memory location except for the one being programmed, and then resumed. Each block can be programmed and erased over 100 000 cycles using the supply voltage VDD. There is a buffer enhanced factory programming command available to speed up programming.

Program and erase commands are written to the command interface of the memory. An internal Program/Erase Controller manages the timings necessary for program and erase operations. The end of a program or erase operation can be detected and any error conditions identified in the Status Register. The command set required to control the memory is consistent with JEDEC standards.

The device supports synchronous burst read and asynchronous read from all blocks of the memory array. At power-up the device is configured for asynchronous read. In synchronous burst read mode, data is output on each clock cycle at frequencies of up to 52 MHz. The synchronous burst read operation can be suspended and resumed.

The device features an automatic standby mode. When the bus is inactive during asynchronous read operations, the device automatically switches to the automatic standby mode. In this condition the power consumption is reduced to the standby value and the outputs are still driven.

The M58LT256KST/B features an instant, individual block protection scheme that allows any block to be protected or unprotected with no latency, enabling instant code and data protection. They can be protected individually preventing any accidental programming or erasure. There is an additional hardware protection against program and erase. When VPP VPPLK all blocks are protected against program or erase. All blocks are protected at power-up.
8/108

M58LT256KST, M58LT256KSB

The device includes 17 Protection Registers and 2 Protection Register locks, one for the first Protection Register and the other for the 16 OTP one-time-programmable Protection Registers of 128 bits each. The first Protection Register is divided into two segments a 64 bit segment containing a unique device number written by Numonyx, and a 64 bit segment OTP by the user. The user programmable segment can be permanently protected. Figure 4, shows the Protection Register Memory map.

The M58LT256KST/B also has a full set of software security features that are not described in this datasheet, but are documented in a dedicated application note. For further information please contact Numonyx.

The M58LT256KST/B are offered in a TBGA64, 10 x 13 mm, 1 mm pitch package, and are supplied with all the bits erased set to

Figure Logic diagram

VDD VDDQ VPP

A0-A23
16 DQ0-DQ15

WAIT

VSS VSSQ

AI13299
9/108

M58LT256KST, M58LT256KSB

Table Signal names

Signal name

Function

A0-A23 DQ0-DQ15

Address inputs Data input/outputs, command inputs

E G W RP K L WAIT VDD VDDQ VPP VSS VSSQ NC DU
Table Ordering information scheme

Example:

M58LT256KST
8 ZA 6 E

Device type M58 Architecture L = multilevel, multiple bank, burst mode Operating voltage T = VDD = V to V, VDDQ = V to V Density 256 = 256 Mbit x 16 Technology K = 65 nm technology, multilevel design Security S = Secure Parameter location T = top boot B = bottom boot Speed 8 = 85ns 7 = 70ns Package ZA = TBGA64, 10 x 13 mm, 1 mm pitch Temperature range 6 = to 85 °C Packing option E = RoHS-compliant package, standard packing F = RoHS-compliant package, tape and reel packing T = tape and reel packing Blank = standard packing

Devices are shipped from the factory with the memory content bits erased to

For a list of available options speed, package, etc. or for further information on any aspect of this device, please contact the Numonyx sales office nearest to you.
72/108

M58LT256KST, M58LT256KSB

Appendix A Block address tables

Block address tables

The following set of equations can be used to calculate a complete set of block addresses using the information contained in Tables 29 to

To calculate the block base address from the block number:

First it is necessary to calculate the bank number and the block number offset. This can be achieved using the following formulas:

Bank_Number = Block_Number − 3 / 16 Block_Number_Offset = Block_Number − 3 − Bank_Number x 16

If Bank_Number = 0, the block base address can be directly read from Tables 29 and 32 parameter bank block addresses in the block number offset row. Otherwise:

Block_Base_Address = Bank_Base_Address + Block_Base_Address_Offset

To calculate the bank number and the block number from the block base address:

If the address is in the range of the parameter bank, the bank number is 0 and the block number can be directly read from tables 29 and 32 parameter bank block addresses , in the row that corresponds to the address given. Otherwise, the block number can be calculated using the formulas below:

For the top configuration M58LT256KST Block_Number = NOT address / 216 + 3

For the bottom configuration M58LT256KSB Block_Number = address / 216 + 3

For both configurations the bank number and the block number offset can be calculated using the following formulas:

Bank_Number = Block_Number − 3 / 16 Block_Number_Offset = Block_Number − 3 − Bank_Number x 16
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Block address tables

M58LT256KST, M58LT256KSB

Table M58LT256KST - parameter bank block addresses

Block number

Size KWords

Address range

FF8000-FFBFFF

FF4000-FF7FFF FF0000-FF3FFF

FE0000-FEFFFF

FD0000-FDFFFF

FC0000-FCFFFF

FB0000-FBFFFF FA0000-FAFFFF

F90000-F9FFFF

F80000-F8FFFF

F70000-F7FFFF F60000-F6FFFF

F50000-F5FFFF

F40000-F4FFFF

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Datasheet ID: M58LT256KST7ZA6E 648301