M58LR128KT85ZB6E

M58LR128KT85ZB6E Datasheet

M58LR128KT M58LR128KB M58LR256KT M58LR256KB

Part	Datasheet
M58LR128KT85ZB6E	M58LR128KT85ZB6E (pdf)

Related Parts	Information
M58LR128KT85ZB5E	M58LR128KT85ZB5E
M58LR128KB85ZB5E	M58LR128KB85ZB5E
M58LR256KB70ZQ5F TR	M58LR256KB70ZQ5F TR
M58LR128KB70ZB5E	M58LR128KB70ZB5E
M58LR128KB85ZB6E	M58LR128KB85ZB6E
M58LR256KT70ZQ5F TR	M58LR256KT70ZQ5F TR
M58LR256KT70ZC5F TR	M58LR256KT70ZC5F TR
M58LR128KB85ZB5F TR	M58LR128KB85ZB5F TR
M58LR128KB85ZB6F TR	M58LR128KB85ZB6F TR
M58LR256KB70ZQ5W TR	M58LR256KB70ZQ5W TR
M58LR128KB70ZB5F TR	M58LR128KB70ZB5F TR
M58LR128KT85ZB5F TR	M58LR128KT85ZB5F TR
M58LR256KB70ZC5F TR	M58LR256KB70ZC5F TR
M58LR256KT70ZQ5E	M58LR256KT70ZQ5E
M58LR256KB70ZQ5Z	M58LR256KB70ZQ5Z
M58LR256KB70ZC5W TR	M58LR256KB70ZC5W TR
M58LR256KB70ZQ5E	M58LR256KB70ZQ5E
M58LR128KT85ZB6F TR	M58LR128KT85ZB6F TR
M58LR256KB70ZC5Z	M58LR256KB70ZC5Z

PDF Datasheet Preview
M58LR128KT M58LR128KB M58LR256KT M58LR256KB 128 or 256 Mbit x16, multiple bank, multilevel interface, burst V supply flash memories - Supply voltage VDD = V to V for program, erase and read VDDQ = V to V for I/O buffers VPP = 9 V for fast program - Synchronous/asynchronous read Synchronous burst read mode 54 MHz, 66 MHz Asynchronous page read mode Random access 70 ns, 85 ns - Synchronous burst read suspend - Programming time us typical word program time using Buffer Enhanced Factory Program command - Memory organization Multiple bank memory array 8 Mbit banks for the M58LR128KT/B 16 Mbit banks for the M58LR256KT/B Parameter blocks top or bottom location - Dual operations Program/erase in one bank while read in others No delay between read and write operations - Block locking All blocks locked at power-up Any combination of blocks can be locked with zero latency WP for block lock-down Absolute write protection with VPP = VSS FBGA VFBGA56 ZB x 9 mm VFBGA79 ZC 9 x 11 mm TFBGA88 ZQ 8 x 10 mm - Security 64 bit unique device number 2112 bit user programmable OTP cells - Common flash interface CFI - 100,000 program/erase cycles per block - Electronic signature Manufacturer code 20h Top device codes: M58LR128KT 88C4h M58LR256KT 880Dh Bottom device codes M58LR128KB 88C5h M58LR256KB 880Eh - The M58LR128KT/B is available in the ECOPACK-compliant VFBGA56 package. - The M58LR256KT/B is available in the ECOPACK-compliant VFBGA79 and TFBGA88 packages. October 2008 1/120 Contents Contents M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB 2/120 Description 9 Signal descriptions 18 Address inputs A0-Amax 18 Data inputs/outputs DQ0-DQ15 18 Chip Enable E 18 Output Enable G 18 Write Enable W 18 Write Protect WP 18 Reset RP 19 Latch Enable L 19 Clock K 19 Wait 19 VDD supply voltage 19 VDDQ supply voltage 19 VPP program supply voltage 20 VSS ground 20 VSSQ ground 20 Bus operations 21 Bus read 21 Bus write 21 Address Latch 21 Output disable 21 Standby 22 Reset 22 Command interface 23 Read Array command 24 Read Status Register command 24 Read Electronic Signature command 25 Read CFI Query command 25 M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB Contents Clear Status Register command 26 Block Erase command 26 Blank Check command 27 Program command 28 Buffer Program command 28 Buffer Enhanced Factory Program command 29 Setup phase 30 Program and verify phase 30 Exit phase 31 Program/Erase Suspend command 31 Program/Erase Resume command 32 Protection Register Program command 32 Set Configuration Register command 33 Block Lock command 33 Block Unlock command 34 Block Lock-Down command 34 Status Register 39 Program/Erase Controller status bit SR7 39 Erase suspend status bit SR6 39 Erase/blank check status bit SR5 40 Program status bit SR4 40 VPP status bit SR3 40 Program suspend status bit SR2 41 Block protection status bit SR1 41 Bank write/multiple word program status bit SR0 41 Signal names 12 M58LR128KT/B bank architecture 16 M58LR256KT/B bank architecture 17 Bus operations 22 Command codes. 23 Standard commands. 35 Factory commands 36 Electronic signature codes 36 Protection Register locks 38 Status Register bits. 42 X latency settings 43 Configuration Register 46 Burst type definition 47 Dual operations allowed in other banks 54 Dual operations allowed in same bank 55 Dual operation limitations 55 Lock status 58 Program/erase times and endurance cycles 59 Absolute maximum ratings 61 Operating and AC measurement conditions 62 Capacitance 63 DC characteristics - currents 64 DC characteristics - voltages 65 Asynchronous read AC characteristics 68 Synchronous read AC characteristics 72 Write AC characteristics, Write Enable controlled 74 Write AC characteristics, Chip Enable controlled 76 Reset and power-up AC characteristics 77 VFBGA56 x 9 mm - 8 x 7 ball array, mm pitch, package mechanical data. 79 TFBGA88 8 x 10 mm - 8 x 10 ball array, mm pitch, package mechanical data 80 VFBGA79 9x11mm - mm pitch, package mechanical data 81 Ordering information scheme 82 M58LR128KT - Parameter bank block addresses 85 M58LR128KT - main bank base addresses 85 M58LR128KT - block addresses in main banks 86 M58LR256KT - parameter bank block addresses 86 M58LR256KT - main bank base addresses 87 M58LR256KT - block addresses in main banks 87 M58LR128KB - parameter bank block addresses 88 M58LR128KB - main bank base addresses 88 M58LR128KB - block addresses in main banks 89 M58LR256KB - parameter bank block addresses 89 M58LR256KB - main bank base addresses 90 M58LR256KB - block addresses in main banks 90 Query structure overview 91 CFI query identification string 92 CFI query system interface information 93 Device geometry definition 94 6/120 M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB List of tables Table 7/120 List of figures List of figures M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB Figure Figure Logic diagram 11 VFBGA56 package connections top view through package 13 TFBGA88 connections top view through package 14 M58LR128KT/B memory map 16 M58LR256KT/B memory map 17 Protection Register memory map 37 X latency and data output configuration example 49 Wait configuration example 50 AC measurement I/O waveform 62 AC measurement load circuit 63 Asynchronous random access read AC waveforms 66 Asynchronous page read AC waveforms 67 Synchronous burst read AC waveforms 69 Single synchronous read AC waveforms 70 Synchronous burst read suspend AC waveforms. 71 Clock input AC waveform 72 Write AC waveforms, Write Enable controlled 73 Write AC waveforms, Chip Enable controlled 75 Reset and power-up AC waveforms 77 VFBGA56 x 9 mm - 8 x 7 active ball array, mm pitch, bottom view package outline. 78 TFBGA88 8 x 10 mm - 8 x 10 ball array, mm pitch, bottom view package outline 79 Drawing is not to scale.. 79 VFBGA79 9x11mm - pitch -package outline 81 Program flowchart and pseudocode 101 Blank check flowchart and pseudocode 102 Buffer program flowchart and pseudocode 103 Program suspend and resume flowchart and pseudocode 104 Block erase flowchart and pseudocode 105 Erase suspend and resume flowchart and pseudocode 106 Locking operations flowchart and pseudocode. 107 Protection Register program flowchart and pseudocode 108 Buffer enhanced factory program flowchart and pseudocode 109 8/120 M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB The M58LR128KT/B and M58LR256KT/B are 128 Mbit 8 Mbit x16 and 256 Mbit 16 Mbit x 16 non-volatile Flash memories, respectively. They can be erased electrically at block level and programmed in-system on a word-by-word basis using a V to V VDD supply for the circuitry and a V to V VDDQ supply for the input/output pins. An optional 9 V VPP power supply is provided to accelerate factory programming. The devices feature an asymmetrical block architecture z The M58LR128KT/B have an array of 131 blocks, and are divided into 8 Mbit banks. There are 15 banks each containing 8 main blocks of 64 Kwords, and one parameter bank containing 4 parameter blocks of 16 Kwords and 7 main blocks of 64 Kwords. z The M58LR256KT/B have an array of 259 blocks, and are divided into 16 Mbit banks. There are 15 banks each containing 16 main blocks of 64 Kwords, and one parameter bank containing 4 parameter blocks of 16 Kwords and 15 main blocks of 64 Kwords. The multiple bank architecture allows dual operations. While programming or erasing in one bank, read operations are possible in other banks. Only one bank at a time is allowed to be in program or erase mode. It is possible to perform burst reads that cross bank boundaries. The bank architecture is summarized in Table 2, and the memory map is shown in Figure The parameter blocks are located at the top of the memory address space for the M58LR128KT and M58LR256KT, and at the bottom for the M58LR128KB and M58LR256KB. Each block can be erased separately. Erase can be suspended to perform a program or read operation in any other block, and then resumed. Program can be suspended to read data at any memory location except for the one being programmed, and then resumed. Each block can be programmed and erased over 100 000 cycles using the supply voltage VDD. There is a buffer enhanced factory programming command available to speed up programming. Program and erase commands are written to the command interface of the memory. An internal Program/Erase Controller manages the timings necessary for program and erase operations. The end of a program or erase operation can be detected and any error conditions identified in the Status Register. The command set required to control the memory is consistent with JEDEC standards. The device supports synchronous burst read and asynchronous read from all blocks of the memory array at power-up the device is configured for asynchronous read. In synchronous burst read mode, data is output on each clock cycle at frequencies of up to 66 MHz. The synchronous burst read operation can be suspended and resumed. The device features an automatic standby mode. When the bus is inactive during asynchronous read operations, the device automatically switches to automatic standby mode. In this condition the power consumption is reduced to the standby value and the outputs are still driven. The M58LRxxxKT/B features an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency, enabling instant code and data protection. All blocks have three levels of protection. They can be locked and locked-down individually preventing any accidental programming or erasure. There is an additional hardware protection against program and erase. When VPP VPPLK all blocks are protected against program or erase. All blocks are locked at power-up. 9/120 M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB The device includes 17 Protection Registers and 2 Protection Register locks, one for the first Protection Register and the other for the 16 one-time-programmable OTP Protection Registers of 128 bits each. The first Protection Register is divided into two segments a 64 bit segment containing a unique device number written by Numonyx, and a 64 bit segment OTP by the user. The user programmable segment can be permanently protected. Figure 6, shows the Protection Register memory map. The M58LR128KT/B is offered in a VFBGA56 x 9 mm, mm package, and the M58LR256KT/B is offered in a VFBGA79 9 x 11mm, mm package and TFGBA88 8 x 10mm, mm package. All devices are supplied with all the bits erased set to 10/120 M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB Figure Logic diagram A0-Amax 1 W E G RP WP L K VDD VDDQ VPP 16 DQ0-DQ15 M58LR128KT M58LR128KB M58LR256KT M58LR256KB WAIT VSS VSSQ AI14011 Amax is equal to A22 in the M58LR128KT/B and, to A23 in the M58LR256KT/B. 11/120 Table Ordering information scheme Example: M58LR128KT 70 ZB 5 E Device type M58 Architecture L = multilevel, multiple bank, burst mode Operating voltage R = VDD = V to V, VDDQ = V to V Density 128 = 128 Mbit x16 256 = 256 Mbit x16 Technology K = 65 nm technology Parameter location T = top boot B = bottom boot Speed 70 = 70 ns 85 = 85 ns Package ZB = VFBGA56, x 9 mm, mm pitch 1 ZC = VFBGA79, 9 x 11 mm, mm pitch ZQ = TFBGA88, 8 x 10mm, mm pitch Temperature range 5 = to 85 °C Packing option E = package, standard packing F = package, tape and reel packing The M58LR128KT/B are available in the ZB package, while the M58LR256KT/B are available M58LR256KT/B are available in the ZC and ZQ package. Devices are shipped from the factory with the memory content bits erased to 82/120 M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB Part numbering For a list of available options speed, package, etc. or for further information on any aspect of this device, please contact the Numonyx sales office nearest to you. 83/120 Block address tables M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB Appendix A Block address tables The following set of equations can be used to calculate a complete set of block addresses for the M58LRxxxKT/B using the information contained in Tables 36 to To calculate the block base address from the block number: First it is necessary to calculate the bank number and the block number offset. This can be achieved using the following formulas: Bank_Number = Block_Number − 3 / 8 Block_Number_Offset = Block_Number − 3 − Bank_Number x 8 , If Bank_Number= 0, the block base address can be directly read from Tables 36 and 42 parameter bank block addresses in the address range column, in the row that corresponds to the given block number. Otherwise Block_Base_Address = Bank_Base_Address + Block_Base_Address_Offset To calculate the bank number and the block number from the block base address: If the address is in the range of the parameter bank, the Bank Number is 0 and the Block Number can be directly read from Tables 36 and 42 parameter bank Block Addresses , in the Block Number column, in the row that corresponds to the address given. Otherwise, the Block Number can be calculated using the formulas below: For the top configuration M58LR256KT and M58LR128KT Block_Number = NOT address / 216 + 3 For the bottom configuration M58LR256KB and M58LR128KB Block_Number = address / 216 + 3 For both configurations the Bank Number and the Block Number Offset can be calculated using the following formulas: Bank_Number = Block_Number − 3 / 8 Block_Number_Offset = Block_Number − 3 − Bank_Number x 8 84/120 M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB Block address tables Table M58LR128KT - Parameter bank block addresses Block number bottom view package outline, Table 23 VFBGA79 9x11mm - pitch -package outline, and amended Table 32 Ordering information scheme to provide the ZB package information, which is available for the M58LR128KT/B devices. Add 79B vfBGA 9x11 package for 256Mbit. Add 88b package 8x10. Change from T=-25°C to T=-30°C Change Terase for Boot sectors 0.4s to 0.6s Change the package reference from ZA to ZQ. 120/120 M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB Please Read Carefully INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. Numonyx may make changes to specifications and product descriptions at any time, without notice. Numonyx, B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Numonyx reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by visiting Numonyx's website at Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright 11/5/7, Numonyx, B.V., All Rights Reserved. 120/120

PDF Datasheet Preview

M58LR128KT M58LR128KB M58LR256KT M58LR256KB
128 or 256 Mbit x16, multiple bank, multilevel interface, burst V supply flash memories
- Supply voltage VDD = V to V for program, erase and read VDDQ = V to V for I/O buffers VPP = 9 V for fast program
- Synchronous/asynchronous read Synchronous burst read mode 54 MHz, 66 MHz Asynchronous page read mode Random access 70 ns, 85 ns
- Synchronous burst read suspend - Programming time
us typical word program time using Buffer Enhanced Factory Program command
- Memory organization Multiple bank memory array 8 Mbit banks for the M58LR128KT/B 16 Mbit banks for the M58LR256KT/B Parameter blocks top or bottom location
- Dual operations Program/erase in one bank while read in others No delay between read and write operations
- Block locking All blocks locked at power-up Any combination of blocks can be locked with zero latency WP for block lock-down Absolute write protection with VPP = VSS

FBGA

VFBGA56 ZB x 9 mm VFBGA79 ZC 9 x 11 mm TFBGA88 ZQ 8 x 10 mm
- Security 64 bit unique device number 2112 bit user programmable OTP cells
- Common flash interface CFI - 100,000 program/erase cycles per block - Electronic signature

Manufacturer code 20h Top device codes:

M58LR128KT 88C4h M58LR256KT 880Dh Bottom device codes M58LR128KB 88C5h M58LR256KB 880Eh - The M58LR128KT/B is available in the ECOPACK-compliant VFBGA56 package. - The M58LR256KT/B is available in the ECOPACK-compliant VFBGA79 and TFBGA88 packages.

October 2008
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Contents

Contents

M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB
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Description 9

Signal descriptions 18

Address inputs A0-Amax 18 Data inputs/outputs DQ0-DQ15 18 Chip Enable E 18 Output Enable G 18 Write Enable W 18 Write Protect WP 18 Reset RP 19 Latch Enable L 19 Clock K 19 Wait 19 VDD supply voltage 19 VDDQ supply voltage 19 VPP program supply voltage 20 VSS ground 20 VSSQ ground 20

Bus operations 21

Bus read 21 Bus write 21 Address Latch 21 Output disable 21 Standby 22 Reset 22

Command interface 23

Read Array command 24 Read Status Register command 24 Read Electronic Signature command 25 Read CFI Query command 25

M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB

Contents

Clear Status Register command 26 Block Erase command 26 Blank Check command 27 Program command 28 Buffer Program command 28 Buffer Enhanced Factory Program command 29

Setup phase 30 Program and verify phase 30 Exit phase 31

Program/Erase Suspend command 31 Program/Erase Resume command 32 Protection Register Program command 32 Set Configuration Register command 33 Block Lock command 33 Block Unlock command 34 Block Lock-Down command 34

Status Register 39

Program/Erase Controller status bit SR7 39

Erase suspend status bit SR6 39

Erase/blank check status bit SR5 40

Program status bit SR4 40

VPP status bit SR3 40 Program suspend status bit SR2 41

Block protection status bit SR1 41

Bank write/multiple word program status bit SR0 41
Signal names 12 M58LR128KT/B bank architecture 16 M58LR256KT/B bank architecture 17 Bus operations 22 Command codes. 23 Standard commands. 35 Factory commands 36 Electronic signature codes 36 Protection Register locks 38 Status Register bits. 42 X latency settings 43 Configuration Register 46 Burst type definition 47 Dual operations allowed in other banks 54 Dual operations allowed in same bank 55 Dual operation limitations 55 Lock status 58 Program/erase times and endurance cycles 59 Absolute maximum ratings 61 Operating and AC measurement conditions 62 Capacitance 63 DC characteristics - currents 64 DC characteristics - voltages 65 Asynchronous read AC characteristics 68 Synchronous read AC characteristics 72 Write AC characteristics, Write Enable controlled 74 Write AC characteristics, Chip Enable controlled 76 Reset and power-up AC characteristics 77 VFBGA56 x 9 mm - 8 x 7 ball array, mm pitch, package mechanical data. 79 TFBGA88 8 x 10 mm - 8 x 10 ball array, mm pitch, package mechanical data 80 VFBGA79 9x11mm - mm pitch, package mechanical data 81 Ordering information scheme 82 M58LR128KT - Parameter bank block addresses 85 M58LR128KT - main bank base addresses 85 M58LR128KT - block addresses in main banks 86 M58LR256KT - parameter bank block addresses 86 M58LR256KT - main bank base addresses 87 M58LR256KT - block addresses in main banks 87 M58LR128KB - parameter bank block addresses 88 M58LR128KB - main bank base addresses 88 M58LR128KB - block addresses in main banks 89 M58LR256KB - parameter bank block addresses 89 M58LR256KB - main bank base addresses 90 M58LR256KB - block addresses in main banks 90 Query structure overview 91 CFI query identification string 92 CFI query system interface information 93 Device geometry definition 94
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List of tables

Table
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List of figures

List of figures

M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB

Figure

Figure

Logic diagram 11 VFBGA56 package connections top view through package 13 TFBGA88 connections top view through package 14 M58LR128KT/B memory map 16 M58LR256KT/B memory map 17 Protection Register memory map 37 X latency and data output configuration example 49 Wait configuration example 50 AC measurement I/O waveform 62 AC measurement load circuit 63 Asynchronous random access read AC waveforms 66 Asynchronous page read AC waveforms 67 Synchronous burst read AC waveforms 69 Single synchronous read AC waveforms 70 Synchronous burst read suspend AC waveforms. 71 Clock input AC waveform 72 Write AC waveforms, Write Enable controlled 73 Write AC waveforms, Chip Enable controlled 75 Reset and power-up AC waveforms 77 VFBGA56 x 9 mm - 8 x 7 active ball array, mm pitch, bottom view package outline. 78 TFBGA88 8 x 10 mm - 8 x 10 ball array, mm pitch, bottom view package outline 79 Drawing is not to scale.. 79 VFBGA79 9x11mm - pitch -package outline 81 Program flowchart and pseudocode 101 Blank check flowchart and pseudocode 102 Buffer program flowchart and pseudocode 103 Program suspend and resume flowchart and pseudocode 104 Block erase flowchart and pseudocode 105 Erase suspend and resume flowchart and pseudocode 106 Locking operations flowchart and pseudocode. 107 Protection Register program flowchart and pseudocode 108 Buffer enhanced factory program flowchart and pseudocode 109
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M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB

The M58LR128KT/B and M58LR256KT/B are 128 Mbit 8 Mbit x16 and 256 Mbit 16 Mbit x 16 non-volatile Flash memories, respectively. They can be erased electrically at block level and programmed in-system on a word-by-word basis using a V to V VDD supply for the circuitry and a V to V VDDQ supply for the input/output pins. An optional 9 V VPP power supply is provided to accelerate factory programming.

The devices feature an asymmetrical block architecture z The M58LR128KT/B have an array of 131 blocks, and are divided into 8 Mbit banks.

There are 15 banks each containing 8 main blocks of 64 Kwords, and one parameter bank containing 4 parameter blocks of 16 Kwords and 7 main blocks of 64 Kwords. z The M58LR256KT/B have an array of 259 blocks, and are divided into 16 Mbit banks. There are 15 banks each containing 16 main blocks of 64 Kwords, and one parameter bank containing 4 parameter blocks of 16 Kwords and 15 main blocks of 64 Kwords.

The multiple bank architecture allows dual operations. While programming or erasing in one bank, read operations are possible in other banks. Only one bank at a time is allowed to be in program or erase mode. It is possible to perform burst reads that cross bank boundaries. The bank architecture is summarized in Table 2, and the memory map is shown in Figure The parameter blocks are located at the top of the memory address space for the M58LR128KT and M58LR256KT, and at the bottom for the M58LR128KB and M58LR256KB.

Each block can be erased separately. Erase can be suspended to perform a program or read operation in any other block, and then resumed. Program can be suspended to read data at any memory location except for the one being programmed, and then resumed. Each block can be programmed and erased over 100 000 cycles using the supply voltage VDD. There is a buffer enhanced factory programming command available to speed up programming.

Program and erase commands are written to the command interface of the memory. An internal Program/Erase Controller manages the timings necessary for program and erase operations. The end of a program or erase operation can be detected and any error conditions identified in the Status Register. The command set required to control the memory is consistent with JEDEC standards.

The device supports synchronous burst read and asynchronous read from all blocks of the memory array at power-up the device is configured for asynchronous read. In synchronous burst read mode, data is output on each clock cycle at frequencies of up to 66 MHz. The synchronous burst read operation can be suspended and resumed.

The device features an automatic standby mode. When the bus is inactive during asynchronous read operations, the device automatically switches to automatic standby mode. In this condition the power consumption is reduced to the standby value and the outputs are still driven.

The M58LRxxxKT/B features an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency, enabling instant code and data protection. All blocks have three levels of protection. They can be locked and locked-down individually preventing any accidental programming or erasure. There is an additional hardware protection against program and erase. When VPP VPPLK all blocks are protected against program or erase. All blocks are locked at power-up.
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M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB

The device includes 17 Protection Registers and 2 Protection Register locks, one for the first Protection Register and the other for the 16 one-time-programmable OTP Protection Registers of 128 bits each. The first Protection Register is divided into two segments a 64 bit segment containing a unique device number written by Numonyx, and a 64 bit segment OTP by the user. The user programmable segment can be permanently protected. Figure 6, shows the Protection Register memory map.

The M58LR128KT/B is offered in a VFBGA56 x 9 mm, mm package, and the M58LR256KT/B is offered in a VFBGA79 9 x 11mm, mm package and TFGBA88 8 x 10mm, mm package.

All devices are supplied with all the bits erased set to
10/120

M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB

Figure Logic diagram

A0-Amax 1 W E G RP

WP L K

VDD VDDQ VPP
16 DQ0-DQ15

M58LR128KT M58LR128KB M58LR256KT M58LR256KB

WAIT

VSS VSSQ

AI14011

Amax is equal to A22 in the M58LR128KT/B and, to A23 in the M58LR256KT/B.
11/120
Table Ordering information scheme

Example:

M58LR128KT
70 ZB 5 E

Device type M58

Architecture L = multilevel, multiple bank, burst mode

Operating voltage R = VDD = V to V, VDDQ = V to V

Density 128 = 128 Mbit x16 256 = 256 Mbit x16

Technology K = 65 nm technology

Parameter location T = top boot B = bottom boot

Speed 70 = 70 ns 85 = 85 ns

Package ZB = VFBGA56, x 9 mm, mm pitch 1 ZC = VFBGA79, 9 x 11 mm, mm pitch ZQ = TFBGA88, 8 x 10mm, mm pitch

Temperature range 5 = to 85 °C

Packing option E = package, standard packing F = package, tape and reel packing

The M58LR128KT/B are available in the ZB package, while the M58LR256KT/B are available M58LR256KT/B are available in the ZC and ZQ package.

Devices are shipped from the factory with the memory content bits erased to
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M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB

Part numbering

For a list of available options speed, package, etc. or for further information on any aspect of this device, please contact the Numonyx sales office nearest to you.
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Block address tables

M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB

Appendix A Block address tables

The following set of equations can be used to calculate a complete set of block addresses for the M58LRxxxKT/B using the information contained in Tables 36 to

To calculate the block base address from the block number:

First it is necessary to calculate the bank number and the block number offset. This can be achieved using the following formulas:

Bank_Number = Block_Number − 3 / 8 Block_Number_Offset = Block_Number − 3 − Bank_Number x 8 ,

If Bank_Number= 0, the block base address can be directly read from Tables 36 and 42 parameter bank block addresses in the address range column, in the row that corresponds to the given block number.

Otherwise Block_Base_Address = Bank_Base_Address + Block_Base_Address_Offset

To calculate the bank number and the block number from the block base address:

If the address is in the range of the parameter bank, the Bank Number is 0 and the Block Number can be directly read from Tables 36 and 42 parameter bank Block Addresses , in the Block Number column, in the row that corresponds to the address given. Otherwise, the Block Number can be calculated using the formulas below:

For the top configuration M58LR256KT and M58LR128KT Block_Number = NOT address / 216 + 3

For the bottom configuration M58LR256KB and M58LR128KB Block_Number = address / 216 + 3

For both configurations the Bank Number and the Block Number Offset can be calculated using the following formulas:

Bank_Number = Block_Number − 3 / 8 Block_Number_Offset = Block_Number − 3 − Bank_Number x 8
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M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB

Block address tables

Table M58LR128KT - Parameter bank block addresses

Block number
bottom view package outline, Table 23 VFBGA79 9x11mm - pitch -package outline, and amended Table 32 Ordering information
scheme to provide the ZB package information, which is available for
the M58LR128KT/B devices.

Add 79B vfBGA 9x11 package for 256Mbit. Add 88b package 8x10.

Change from T=-25°C to T=-30°C

Change Terase for Boot sectors 0.4s to 0.6s

Change the package reference from ZA to ZQ.
120/120

M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB

Please Read Carefully INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY

WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.

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Datasheet ID: M58LR128KT85ZB6E 648299