M45PE40-VMP6TG TR

M45PE40-VMP6TG TR Datasheet

M45PE40

Part	Datasheet
M45PE40-VMP6TG TR	M45PE40-VMP6TG TR (pdf)

Related Parts	Information
M45PE40-VMP6G	M45PE40-VMP6G
M45PE40-VMW6TG TR	M45PE40-VMW6TG TR

PDF Datasheet Preview
M45PE40 4-Mbit, page-erasable serial flash memory with byte-alterability and a 75 MHz SPI bus interface • SPI bus compatible serial interface • 75 MHz clock rate maximum • V to V single supply voltage • 4-Mbit page-erasable flash memory • Page size 256 bytes: Page write in 11 ms typical Page program in ms typical Page erase in 10 ms typical • Sector erase 64 Kbytes • Hardware write protection of the bottom sector 64 Kbytes • Electronic signature JEDEC standard two-byte signature 4013h Unique ID code UID with 16 bytes read- only, available upon customer request only in the T9HX process • Deep power-down mode 1 µA typical • More than 100 000 write cycles • More than 20 years data retention • Packages RoHS compliant VFQFPN8 MP 6 x 5 mm MLP8 SO8W MW 208 mils width SO8N MN 150 mils width May 2008 1/49 Contents Contents M45PE40 Description 6 Signal descriptions 8 Serial data output Q 8 Serial data input D 8 Serial Clock C 8 Chip Select S 8 Reset 8 Write Protect W 8 VCC supply voltage 9 VSS ground 9 SPI modes 10 Operating features 12 Sharing the overhead of modifying data 12 An easy way to modify data 12 A fast way to modify data 13 Polling during a write, program or erase cycle 13 Reset 13 Active power, standby power and deep power-down modes 13 Status register 14 Protection modes 14 Memory organization 15 Instructions 17 Write Enable WREN 18 Write disable WRDI 18 Read identification RDID 19 Read status register RDSR 21 WIP bit 21 2/49 Ordering information 47 3/49 List of tables List of tables M45PE40 Table Table Table Table 4/49 M45PE40 List of figures List of figures Figure Figure Figure Logic diagram 6 VFQFPN and SO connections 7 Bus master and memory devices on the SPI bus 10 SPI modes supported 11 Block diagram 16 Write enable WREN instruction sequence 18 Write disable WRDI instruction sequence 18 Read identification RDID instruction sequence and data-out sequence 20 Read status register RDSR instruction sequence and data-out sequence 21 Read data bytes READ instruction sequence and data-out sequence 22 Read data bytes at higher speed FAST_READ instruction sequence and data-out sequence 23 Page write PW instruction sequence 25 Page program PP instruction sequence 27 Page erase PE instruction sequence 28 Sector erase SE instruction sequence 29 Deep power-down DP instruction sequence 30 Release from deep power-down RDP instruction sequence 31 Power-up timing 33 AC measurement I/O waveform 35 Serial input timing 41 Write protect setup and hold timing 41 Output timing 41 Reset AC waveforms 42 VFQFPN8 MLP8 8-lead very thin dual flat package no lead, 6 x 5 mm, package outline. 43 SO8 wide 8 lead plastic small outline, 208 mils body width, package outline 45 SO8N 8 lead plastic small outline, 150 mils body width, package outline 46 5/49 M45PE40 The M45PE40 is a 4-Mbit 512 Kbit x8 bit serial paged flash memory accessed by a high speed SPI-compatible bus. The memory can be written or programmed 1 to 256 bytes at a time, using the page write or page program instruction. The page write instruction consists of an integrated page erase cycle followed by a page program cycle. The memory is organized as 8 sectors, each containing 256 pages. Each page is 256 bytes wide. Thus, the whole memory can be viewed as consisting of 2048 pages, or 524288 bytes. The memory can be erased a page at a time, using the page erase instruction, or a sector at a time, using the sector erase instruction. Important note This datasheet details the functionality of the M45PE40 devices, based on the previous T7X process or based on the current T9HX process available since August Delivery of parts operating with a maximum clock rate of 75 MHz starts from week 8 of Figure Logic diagram D C S W Reset Q M45PE40 AI04040C 6/49 M45PE40 Table Signal names Signal name Function C D Q S W Reset VCC VSS Serial Clock Serial data input Serial data output Chip Select Write Protect Reset Supply voltage Ground Figure VFQFPN and SO connections M45PE40 Direction Input Output Input D1 C2 Reset 3 S4 7 VSS 6 VCC 5W AI04041D There is an exposed central pad on the underside of the VFQFPN package. This is pulled, internally, to VSS, and must not be allowed to be connected to any other voltage or signal line on the PCB. See Section 11 Package mechanical for package dimensions, and how to identify pin-1. 7/49 Signal descriptions Signal descriptions M45PE40 Serial data output Q This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock C . Details of how to find the technology process in the marking are given in AN1995, see also Section 12 Ordering information. tCH + tCL must be greater than or equal to 1/ fC. Value guaranteed by characterization, not 100% tested in production. Only applicable as a constraint for a WRSR instruction when SRWD is set to When using PP and PW instructions to update consecutive bytes, optimized timings are obtained with one sequence including all the bytes versus several sequences of only a few bytes 1 n int A corresponds to the upper integer part of A. For instance, int 12/8 = 2, int 32/8 = 4 int 15.3 40/49 M45PE40 Figure Serial input timing S tCHSL tSLCH C tDVCH tCHDX MSB IN High Impedance Q Figure Write protect setup and hold timing W tWHSL DC and AC parameters tSHSL tCHSH tSHCH tCLCH LSB IN tCHCL AI01447C tSHWL High Impedance Q Figure Output timing C tCLQV tCLQX Q tCLQX tCLQV D ADDR.LSB IN AI07439 tCH tCL tSHQZ tQLQH tQHQL LSB OUT AI01449e 41/49 DC and AC parameters M45PE40 Table Reset conditions Test conditions specified in Table 8 and Table 9 Symbol Alt 12 Ordering information Ordering information Note: Table Ordering information scheme Example: M45PE40 V MP 6 T G Device type M45PE = page-erasable serial flash memory Device function 40 = 4-Mbit 512 Kbits x8 Operating voltage V = VCC = V to V Package MW = SO8W 208 mils width MN = SO8N 150 mils width 1 MP = VFQFPN8 6 x 5 mm MLP8 Device grade 6 = Industrial temperature range, to 85 °C. Device tested with standard test flow Option blank = standard packing T = tape and reel packing Plating technology P or G = RoHS compliant Package available only in T9HX technology. For a list of available options speed, package, etc. , for further information on any aspect of this device, or when ordering parts operating at 75 MHz µm technology, process digit ‘4’ , please contact your nearest Numonyx sales office. 47/49 M45PE40 Version Changes 04-Dec-2003 Initial release. 23-Jan-2004 31-Mar-2004 2 SO16 pin-out corrected. Soldering temperature information clarified for RoHS compliant devices. Device grade information clarified. 05-Aug-2004 11-Jan-2005 4-Oct-2005 18-Jan-2007 10-Dec-2007 14-May-2008 4 Device grade information further clarified. Document status promoted from preliminary data to datasheet. Minor text changes. 5 Notes 1 and 2 removed from Table 20 Ordering information scheme. SO16 package removed and SO8 wide package added. Added Table 13 AC characteristics 33 MHz operation . An easy way to modify data, A fast way to modify data, Page write PW and Page program PP sections updated to explain optimal use of page write and page program instructions. Updated ICC3 values in Table 11 DC characteristics. Updated Table 20 Ordering information scheme. information added. 50 MHz frequency added. VCC supply voltage and VSS ground descriptions added. Figure 3 Bus master and memory devices on the SPI bus updated and explanatory paragraph added. At power-up The write in progress WIP bit is reset. VIO max modified in Table 7 Absolute maximum ratings. tRLRH, tRHSL and tSHSR removed from Table 12 AC characteristics 25 MHz operation and Table 16 Reset conditions added. SO8N package added, SO8W and VFQFPN package specifications updated see Section 11 Package mechanical . Blank option removed below Plating technology in Table 20 Ordering information scheme. 8 Applied Numonyx branding. Removed ‘low voltage’ from the title. Updated the value for the maximum clock frequency from 50 to 75 MHz throughout the document. Added Table 15 AC characteristics 75 MHz operation, T9HX µm process and text in Section 11 Package mechanical. Modified Table 11 DC characteristics, Figure 3 Bus master and memory devices on the SPI bus, and Section Read identification RDID . 48/49 M45PE40 Please Read Carefully INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. Numonyx may make changes to specifications and product descriptions at any time, without notice. Numonyx, B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Numonyx reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by visiting Numonyx's website at Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright 11/5/7, Numonyx, B.V., All Rights Reserved. 49/49

PDF Datasheet Preview

M45PE40
4-Mbit, page-erasable serial flash memory with byte-alterability and a 75 MHz SPI bus interface
• SPI bus compatible serial interface
• 75 MHz clock rate maximum
• V to V single supply voltage
• 4-Mbit page-erasable flash memory
• Page size 256 bytes:

Page write in 11 ms typical Page program in ms typical Page erase in 10 ms typical
• Sector erase 64 Kbytes
• Hardware write protection of the bottom sector 64 Kbytes
• Electronic signature JEDEC standard two-byte signature
4013h Unique ID code UID with 16 bytes read-
only, available upon customer request only in the T9HX process
• Deep power-down mode 1 µA typical
• More than 100 000 write cycles
• More than 20 years data retention
• Packages RoHS compliant

VFQFPN8 MP 6 x 5 mm MLP8

SO8W MW 208 mils width

SO8N MN 150 mils width

May 2008
1/49

Contents

Contents

M45PE40

Description 6

Signal descriptions 8

Serial data output Q 8

Serial data input D 8

Serial Clock C 8

Chip Select S 8

Reset 8

Write Protect W 8

VCC supply voltage 9 VSS ground 9

SPI modes 10

Operating features 12

Sharing the overhead of modifying data 12

An easy way to modify data 12

A fast way to modify data 13

Polling during a write, program or erase cycle 13

Reset 13

Active power, standby power and deep power-down modes 13

Status register 14

Protection modes 14

Memory organization 15

Instructions 17

Write Enable WREN 18

Write disable WRDI 18

Read identification RDID 19

Read status register RDSR 21

WIP bit 21
2/49
Ordering information 47
3/49

List of tables

List of tables

M45PE40

Table

Table

Table

Table
4/49

M45PE40

List of figures

List of figures

Figure

Figure

Figure

Logic diagram 6 VFQFPN and SO connections 7 Bus master and memory devices on the SPI bus 10 SPI modes supported 11 Block diagram 16 Write enable WREN instruction sequence 18 Write disable WRDI instruction sequence 18 Read identification RDID instruction sequence and data-out sequence 20 Read status register RDSR instruction sequence and data-out sequence 21 Read data bytes READ instruction sequence and data-out sequence 22 Read data bytes at higher speed FAST_READ instruction sequence and data-out sequence 23 Page write PW instruction sequence 25 Page program PP instruction sequence 27 Page erase PE instruction sequence 28 Sector erase SE instruction sequence 29 Deep power-down DP instruction sequence 30 Release from deep power-down RDP instruction sequence 31 Power-up timing 33 AC measurement I/O waveform 35 Serial input timing 41 Write protect setup and hold timing 41 Output timing 41 Reset AC waveforms 42 VFQFPN8 MLP8 8-lead very thin dual flat package no lead, 6 x 5 mm, package outline. 43 SO8 wide 8 lead plastic small outline, 208 mils body width, package outline 45 SO8N 8 lead plastic small outline, 150 mils body width, package outline 46
5/49

M45PE40

The M45PE40 is a 4-Mbit 512 Kbit x8 bit serial paged flash memory accessed by a high speed SPI-compatible bus.

The memory can be written or programmed 1 to 256 bytes at a time, using the page write or page program instruction. The page write instruction consists of an integrated page erase cycle followed by a page program cycle.

The memory is organized as 8 sectors, each containing 256 pages. Each page is 256 bytes wide. Thus, the whole memory can be viewed as consisting of 2048 pages, or 524288 bytes.

The memory can be erased a page at a time, using the page erase instruction, or a sector at a time, using the sector erase instruction.

Important note

This datasheet details the functionality of the M45PE40 devices, based on the previous T7X process or based on the current T9HX process available since August Delivery of parts operating with a maximum clock rate of 75 MHz starts from week 8 of

Figure Logic diagram

D C S W Reset

Q M45PE40

AI04040C
6/49

M45PE40

Table Signal names

Signal name

Function

C D Q S W Reset VCC VSS

Serial Clock Serial data input Serial data output Chip Select Write Protect Reset Supply voltage Ground

Figure VFQFPN and SO connections

M45PE40

Direction Input Output Input

D1 C2 Reset 3 S4
7 VSS 6 VCC 5W

AI04041D

There is an exposed central pad on the underside of the VFQFPN package. This is pulled, internally, to VSS, and must not be allowed to be connected to any other voltage or signal line on the PCB.

See Section 11 Package mechanical for package dimensions, and how to identify pin-1.
7/49

Signal descriptions

Signal descriptions

M45PE40

Serial data output Q

This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock C .
Details of how to find the technology process in the marking are given in AN1995, see also Section 12 Ordering information.
tCH + tCL must be greater than or equal to 1/ fC. Value guaranteed by characterization, not 100% tested in production.

Only applicable as a constraint for a WRSR instruction when SRWD is set to

When using PP and PW instructions to update consecutive bytes, optimized timings are obtained with one sequence including all the bytes versus several sequences of only a few bytes 1 n
int A corresponds to the upper integer part of A. For instance, int 12/8 = 2, int 32/8 = 4 int 15.3
40/49

M45PE40 Figure Serial input timing

S tCHSL
tSLCH

C tDVCH
tCHDX

MSB IN

High Impedance Q

Figure Write protect setup and hold timing

W tWHSL

DC and AC parameters
tSHSL
tCHSH
tSHCH
tCLCH LSB IN
tCHCL

AI01447C
tSHWL

High Impedance Q

Figure Output timing

C tCLQV
tCLQX Q
tCLQX
tCLQV

D ADDR.LSB IN

AI07439
tCH tCL
tSHQZ
tQLQH tQHQL

LSB OUT

AI01449e
41/49

DC and AC parameters

M45PE40

Table Reset conditions Test conditions specified in Table 8 and Table 9

Symbol Alt
12 Ordering information
Ordering information

Note:
Table Ordering information scheme

Example:

M45PE40

V MP 6 T G

Device type M45PE = page-erasable serial flash memory

Device function 40 = 4-Mbit 512 Kbits x8

Operating voltage V = VCC = V to V

Package MW = SO8W 208 mils width MN = SO8N 150 mils width 1 MP = VFQFPN8 6 x 5 mm MLP8

Device grade
6 = Industrial temperature range, to 85 °C. Device tested with standard test flow

Option blank = standard packing T = tape and reel packing

Plating technology P or G = RoHS compliant

Package available only in T9HX technology.
For a list of available options speed, package, etc. , for further information on any aspect of this device, or when ordering parts operating at 75 MHz µm technology, process digit ‘4’ , please contact your nearest Numonyx sales office.
47/49

M45PE40

Version

Changes
04-Dec-2003

Initial release.
23-Jan-2004 31-Mar-2004
2 SO16 pin-out corrected.

Soldering temperature information clarified for RoHS compliant devices. Device grade information clarified.
05-Aug-2004 11-Jan-2005 4-Oct-2005
18-Jan-2007 10-Dec-2007 14-May-2008
4 Device grade information further clarified.
Document status promoted from preliminary data to datasheet. Minor text changes. 5 Notes 1 and 2 removed from Table 20 Ordering information scheme. SO16 package removed and SO8 wide package added.

Added Table 13 AC characteristics 33 MHz operation . An easy way to
modify data, A fast way to modify data, Page write PW and Page
program PP sections updated to explain optimal use of page write and page program instructions. Updated ICC3 values in Table 11 DC
characteristics. Updated Table 20 Ordering information scheme.
information added.
50 MHz frequency added. VCC supply voltage and VSS ground descriptions added. Figure 3 Bus master and memory devices on the SPI bus updated and explanatory paragraph added.

At power-up The write in progress WIP bit is reset.

VIO max modified in Table 7 Absolute maximum ratings. tRLRH, tRHSL and tSHSR removed from Table 12 AC characteristics 25

MHz operation and Table 16 Reset conditions added.

SO8N package added, SO8W and VFQFPN package specifications updated see Section 11 Package mechanical .
Blank option removed below Plating technology in Table 20 Ordering information scheme.
8 Applied Numonyx branding.

Removed ‘low voltage’ from the title.

Updated the value for the maximum clock frequency from 50 to
75 MHz throughout the document.

Added Table 15 AC characteristics 75 MHz operation, T9HX
µm process and text in Section 11 Package mechanical.

Modified Table 11 DC characteristics, Figure 3 Bus master and
memory devices on the SPI bus, and Section Read identification

RDID .
48/49

M45PE40

Please Read Carefully INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY

WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.

Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications.

Numonyx may make changes to specifications and product descriptions at any time, without notice. Numonyx, B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied,
by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Numonyx reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by
visiting Numonyx's website at Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries.
*Other names and brands may be claimed as the property of others. Copyright 11/5/7, Numonyx, B.V., All Rights Reserved.
49/49

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived M45PE40-VMP6TGTR Datasheet file may be downloaded here without warranties.

Datasheet ID: M45PE40-VMP6TGTR 648297