M29W800DT90N1

M29W800DT90N1 Datasheet

M29W800DT M29W800DB

Part	Datasheet
M29W800DT90N1	M29W800DT90N1 (pdf)

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PDF Datasheet Preview
M29W800DT M29W800DB 8-Mbit 1 Mbit x 8 or 512 Kbits x 16, boot block 3 V supply flash memory - Supply voltage VCC = V to V for program, erase and read - Access times 45, 70, 90 ns - Programming time 10 us per byte/word typical - 19 memory blocks 1 boot block top or bottom location 2 parameter and 16 main blocks - Program/erase controller Embedded byte/word program algorithms - Erase suspend and resume modes Read and program another block during erase suspend - Unlock bypass program command Faster production/batch programming - Temporary block unprotection mode - Common flash interface 64-bit security code - Low power consumption Standby and automatic standby - 100,000 program/erase cycles per block - Electronic signature Manufacturer code 0020h Top device code M29W800DT 22D7h Bottom device code M29W800DB 225Bh SO44 M TSOP48 N 12 x 20 mm FBGA TFBGA48 ZE 6 x 8 mm April 2009 1/52 Contents Contents M29W800DT, M29W800DB Description 6 Signal descriptions 12 Address inputs A0-A18 12 Data inputs/outputs DQ0-DQ7 12 Data inputs/outputs DQ8-DQ14 12 Data input/output or address input DQ15A-1 12 Chip enable E 12 Output enable G 12 Write enable W 13 Reset/block temporary unprotect RP 13 Ready/busy output RB 13 Byte/word organization select BYTE 13 VCC supply voltage 13 VSS ground 14 Bus operations 15 Bus read 15 Bus write 15 Output disable 15 Standby 15 Automatic standby 15 Special bus operations 16 Electronic signature 16 Ordering information 38 Appendix A Block address table 39 Appendix B Common flash interface CFI . 41 Appendix C Block protection. 45 C.1 Programmer technique 45 C.2 In-system technique 45 3/52 List of tables List of tables M29W800DT, M29W800DB Table 4/52 M29W800DT, M29W800DB List of figures List of figures Figure Logic diagram 6 SO connections 7 TSOP connections 8 TFBGA connections top view through package 9 Block addresses x 8 10 Block addresses x 16 11 Data polling flowchart 25 Data toggle flowchart 26 AC measurement I/O waveform 28 AC measurement load circuit 29 Read mode AC waveforms 30 Write AC waveforms, write enable controlled 31 Write AC waveforms, chip enable controlled 32 Reset/block temporary unprotect AC waveforms 33 SO44 44 lead plastic small outline, 525 mils body width, package outline 34 TSOP48 48 lead plastic thin small outline, 12 x 20 mm, package outline 36 TFBGA48 6 x 8 mm 6 x 8 ball array mm pitch, bottom view package outline. 37 Programmer equipment block protect flowchart 47 Programmer equipment chip unprotect flowchart 48 In-system equipment block protect flowchart 49 In-system equipment chip unprotect flowchart 50 5/52 M29W800DT, M29W800DB The M29W800D is a 8-Mbit 1 Mbit x 8 or 512 Kbits x 16 non-volatile memory that can be read, erased and reprogrammed. These operations can be performed using a single low voltage to V supply. On power-up the memory defaults to its read mode where it can be read in the same way as a ROM or EPROM. The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased. Each block can be protected independently to prevent accidental program or erase commands from modifying the memory. Program and erase commands are written to the command interface of the memory. An on-chip program/erase controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The end of a program or erase operation can be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards. The blocks in the memory are asymmetrically arranged, see Figure 5 Block addresses x 8 and Figure 6 Block addresses x The first or last 64 Kbytes have been divided into four additional blocks. The 16-Kbyte boot block can be used for small initialization code to start the microprocessor, the two 8-Kbyte parameter blocks can be used for parameter storage and the remaining 32-Kbyte is a small main block where the application may be stored. Chip Enable, Output Enable and Write Enable signals control the bus operation of the memory. They allow simple connection to most microprocessors, often without additional logic. The memory is offered in SO44, TSOP48 12 x 20 mm and TFBGA48 6 x 8 mm pitch packages. The memory is supplied with all the bits erased set to Figure Logic diagram VCC 19 A0-A18 15 DQ0-DQ14 W E G RP BYTE M29W800DT M29W800DB AI05470B 6/52 M29W800DT, M29W800DB Table Signal names Signal A0-A18 DQ0-DQ7 DQ8-DQ14 E G W RP RB BYTE VCC VSS NC Address inputs Data inputs/outputs Data inputs/outputs Data input/output or address input Chip enable Output enable Write enable Reset/block temporary unprotect Ready/busy output not available on SO44 package Byte/word organization select Supply voltage Ground Not connected internally Figure SO connections Direction Inputs I/O I/O I/O Input Output Input RP A18 A17 A7 A6 A5 A4 A3 A2 A1 A0 E VSS G DQ0 DQ8 DQ1 DQ9 DQ2 DQ10 DQ3 DQ11 11 M29W800DT 34 12 M29W800DB 33 W NC A8 A9 A10 A11 A12 A13 A14 A15 A16 BYTE VSS DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC AI05462b 7/52 Description Figure TSOP connections M29W800DT, M29W800DB A15 1 48 A16 BYTE Ordering information Ordering information M29W800DT, M29W800DB Note: Table Ordering information scheme Example: Device type M29 Operating voltage W = VCC = to V Device function 800D = 8-Mbit x 8/x 16 , boot block Array matrix T = top boot B = bottom boot Speed 45 = 45 ns 70 = 70 ns 90 = 90 ns Package M = SO44 N = TSOP48 12 x 20 mm ZE = TFBGA48 6 x 8 mm, mm pitch Temperature range 6 = to 85 °C 1 = 0 to 70 °C Option T = tape & reel packing E = lead-free package, standard packing F = lead-free package, tape & reel packing M29W800DB 90 N 6 T For a list of available options speed, package, etc. or for further information on any aspect of this device, please contact your nearest Numonyx Sales Office. 38/52 M29W800DT, M29W800DB Appendix A Block address table Table Top boot block addresses, M29W800DT # Size Kbytes Address range x 8 FA000h-FBFFFh F8000h-F9FFFh F0000h-F7FFFh E0000h-EFFFFh D0000h-DFFFFh C0000h-CFFFFh B0000h-BFFFFh A0000h-AFFFFh 90000h-9FFFFh 80000h-8FFFFh 70000h-7FFFFh 60000h-6FFFFh 50000h-5FFFFh 40000h-4FFFFh 30000h-3FFFFh 20000h-2FFFFh 10000h-1FFFFh Block address table Address range x 16 7E000h-7FFFFh 7D000h-7DFFFh 7C000h-7CFFFh 78000h-7BFFFh 70000h-77FFFh 68000h-6FFFFh 60000h-67FFFh 58000h-5FFFFh 50000h-57FFFh 48000h-4FFFFh 40000h-47FFFh 38000h-3FFFFh 30000h-37FFFh 28000h-2FFFFh 20000h-27FFFh 18000h-1FFFFh 10000h-17FFFh 08000h-0FFFFh 39/52 Block address table M29W800DT, M29W800DB Table Bottom boot block addresses, M29W800DB # Size Kbytes Address range x 8 E0000h-EFFFFh D0000h-DFFFFh C0000h-CFFFFh B0000h-BFFFFh A0000h-AFFFFh 90000h-9FFFFh 80000h-8FFFFh 70000h-7FFFFh 60000h-6FFFFh 50000h-5FFFFh 40000h-4FFFFh 30000h-3FFFFh 20000h-2FFFFh 10000h-1FFFFh 08000h-0FFFFh 06000h-07FFFh 04000h-05FFFh Address range x 16 78000h-7FFFFh 70000h-77FFFh 68000h-6FFFFh 60000h-67FFFh 58000h-5FFFFh 50000h-57FFFh 48000h-4FFFFh 40000h-47FFFh 38000h-3FFFFh 30000h-37FFFh 28000h-2FFFFh 20000h-27FFFh 18000h-1FFFFh 10000h-17FFFh 08000h-0FFFFh 04000h-07FFFh 03000h-03FFFh 02000h-02FFFh 40/52 M29W800DT, M29W800DB Common flash interface CFI Appendix B Common flash interface CFI The common flash interface is a JEDEC approved, standardized data structure that can be read from the flash memory device. It allows a system software to query the device to determine various electrical and timing parameters, density information and functions supported by the memory. The system can interface easily with the device, enabling the software to upgrade itself when necessary. When the CFI Query command is issued the device enters CFI query mode and the data structure is read from the memory. Table 22, Table 23, Table 24, Table 25, Table 26 and Table 27 show the addresses used to retrieve the data. Erase suspend latency time typical and maximum and data retention parameters added to Table 6 Program/erase times and program/erase endurance cycles, and typical after 100k W/E cycles column removed. Minimum voltage corrected for 70 ns speed class in Table 9 Operating and AC measurement conditions. Logic diagram and data toggle flowchart corrected. Lead-free package options E and F added to Table 19 Ordering information scheme. TSOP48 package outline and mechanical data updated. TFBGA48 6 x 8 mm 6 x 8 active ball array mm pitch added. 5 Table 9 Operating and AC measurement conditions updated for 70 ns speed option. 6 Figure 2 SO connections updated. 7 45 ns speed class added. Removed TFBGA48 ZA 6 x 9 mm package. Converted to new ST 8 corporate template. 9 Applied Numonyx branding. 10 Minor text changes. 51/52 M29W800DT, M29W800DB Please Read Carefully INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. Numonyx may make changes to specifications and product descriptions at any time, without notice. Numonyx, B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Numonyx reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by visiting Numonyx's website at Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright 2009, Numonyx, B.V., All Rights Reserved. 52/52

PDF Datasheet Preview

M29W800DT M29W800DB
8-Mbit 1 Mbit x 8 or 512 Kbits x 16, boot block 3 V supply flash memory
- Supply voltage VCC = V to V for program, erase and read
- Access times 45, 70, 90 ns - Programming time
10 us per byte/word typical - 19 memory blocks
1 boot block top or bottom location 2 parameter and 16 main blocks - Program/erase controller Embedded byte/word program algorithms - Erase suspend and resume modes Read and program another block during
erase suspend - Unlock bypass program command

Faster production/batch programming - Temporary block unprotection mode - Common flash interface
64-bit security code - Low power consumption

Standby and automatic standby - 100,000 program/erase cycles per block - Electronic signature

Manufacturer code 0020h Top device code M29W800DT 22D7h Bottom device code M29W800DB 225Bh

SO44 M

TSOP48 N 12 x 20 mm

FBGA

TFBGA48 ZE 6 x 8 mm

April 2009
1/52

Contents

Contents

M29W800DT, M29W800DB

Description 6

Signal descriptions 12

Address inputs A0-A18 12

Data inputs/outputs DQ0-DQ7 12

Data inputs/outputs DQ8-DQ14 12

Data input/output or address input DQ15A-1 12

Chip enable E 12

Output enable G 12

Write enable W 13

Reset/block temporary unprotect RP 13

Ready/busy output RB 13

Byte/word organization select BYTE 13

VCC supply voltage 13 VSS ground 14

Bus operations 15

Bus read 15

Bus write 15

Output disable 15

Standby 15

Automatic standby 15

Special bus operations 16

Electronic signature 16
Ordering information 38

Appendix A Block address table 39

Appendix B Common flash interface CFI . 41

Appendix C Block protection. 45

C.1 Programmer technique 45 C.2 In-system technique 45
3/52

List of tables

List of tables

M29W800DT, M29W800DB

Table
4/52

M29W800DT, M29W800DB

List of figures

List of figures

Figure

Logic diagram 6 SO connections 7 TSOP connections 8 TFBGA connections top view through package 9 Block addresses x 8 10 Block addresses x 16 11 Data polling flowchart 25 Data toggle flowchart 26 AC measurement I/O waveform 28 AC measurement load circuit 29 Read mode AC waveforms 30 Write AC waveforms, write enable controlled 31 Write AC waveforms, chip enable controlled 32 Reset/block temporary unprotect AC waveforms 33 SO44 44 lead plastic small outline, 525 mils body width, package outline 34 TSOP48 48 lead plastic thin small outline, 12 x 20 mm, package outline 36 TFBGA48 6 x 8 mm 6 x 8 ball array mm pitch, bottom view package outline. 37 Programmer equipment block protect flowchart 47 Programmer equipment chip unprotect flowchart 48 In-system equipment block protect flowchart 49 In-system equipment chip unprotect flowchart 50
5/52

M29W800DT, M29W800DB

The M29W800D is a 8-Mbit 1 Mbit x 8 or 512 Kbits x 16 non-volatile memory that can be read, erased and reprogrammed. These operations can be performed using a single low voltage to V supply. On power-up the memory defaults to its read mode where it can be read in the same way as a ROM or EPROM.

The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased. Each block can be protected independently to prevent accidental program or erase commands from modifying the memory. Program and erase commands are written to the command interface of the memory. An on-chip program/erase controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents.

The end of a program or erase operation can be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards.

The blocks in the memory are asymmetrically arranged, see Figure 5 Block addresses x 8 and Figure 6 Block addresses x The first or last 64 Kbytes have been divided into four additional blocks. The 16-Kbyte boot block can be used for small initialization code to start the microprocessor, the two 8-Kbyte parameter blocks can be used for parameter storage and the remaining 32-Kbyte is a small main block where the application may be stored.

Chip Enable, Output Enable and Write Enable signals control the bus operation of the memory. They allow simple connection to most microprocessors, often without additional logic.

The memory is offered in SO44, TSOP48 12 x 20 mm and TFBGA48 6 x 8 mm pitch packages. The memory is supplied with all the bits erased set to

Figure Logic diagram VCC
19 A0-A18
15 DQ0-DQ14

W E G RP BYTE

M29W800DT M29W800DB

AI05470B
6/52

M29W800DT, M29W800DB

Table Signal names

Signal

A0-A18 DQ0-DQ7 DQ8-DQ14 E G W RP RB BYTE VCC VSS NC

Address inputs Data inputs/outputs Data inputs/outputs Data input/output or address input Chip enable Output enable Write enable Reset/block temporary unprotect Ready/busy output not available on SO44 package Byte/word organization select Supply voltage Ground Not connected internally

Figure SO connections

Direction Inputs I/O I/O I/O Input Output Input

RP A18 A17

A7 A6 A5 A4 A3 A2 A1 A0

E VSS

G DQ0 DQ8 DQ1 DQ9 DQ2 DQ10 DQ3 DQ11
11 M29W800DT 34 12 M29W800DB 33

W NC A8 A9 A10 A11 A12 A13 A14 A15 A16 BYTE VSS DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC

AI05462b
7/52

Description Figure TSOP connections

M29W800DT, M29W800DB

A15 1
48 A16

BYTE
Ordering information
Ordering information

M29W800DT, M29W800DB

Note:
Table Ordering information scheme

Example:

Device type M29

Operating voltage W = VCC = to V

Device function 800D = 8-Mbit x 8/x 16 , boot block

Array matrix T = top boot B = bottom boot

Speed 45 = 45 ns 70 = 70 ns 90 = 90 ns

Package M = SO44 N = TSOP48 12 x 20 mm ZE = TFBGA48 6 x 8 mm, mm pitch

Temperature range 6 = to 85 °C 1 = 0 to 70 °C

Option T = tape & reel packing E = lead-free package, standard packing F = lead-free package, tape & reel packing

M29W800DB
90 N 6 T

For a list of available options speed, package, etc. or for further information on any aspect of this device, please contact your nearest Numonyx Sales Office.
38/52

M29W800DT, M29W800DB

Appendix A Block address table

Table Top boot block addresses, M29W800DT
# Size Kbytes

Address range x 8

FA000h-FBFFFh F8000h-F9FFFh F0000h-F7FFFh E0000h-EFFFFh D0000h-DFFFFh C0000h-CFFFFh B0000h-BFFFFh A0000h-AFFFFh 90000h-9FFFFh 80000h-8FFFFh 70000h-7FFFFh 60000h-6FFFFh 50000h-5FFFFh 40000h-4FFFFh 30000h-3FFFFh 20000h-2FFFFh 10000h-1FFFFh

Block address table

Address range x 16 7E000h-7FFFFh 7D000h-7DFFFh 7C000h-7CFFFh 78000h-7BFFFh 70000h-77FFFh 68000h-6FFFFh 60000h-67FFFh 58000h-5FFFFh 50000h-57FFFh 48000h-4FFFFh 40000h-47FFFh 38000h-3FFFFh 30000h-37FFFh 28000h-2FFFFh 20000h-27FFFh 18000h-1FFFFh 10000h-17FFFh 08000h-0FFFFh
39/52

Block address table

M29W800DT, M29W800DB

Table Bottom boot block addresses, M29W800DB
# Size Kbytes

Address range x 8

E0000h-EFFFFh

D0000h-DFFFFh C0000h-CFFFFh B0000h-BFFFFh A0000h-AFFFFh 90000h-9FFFFh 80000h-8FFFFh 70000h-7FFFFh
60000h-6FFFFh
50000h-5FFFFh 40000h-4FFFFh
30000h-3FFFFh
20000h-2FFFFh 10000h-1FFFFh 08000h-0FFFFh 06000h-07FFFh 04000h-05FFFh

Address range x 16 78000h-7FFFFh 70000h-77FFFh 68000h-6FFFFh 60000h-67FFFh 58000h-5FFFFh 50000h-57FFFh 48000h-4FFFFh 40000h-47FFFh 38000h-3FFFFh 30000h-37FFFh 28000h-2FFFFh 20000h-27FFFh 18000h-1FFFFh 10000h-17FFFh 08000h-0FFFFh 04000h-07FFFh 03000h-03FFFh 02000h-02FFFh
40/52

M29W800DT, M29W800DB

Common flash interface CFI

Appendix B Common flash interface CFI

The common flash interface is a JEDEC approved, standardized data structure that can be read from the flash memory device. It allows a system software to query the device to determine various electrical and timing parameters, density information and functions supported by the memory. The system can interface easily with the device, enabling the software to upgrade itself when necessary.

When the CFI Query command is issued the device enters CFI query mode and the data structure is read from the memory. Table 22, Table 23, Table 24, Table 25, Table 26 and Table 27 show the addresses used to retrieve the data.
Erase suspend latency time typical and maximum and data retention parameters added to Table 6 Program/erase times and program/erase endurance cycles, and typical after 100k W/E cycles column removed. Minimum voltage corrected for 70 ns speed class in Table 9 Operating and AC measurement conditions. Logic diagram and data toggle flowchart corrected. Lead-free package options E and F added to Table 19 Ordering information scheme.

TSOP48 package outline and mechanical data updated. TFBGA48 6 x 8 mm 6 x 8 active ball array mm pitch added. 5 Table 9 Operating and AC measurement conditions updated for 70 ns speed option.
6 Figure 2 SO connections updated.
7 45 ns speed class added.

Removed TFBGA48 ZA 6 x 9 mm package. Converted to new ST 8
corporate template.
9 Applied Numonyx branding.
10 Minor text changes.
51/52

M29W800DT, M29W800DB

Please Read Carefully INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY

WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.

Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications.

Numonyx may make changes to specifications and product descriptions at any time, without notice. Numonyx, B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied,
by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Numonyx reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by
visiting Numonyx's website at Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries.
*Other names and brands may be claimed as the property of others. Copyright 2009, Numonyx, B.V., All Rights Reserved.
52/52

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Datasheet ID: M29W800DT90N1 648294