M25P10-AVMN6TP TR

M25P10-AVMN6TP TR Datasheet

M25P10-A

Part	Datasheet
M25P10-AVMN6TP TR	M25P10-AVMN6TP TR (pdf)

Related Parts	Information
M25P10-AVMN6P	M25P10-AVMN6P
M25P10-AVMN3TP/X TR	M25P10-AVMN3TP/X TR
M25P10-AVMP6TG TR	M25P10-AVMP6TG TR
M25P10-AVMN3P/X	M25P10-AVMN3P/X
M25P10-AVMP6T TR	M25P10-AVMP6T TR

PDF Datasheet Preview
M25P10-A 1 Mbit, serial Flash memory, 50 MHz SPI bus interface - 1 Mbit of Flash memory - Page Program up to 256 bytes in ms typical - Sector Erase 256 Kbit in s typical - Bulk Erase 1 Mbit in s typical - to V single supply voltage - SPI bus compatible serial interface - 50 MHz Clock rate maximum - Deep Power-down mode 1 uA typical - Electronic signatures JEDEC standard two-byte signature 2011h RES instruction, one-byte signature 10h , for backward compatibility - More than 20 years’ data retention - Packages SO8 MN 150 mil width VFQFPN8 MP MLP8 UFDFPN8 MB 2 x 3 mm December 2008 1/51 Contents Contents M25P10-A Description 6 Signal descriptions 8 Serial Data output Q 8 Serial Data input D 8 Serial Clock C 8 Chip Select S 8 Hold 8 Write Protect W 8 SPI modes 9 Operating features 11 Page Programming Sector Erase and Bulk Erase Polling during a Write, Program or Erase cycle Active Power, Standby Power and Deep Power-down modes Status Register 12 Protection modes 12 Hold condition 13 Memory organization 15 Instructions 16 Write Enable WREN 17 Write Disable WRDI 18 Read Identification RDID 19 Read Status Register RDSR 20 WIP bit 20 WEL bit 20 BP1, BP0 bits 20 SRWD bit 20 Write Status Register WRSR 22 2/51 4/51 M25P10-A List of figures List of figures Figure Logic diagram 6 Figure SO, VFQFPN and UFDFPN8 connections 7 Figure Bus master and memory devices on the SPI bus 9 Figure SPI modes supported 10 Figure Hold condition activation. 14 Figure Block diagram 15 Figure Write Enable WREN instruction sequence. 17 Figure Write Disable WRDI instruction sequence 18 Figure Read Identification RDID instruction sequence and data-out sequence 19 Figure Read Status Register RDSR instruction sequence and data-out sequence 21 Figure Write Status Register WRSR instruction sequence 23 Figure Read Data Bytes READ instruction sequence and data-out sequence 24 Figure Read Data Bytes at Higher Speed FAST_READ instruction sequence and data-out sequence 25 Figure Page Program PP instruction sequence 27 Figure Sector Erase SE instruction sequence. 28 Figure Bulk Erase BE instruction sequence 29 Figure Deep Power-down DP instruction sequence 30 Figure Release from Deep Power-down and Read Electronic Signature RES instruction sequence and data-out sequence 32 Figure Release from Deep Power-down RES instruction sequence 32 Figure Power-up timing 34 Figure AC measurement I/O waveform 36 Figure Serial input timing 43 Figure Write Protect Setup and Hold timing during WRSR when SRWD=1 43 Figure Hold timing 44 Figure Output timing 44 Figure SO8 narrow 8-lead plastic small outline, 150 mils body width, package outline 45 Figure VFQFPN8 MLP8 8-lead very thin fine pitch quad flat package no lead, package outline. 46 Figure UFDFPN8 MLP8 8-lead ultra thin fine pitch dual flat package no lead, 2 x 3 mm package outline47 5/51 M25P10-A The M25P10-A is a 1 Mbit 128 Kbit x 8 serial Flash memory, with advanced write protection mechanisms, accessed by a high speed SPI-compatible bus. The memory can be programmed 1 to 256 bytes at a time, using the Page Program instruction. The memory is organized as 4 sectors, each containing 128 pages. Each page is 256 bytes wide. Thus, the whole memory can be viewed as consisting of 512 pages, or 131,072 bytes. The whole memory can be erased using the Bulk Erase instruction, or a sector at a time, using the Sector Erase instruction. Figure Logic diagram VCC HOLD Logic_Diagram_M25P Table Signal names Signal name Function C D Q S W HOLD VCC VSS Serial Clock Serial Data input Serial Data output Chip Select Write Protect Hold Supply voltage Ground Input Output Input Direction 6/51 M25P10-A Figure SO, VFQFPN and UFDFPN8 connections S1 Q2 W3 VSS 4 8 VCC 7 HOLD 6C 5D Pin_Connections_M25P There is an exposed die paddle on the underside of the MLP8 packages. This is pulled, internally, to VSS, and must not be allowed to be connected to any other voltage or signal line on the PCB. See Package mechanical section for package dimensions, and how to identify pin-1. 7/51 Signal descriptions Signal descriptions M25P10-A Serial Data output Q This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock C . Serial Data input D This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data to be programmed. Values are latched on the rising edge of Serial Clock C . Serial Clock C Table Ordering information scheme Example: M25P10-A Device type M25P Device function 10-A = 1 Mbit 128 Kbit x 8 Operating voltage V = Vcc = to V for /X parts V = Vcc = to V for /Y parts Package MN = SO8 150 mil width MP = VFQFPN8 MLP8 MB = UFDFPN8 MLP8 Device grade 6 = Industrial temperature range, to 85 °C. Device tested with standard test flow 3 1 = Device tested with high reliability certified flow 2 . Automotive temperature range to 125 °C Option blank = Standard packing T = Tape & reel packing Plating technology blank = Standard SnPb plating P or G = RoHS compliant Process 3 /X = T7Y /Y = T7Y redesigned 4 V MN 6 T P /X Device grade 3 available in an SO8 RoHS compliant package. Numonyx strongly recommends the use of the Automotive Grade devices for use in an automotive environment. The High Reliability Certified Flow HRCF is described in the quality note QNEE9801. Please ask your nearest Numonyx Sales Office for a copy. The process letter /X is specified in the ordering information of grade 3 devices only. For grade 6 devices, the process letter does not appear in the ordering information, it only appears on the device package marking and on the shipment box. Please contact your nearest Numonyx Sales Office. For more information on how to identify products by the process identification letter, please refer to AN1995 Serial Flash memory device marking. Only available for grade 6 devices. For a list of available options speed, package, etc. or for further information on any aspect of this device, please contact your nearest Numonyx Sales Office. 48/51 M25P10-A Changes 25-Feb-2001 Document written. VFQFPN8 package MLP8 added. Clarification of descriptions of 12-Sep-2002 entering Standby Power mode from Deep Power-down mode, and of terminating an instruction sequence or data-out sequence. Typical Page Program time improved. Write Protect setup and hold times specified, for applications that switch Write Protect to exit the Hardware 13-Dec-2002 Protection mode immediately before a WRSR, and to enter the Hardware Protection mode again immediately after. 21-Feb-2003 Erroneous address ranges corrected in memory organization table. 24-Nov-2003 Table of contents, warning about exposed paddle on MLP8, and Pb-free options added. 40 MHz AC characteristics table included as well as 25 MHz. ICC3 max , tSE typ and tBE typ values improved. Change of naming for VDFPN8 package. 08-Mar-2005 Devices with Process technology Code X added Read Identification RDID and Table 20 AC characteristics 50 MHz operation, device grade 6 added. SO8 narrow package specifications updated. Notes 1 and 2 removed from Table 24 Ordering information scheme. Note 1 to Table 9 Absolute maximum ratings changed, note 2 removed and TLEAD values removed. Small text changes. End timing line of tSHQZ modified in Figure 25 Output timing. 01-Apr-2005 Read Identification RDID , Deep Power-down DP and Release from Deep Power-down and Read Electronic Signature RES instructions, and Active Power, Standby Power and Deep Power-down modes paragraph clarified. Updated Page Program PP instructions in Page Programming, Page 01-Aug-2005 Program PP and Table 16 Instruction times device grade 14-Apr-2006 All packages are RoHS compliant. Grade 3 information added see Table 10, Table 11, Table 15, Table 17, Table 18 and Table Figure 3 Bus master and memory devices on the SPI bus modified and Note 2 added. Table 11 Data retention and endurance added. 40MHz frequency condition modified for ICC3 in Table 14 DC characteristics device grade Table 14 DC characteristics device grade 6 shows preliminary data. MLP package renamed as VFQFPN and specifications updated see silhouette on first page, Figure 27 and Table Note 2 added below Figure 26 and Note 2 added below Figure VWI parameter for device grade 3 added to Table 8 Power-up timing and VWI threshold. /X Process added to Table 24 Ordering information scheme. 49/51 M25P10-A Changes 05-Jun-2006 tRES1 and tRES2 parameter timings changed for devices produced with the “X” process technology in Table 18 and Table SO8 narrow package specifications updated see Figure 26 and Table 06-Jul-2007 Changed the minimum value for supply voltage. Added TLEAD and changed maximum value for VIO in Table 9 Absolute maximum ratings. Updated Section 3 SPI modes and modified Figure 3 Bus master and memory devices on the SPI bus. Note 1 to Table 13 Capacitance changed. Note 2 below Table 16 Instruction times device grade 6 added. Changed test condition for ICC3 in Table 14 and fR in Table Removed “low voltage” from the title. Small text changes. 23-Aug-2007 Typical values for Sector Erase and Bulk Erase modified. UFDFPN8 package MLP8 added. Added the reference to a new process technology code “Y” . Added notes below Table 10 Operating conditions, Table 15 DC characteristics device grade 3 , and Table 17 Instruction times device grade /Y process added to Table 24 Ordering information scheme. 18-Oct-2007 Code of the UFDFPN8 package modified. 10 Small text changes. 10-Dec-2007 11 Applied Numonyx branding. 15-Dec-2008 Added the following to Operating Voltage section of Table Ordering information scheme 12 V = Vcc = to V for /X parts V = Vcc = to V for /Y parts 50/51 M25P10-A Please Read Carefully INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. Numonyx may make changes to specifications and product descriptions at any time, without notice. Numonyx, B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Numonyx reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by visiting Numonyx's website at Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright 2008, Numonyx, B.V., All Rights Reserved. 51/51

PDF Datasheet Preview

M25P10-A
1 Mbit, serial Flash memory, 50 MHz SPI bus interface
- 1 Mbit of Flash memory - Page Program up to 256 bytes in ms
typical - Sector Erase 256 Kbit in s typical - Bulk Erase 1 Mbit in s typical - to V single supply voltage - SPI bus compatible serial interface - 50 MHz Clock rate maximum - Deep Power-down mode 1 uA typical - Electronic signatures

JEDEC standard two-byte signature 2011h

RES instruction, one-byte signature 10h , for backward compatibility
- More than 20 years’ data retention - Packages

SO8 MN 150 mil width

VFQFPN8 MP MLP8

UFDFPN8 MB 2 x 3 mm

December 2008
1/51

Contents

Contents

M25P10-A

Description 6

Signal descriptions 8

Serial Data output Q 8

Serial Data input D 8

Serial Clock C 8

Chip Select S 8

Hold 8

Write Protect W 8

SPI modes 9

Operating features 11

Page Programming

Sector Erase and Bulk Erase

Polling during a Write, Program or Erase cycle

Active Power, Standby Power and Deep Power-down modes

Status Register 12

Protection modes 12

Hold condition 13

Memory organization 15

Instructions 16

Write Enable WREN 17

Write Disable WRDI 18

Read Identification RDID 19

Read Status Register RDSR 20

WIP bit 20 WEL bit 20 BP1, BP0 bits 20 SRWD bit 20

Write Status Register WRSR 22
2/51
4/51

M25P10-A

List of figures

List of figures

Figure Logic diagram 6 Figure SO, VFQFPN and UFDFPN8 connections 7 Figure Bus master and memory devices on the SPI bus 9 Figure SPI modes supported 10 Figure Hold condition activation. 14 Figure Block diagram 15 Figure Write Enable WREN instruction sequence. 17 Figure Write Disable WRDI instruction sequence 18 Figure Read Identification RDID instruction sequence and data-out sequence 19 Figure Read Status Register RDSR instruction sequence and data-out sequence 21 Figure Write Status Register WRSR instruction sequence 23 Figure Read Data Bytes READ instruction sequence and data-out sequence 24 Figure Read Data Bytes at Higher Speed FAST_READ instruction sequence
and data-out sequence 25 Figure Page Program PP instruction sequence 27 Figure Sector Erase SE instruction sequence. 28 Figure Bulk Erase BE instruction sequence 29 Figure Deep Power-down DP instruction sequence 30 Figure Release from Deep Power-down and Read Electronic Signature RES instruction
sequence and data-out sequence 32 Figure Release from Deep Power-down RES instruction sequence 32 Figure Power-up timing 34 Figure AC measurement I/O waveform 36 Figure Serial input timing 43 Figure Write Protect Setup and Hold timing during WRSR when SRWD=1 43 Figure Hold timing 44 Figure Output timing 44 Figure SO8 narrow 8-lead plastic small outline, 150 mils body width, package outline 45 Figure VFQFPN8 MLP8 8-lead very thin fine pitch quad flat package no lead,
package outline. 46 Figure UFDFPN8 MLP8 8-lead ultra thin fine pitch dual flat package no lead, 2 x 3 mm package outline47
5/51

M25P10-A

The M25P10-A is a 1 Mbit 128 Kbit x 8 serial Flash memory, with advanced write protection mechanisms, accessed by a high speed SPI-compatible bus.

The memory can be programmed 1 to 256 bytes at a time, using the Page Program instruction.

The memory is organized as 4 sectors, each containing 128 pages. Each page is 256 bytes wide. Thus, the whole memory can be viewed as consisting of 512 pages, or 131,072 bytes.

The whole memory can be erased using the Bulk Erase instruction, or a sector at a time, using the Sector Erase instruction.

Figure Logic diagram VCC

HOLD

Logic_Diagram_M25P

Table Signal names

Signal name

Function

C D Q S W HOLD VCC VSS

Serial Clock Serial Data input Serial Data output Chip Select Write Protect Hold Supply voltage Ground

Input Output Input

Direction
6/51

M25P10-A

Figure SO, VFQFPN and UFDFPN8 connections

S1 Q2 W3 VSS 4
8 VCC 7 HOLD 6C 5D

Pin_Connections_M25P

There is an exposed die paddle on the underside of the MLP8 packages. This is pulled, internally, to VSS, and must not be allowed to be connected to any other voltage or signal line on the PCB.

See Package mechanical section for package dimensions, and how to identify pin-1.
7/51

Signal descriptions

Signal descriptions

M25P10-A

Serial Data output Q

This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock C .

Serial Data input D

This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data to be programmed. Values are latched on the rising edge of Serial Clock C .

Serial Clock C
Table Ordering information scheme

Example:

M25P10-A

Device type M25P

Device function 10-A = 1 Mbit 128 Kbit x 8

Operating voltage V = Vcc = to V for /X parts V = Vcc = to V for /Y parts

Package MN = SO8 150 mil width MP = VFQFPN8 MLP8 MB = UFDFPN8 MLP8

Device grade 6 = Industrial temperature range, to 85 °C. Device tested with standard test flow 3 1 = Device tested with high reliability certified flow 2 .

Automotive temperature range to 125 °C

Option blank = Standard packing T = Tape & reel packing

Plating technology blank = Standard SnPb plating P or G = RoHS compliant

Process 3 /X = T7Y /Y = T7Y redesigned 4

V MN 6 T P /X

Device grade 3 available in an SO8 RoHS compliant package.

Numonyx strongly recommends the use of the Automotive Grade devices for use in an automotive environment. The High Reliability Certified Flow HRCF is described in the quality note QNEE9801. Please ask your nearest Numonyx Sales Office for a copy.
The process letter /X is specified in the ordering information of grade 3 devices only. For grade 6 devices, the process letter does not appear in the ordering information, it only appears on the device package marking and on the shipment box. Please contact your nearest Numonyx Sales Office. For more information on how to identify products by the process identification letter, please refer to AN1995 Serial Flash memory device marking.

Only available for grade 6 devices.

For a list of available options speed, package, etc. or for further information on any aspect of this device, please contact your nearest Numonyx Sales Office.
48/51

M25P10-A

Changes
25-Feb-2001 Document written.

VFQFPN8 package MLP8 added. Clarification of descriptions of 12-Sep-2002 entering Standby Power mode from Deep Power-down mode, and of
terminating an instruction sequence or data-out sequence.

Typical Page Program time improved. Write Protect setup and hold times specified, for applications that switch Write Protect to exit the Hardware 13-Dec-2002 Protection mode immediately before a WRSR, and to enter the Hardware Protection mode again immediately after.
21-Feb-2003 Erroneous address ranges corrected in memory organization table.
24-Nov-2003

Table of contents, warning about exposed paddle on MLP8, and Pb-free options added.
40 MHz AC characteristics table included as well as 25 MHz. ICC3 max , tSE typ and tBE typ values improved. Change of naming for VDFPN8 package.
08-Mar-2005

Devices with Process technology Code X added Read Identification RDID and Table 20 AC characteristics 50 MHz operation, device grade 6 added.

SO8 narrow package specifications updated.
Notes 1 and 2 removed from Table 24 Ordering information scheme. Note 1 to Table 9 Absolute maximum ratings changed, note 2 removed and TLEAD values removed. Small text changes. End timing line of tSHQZ modified in Figure 25 Output timing.
01-Apr-2005

Read Identification RDID , Deep Power-down DP and Release from Deep Power-down and Read Electronic Signature RES instructions, and Active Power, Standby Power and Deep Power-down modes paragraph clarified.

Updated Page Program PP instructions in Page Programming, Page 01-Aug-2005 Program PP and Table 16 Instruction times device grade
14-Apr-2006

All packages are RoHS compliant. Grade 3 information added see Table 10, Table 11, Table 15, Table 17, Table 18 and Table

Figure 3 Bus master and memory devices on the SPI bus modified and

Note 2 added.

Table 11 Data retention and endurance added.
40MHz frequency condition modified for ICC3 in Table 14 DC
characteristics device grade

Table 14 DC characteristics device grade 6 shows preliminary data.

MLP package renamed as VFQFPN and specifications updated see
silhouette on first page, Figure 27 and Table Note 2 added below

Figure 26 and Note 2 added below Figure VWI parameter for device grade 3 added to Table 8 Power-up timing and VWI threshold.
/X Process added to Table 24 Ordering information scheme.
49/51

M25P10-A

Changes
05-Jun-2006
tRES1 and tRES2 parameter timings changed for devices produced with
the “X” process technology in Table 18 and Table

SO8 narrow package specifications updated see Figure 26 and

Table
06-Jul-2007

Changed the minimum value for supply voltage.

Added TLEAD and changed maximum value for VIO in Table 9 Absolute maximum ratings.

Updated Section 3 SPI modes and modified Figure 3 Bus master and
memory devices on the SPI bus.

Note 1 to Table 13 Capacitance changed.

Note 2 below Table 16 Instruction times device grade 6 added.

Changed test condition for ICC3 in Table 14 and fR in Table

Removed “low voltage” from the title. Small text changes.
23-Aug-2007

Typical values for Sector Erase and Bulk Erase modified.

UFDFPN8 package MLP8 added.

Added the reference to a new process technology code “Y” .

Added notes below Table 10 Operating conditions, Table 15 DC
characteristics device grade 3 , and Table 17 Instruction times device
grade
/Y process added to Table 24 Ordering information scheme.
18-Oct-2007

Code of the UFDFPN8 package modified. 10

Small text changes.
10-Dec-2007 11 Applied Numonyx branding.
15-Dec-2008
Added the following to Operating Voltage section of Table Ordering information scheme 12 V = Vcc = to V for /X parts

V = Vcc = to V for /Y parts
50/51

M25P10-A

Please Read Carefully INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY

WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.

Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications.

Numonyx may make changes to specifications and product descriptions at any time, without notice. Numonyx, B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied,
by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Numonyx reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by
visiting Numonyx's website at Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries.
*Other names and brands may be claimed as the property of others. Copyright 2008, Numonyx, B.V., All Rights Reserved.
51/51

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Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived M25P10-AVMN6TPTR Datasheet file may be downloaded here without warranties.

Datasheet ID: M25P10-AVMN6TPTR 648279