PC28F512P30EFB

PC28F512P30EFB Datasheet

JS28F512P30BFx, JS28F512P30EFx, JS28F512P30TFx, PC28F512P30BFx, PC28F512P30EFx, PC28F512P30TFx JS28F00AP30BFx, JS28F00AP30TFx, JS28F00AP30EFx, PC28F00AP30BFx, PC28F00AP30TFx, PC28F00AP30EFx, RC28F00AP30BFx, RC28F00AP30TFx, PC28F00BP30EFx

Part	Datasheet
PC28F512P30EFB	PC28F512P30EFB (pdf)

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512Mb, 1Gb, 2Gb P30-65nm Features Micron Parallel NOR Flash Embedded Memory P30-65nm JS28F512P30BFx, JS28F512P30EFx, JS28F512P30TFx, PC28F512P30BFx, PC28F512P30EFx, PC28F512P30TFx JS28F00AP30BFx, JS28F00AP30TFx, JS28F00AP30EFx, PC28F00AP30BFx, PC28F00AP30TFx, PC28F00AP30EFx, RC28F00AP30BFx, RC28F00AP30TFx, PC28F00BP30EFx • High performance • Easy BGA package features 100ns initial access for 512Mb, 1Gb Easy BGA 105ns initial access for 2Gb Easy BGA 25ns 16-word asychronous page read mode 52 MHz Easy BGA with zero WAIT states and 17ns clock-to-data output synchronous burst read mode 4-, 8-, 16-, and continuous word options for burst mode • TSOP package features 110ns initial access for 512Mb, 1Gb TSOP • Both Easy BGA and TSOP package features Buffered enhanced factory programming BEFP at 2 MB/s TYP using a 512-word buffer 1.8V buffered programming at MB/s TYP using a 512-word buffer • Architecture MLC highest density at lowest cost Symmetrically blocked architecture 512Mb, 1Gb, 2Gb Asymmetrically blocked architecture 512Mb, 1Gb four 32KB parameter blocks top or bottom configuration 128KB main blocks Blank check to verify an erased block • Voltage and power VCC core voltage VCCQ I/O voltage Standy current 70µA TYP for 512Mb 75µA TYP for 1Gb 52 MHz continuous synchronous read current 21mA TYP , 24mA MAX • Security One-time programmable register 64 OTP bits, programmed with unique information from Micron 2112 OTP bits available for customer programming Absolute write protection VPP = VSS Power-transition erase/program lockout Individual zero-latency block locking Individual block lock-down Password access • Software 25us TYP program suspend 25us TYP erase suspend Flash Data Integrator optimized Basic command set and extended function Interface EFI command set compatible Common flash interface • Density and Packaging 56-lead TSOP package 512Mb, 1Gb 64-ball Easy BGA package 512Mb, 1Gb, 2Gb 16-bit wide data bus • Quality and reliabilty JESD47 compliant Operating temperature to +85°C Minimum 100,000 ERASE cycles per block 65nm process technology Micron Technology, Inc. reserves the right to change products or specifications without notice. 2013 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 512Mb, 1Gb, 2Gb P30-65nm Features Discrete and MCP Part Numbering Information Devices are shipped from the factory with memory content bits erased to For available options, such as packages or for further information, contact your Micron sales representative. Part numbers can be verified at Feature and specification comparison by device type is available at Contact the factory for devices not found. Note Not all part numbers listed here are available for ordering. Table 1 Discrete Part Number Information Package Part Number Category Product Line Density Product Family Parameter Location Lithography Features Category Details JS = 56-lead TSOP, lead free PC = 64-ball Easy BGA, lead-free RC = 64-ball Easy BGA, leaded 28F = Micron Flash memory 512 = 512Mb 00A = 1Gb 00B = 2Gb P30 VCC = VCCQ = B/T = Bottom/Top parameter E = Symmetrical Blocks F = 65nm * Note The last digit is assigned randomly to cover packaging media, features, or other specific configuration information. Sample part number JS28F512P30EF* Table 2 Standard Part Numbers Density 512Mb Configuration Bottom boot Top boot Uniform Bottom boot Top boot Uniform Medium Tray Tape & Reel Tray Tape & Reel Tray Tape & Reel Tray Tape & Reel Tray Tape & Reel Tray Tape & Reel Tray Tape & Reel JS JS28F512P30BFA JS28F512P30TFA JS28F512P30EFA JS28F00AP30BFA JS28F00AP30BTFA JS28F00AP30EFA PC PC28F512P30BFA PC28F512P30BFB PC28F512P30TFA PC28F512P30TFB PC28F512P30EFA PC28F00AP30BFA PC28F00AP30BFB PC28F00AP30TFA PC28F00AP30EFA PC28F00BP30EFA RC RC28F00AP30BFA RC28F00AP30TFA Micron Technology, Inc. reserves the right to change products or specifications without notice. 2013 Micron Technology, Inc. All rights reserved. 512Mb, 1Gb, 2Gb P30-65nm Features Contents General Description 7 Virtual Chip Enable Description 8 Memory Map 9 Package Dimensions 11 Pinouts and Ballouts 13 Signal Descriptions 15 Bus Operations 17 Read 17 Write 17 Output Disable 17 Standby 17 Reset 18 Device Command Codes 19 Device Command Bus Cycles 22 Read Operations 24 Asynchronous Single Word Read 24 Asynchronous Page Mode Read Easy BGA Only 24 Synchronous Burst Mode Read Easy BGA Only 25 Read CFI 25 Read Device ID 25 Device ID Codes 26 Program Operations 27 Word Programming 40h 27 Buffered Programming E8h, D0h 27 Buffered Enhanced Factory Programming 80h, D0h 28 Program Suspend 30 Program Resume 31 Program Protection 31 Erase Operations 32 BLOCK ERASE Command 32 BLANK CHECK Command 32 ERASE SUSPEND Command 33 ERASE RESUME Command 33 Erase Protection 33 Security Operations 34 Block Locking 34 BLOCK LOCK Command 34 BLOCK UNLOCK Command 34 BLOCK LOCK DOWN Command 34 Block Lock Status 34 Block Locking During Suspend 35 Selectable OTP Blocks 36 Password Access 36 Status Register 37 Read Status Register 37 Clear Status Register 38 Configuration Register 39 Read Configuration Register 39 Read Mode 39 Latency Count 40 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2013 Micron Technology, Inc. All rights reserved. 512Mb, 1Gb, 2Gb P30-65nm Features Micron Technology, Inc. reserves the right to change products or specifications without notice. 2013 Micron Technology, Inc. All rights reserved. 512Mb, 1Gb, 2Gb P30-65nm Features List of Figures Table 1 Discrete Part Number Information 2 Table 2 Standard Part Numbers 2 Table 3 Virtual Chip Enable Truth Table for Easy BGA Packages 8 Table 4 TSOP and Easy BGA Signal Descriptions 15 Table 5 Bus Operations 17 Table 6 Command Codes and Definitions 19 Table 7 Command Bus Cycles 22 Table 8 Device ID Information 25 Table 9 Device ID codes 26 Table 10 BEFP Requirements 29 Table 11 BEFP Considerations 29 Table 12 Status Register Description 37 Table 13 Read Configuration Register 39 Table 14 End of Wordline Data and WAIT State Comparison 42 Table 15 WAIT Functionality Table 42 Table 16 Burst Sequence Word Ordering 43 Table 17 Example of CFI Output x16 device as a Function of Device and Mode 48 Table 18 CFI Database Addresses and Sections 49 Table 19 CFI ID String 49 Table 20 System Interface Information 50 Table 21 Device Geometry 51 Table 22 Block Region Map Information 51 Table 23 Primary Vendor-Specific Extended Query 52 Table 24 Optional Features Field 54 Table 25 One Time Programmable OTP Space Information 54 Table 26 Burst Read Information 55 Table 27 Partition and Block Erase Region Information 56 Table 28 Partition Region 1 Information Top and Bottom Offset/Address 57 Table 29 Partition Region 1 Information 57 Table 30 Partition Region 1 Partition and Erase Block Map Information 60 Table 31 CFI Link Information 2Gb 61 Table 32 Power and Reset 71 Table 33 Maximum Ratings 73 Table 34 Operating Conditions 73 Table 35 DC Current Characteristics 74 Table 36 DC Voltage Characteristics 75 Table 37 Test Configuration Worst-Case Speed Condition 76 Table 38 Capacitance 77 Table 39 AC Read Specifications 78 Table 40 AC Write Specifications 85 Table 41 Program and Erase Specifications 91 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2013 Micron Technology, Inc. All rights reserved. 512Mb, 1Gb, 2Gb P30-65nm General Description The Micron Parallel NOR Flash memory is the latest generation of Flash memory devices. Benefits include more density in less space, high-speed interface device, and support for code and data storage. Features include high-performance synchronous-burst read mode, fast asynchronous access times, low power, flexible security options, and three industry-standard package choices. The product family is manufactured using Micron 65nm process technology. The NOR Flash device provides high performance at low voltage on a 16-bit data bus. Individually erasable memory blocks are sized for optimum code and data storage. Upon initial power up or return from reset, the device defaults to asynchronous pagemode read. Configuring the read configuration register enables synchronous burstmode reads. In synchronous burst mode, output data is synchronized with a user-supplied clock signal. A WAIT signal provides easy CPU-to-flash memory synchronization. In addition to the enhanced architecture and interface, the device incorporates technology that enables fast factory PROGRAM and ERASE operations. Designed for low-voltage systems, the devIce supports READ operations with VCC at the low voltages, and ERASE and PROGRAM operations with VPP at the low voltages or VPPH. Buffered enhanced factory programming BEFP provides the fastest Flash array programming performance with VPP at VPPH, which increases factory throughput. With V PP at low voltages, VCC and VPP can be tied together for a simple, ultra low-power design. In addition to voltage flexibility, a dedicated VPP connection provides complete data protection when VPP VPPLK. A command user interface is the interface between the system processor and all internal operations of the device. The device automatically executes the algorithms and timings necessary for block erase and program. A status register indicates ERASE or PROGRAM completion and any errors that may have occurred. An industry-standard command sequence invokes program and erase automation. Each ERASE operation erases one block. The erase suspend feature enables system software to pause an ERASE cycle to read or program data in another block. Program suspend enables system software to pause programming to read other locations. Data is programmed in word increments 16 bits . The protection register enables unique device identification that can be used to increase system security. The individual block lock feature provides zero-latency block locking and unlocking. The device includes enhanced protection via password access this new feature supports write and/or read access protection of user-defined blocks. In addition, the device also provides the full-device OTP security feature. Micron Technology, Inc. reserves the right to change products or specifications without notice. 2013 Micron Technology, Inc. All rights reserved. 512Mb, 1Gb, 2Gb P30-65nm Virtual Chip Enable Description Virtual Chip Enable Description The 2Gb device employs a virtual chip enable feature, which combines two 1Gb die with a common chip enable, CE# for Easy BGA packages. The maximum address bit is then used to select between the die pair with CE# asserted. When CE# is asserted and the maximum address bit is LOW, the lower parameter die is selected when CE# is asserted and the maximum address bit is HIGH, the upper parameter die is selected. Table 3 Virtual Chip Enable Truth Table for Easy BGA Packages Die Selected Lower parameter die Upper parameter die A[MAX] L H Figure 1 Easy BGA Block Diagram Easy BGA Dual Die Top/Bottom Parameter Configuration CE# WP# OE# WE# CLK ADV# A[MAX:1] Top Parameter Die Bottom Parameter Die RST# VCC VPP VCCQ VSS DQ[15:0] WAIT Micron Technology, Inc. reserves the right to change products or specifications without notice. 2013 Micron Technology, Inc. All rights reserved. Memory Map Figure 2 Memory Map 512Mb and 1Gb 512Mb, 1Gb, 2Gb P30-65nm Memory Map 3FF0000 - 64 KWord Block 1026 A[25:1] 512Mb and A[26:1] 1Gb 3FF0000 - 64 KWord Block 1023 1FF0000 - 64 KWord Block 514 1FF0000 - 64 KWord Block 511 FF0000 - 64 KWord Block 258 020000 - 02FFFF 010000 - 01FFFF 00C000 - 00FFFF 008000 - 00BFFF 004000 - 007FFF - 003FFF Table 16 Burst Sequence Word Ordering Start Address DEC 0 1 2 3 4 5 6 7 14 15 0 1 2 3 Burst Wrap RCR3 4-Word Burst BL[2:0] = 0b001 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3 1-2-3-4 2-3-4-5 3-4-5-6 Burst Addressing Sequence DEC 8-Word Burst BL[2:0] = 0b010 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-8 2-3-4-5-6-7-8-9 3-4-5-6-7-8-9-10 16-Word Burst BL[2:0] = 0b011 Continuous Burst BL[2:0] = 0b111 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2013 Micron Technology, Inc. All rights reserved. 512Mb, 1Gb, 2Gb P30-65nm Configuration Register Table 16 Burst Sequence Word Ordering Continued Start Address DEC 4 5 6 7 14 15 Burst Wrap RCR3 4-Word Burst BL[2:0] = 0b001 Burst Addressing Sequence DEC 8-Word Burst BL[2:0] = 0b010 4-5-6-7-8-9-10-11 5-6-7-8-9-10-11-12 6-7-8-9-10-11-12-13 7-8-9-10-11-12-13-14 16-Word Burst BL[2:0] = 0b011 Continuous Burst BL[2:0] = 0b111 Clock Edge The clock edge CE bit selects either a rising default or falling clock edge for CLK. This clock edge is used at the start of a burst cycle to output synchronous data and to assert/de-assert WAIT. Burst Wrap The burst wrap BW bit determines whether 4-word, 8-word, or 16-word burst length accesses wrap within the selected word length boundaries or cross word length boundaries. When BW is set, burst wrapping does not occur default . When BW is cleared, burst wrapping occurs. When performing synchronous burst reads with BW set no wrap , an output delay may occur when the burst sequence crosses its first device row 16-word boundary. If the burst sequence’s start address is 4-word aligned, then no delay occurs. If the start address is at the end of a 4-word boundary, the worst-case output delay is one clock cycle less than the first access latency count. This delay can take place only once and doesn’t occur if the burst sequence does not cross a device row boundary. WAIT informs the system of this delay when it occurs. Burst Length The burst length bits BL[2:0] select the linear burst length for all synchronous burst reads of the flash memory array. The burst lengths are 4-word, 8-word, 16-word, or continuous. Continuous burst accesses are linear only and do not wrap within any word length boundaries. When a burst cycle begins, the device outputs synchronous burst data until it reaches the end of the “burstable” address space. Micron Technology, Inc. reserves the right to change products or specifications without notice. 2013 Micron Technology, Inc. All rights reserved. 512Mb, 1Gb, 2Gb P30-65nm One-Time Programmable Registers One-Time Programmable Registers Read OTP Registers The device contains 17 OTP registers that can be used to implement system security measures and/or device identification. Each OTP register can be individually locked. The first 128-bit OTP register is comprised of two 64-bit 8-word segments. The lower 64-bit segment is preprogrammed at the Micron factory with a unique 64-bit number. The upper 64-bit segment, as well as the other sixteen 128-bit OTP registers, are blank. Users can program them as needed. Once programmed, users can also lock the OTP register s to prevent additional bit programming see the OTP Register Map figure below . The OTP registers contain OTP bits when programmed, PR bits cannot be erased. Each OTP register can be accessed multiple times to program individual bits, as long as the register remains unlocked. Each OTP register has an associated lock register bit. When a lock register bit is programmed, the associated OTP register can only be read it can no longer be programmed. Additionally, because the lock register bits themselves are OTP, when programmed, they cannot be erased. Therefore, when an OTP register is locked, it cannot be unlocked. The OTP registers can be read from an OTP-RA address. To read the OTP register, a READ DEVICE IDENTIFIER command is issued at an OTP-RA address to place the device in the read device identifier state. Next, a READ operation is performed using the address offset corresponding to the register to be read. The Device Identifier Information table shows the address offsets of the OTP registers and lock registers. PR data is read 16 bits at a time. Micron Technology, Inc. reserves the right to change products or specifications without notice. 2013 Micron Technology, Inc. All rights reserved. Figure 13 OTP Register Map 0x109 128-bit OTP Register 16 0x102 512Mb, 1Gb, 2Gb P30-65nm One-Time Programmable Registers User Programmable 0x91 128-bit OTP Register 1 User Programmable 0x8A Lock Register 1 0x89 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 128-bit OTP Register 0 0x88 0x85 0x84 64-bit Segment User Programmable 64-bit Segment Factory Programed • Initial Micron brand release 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel 208-368-4000 Sales inquiries 800-932-4992 Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization some- times occur. Micron Technology, Inc. reserves the right to change products or specifications without notice. 2013 Micron Technology, Inc. All rights reserved.

PDF Datasheet Preview

512Mb, 1Gb, 2Gb P30-65nm Features

Micron Parallel NOR Flash Embedded Memory P30-65nm

JS28F512P30BFx, JS28F512P30EFx, JS28F512P30TFx, PC28F512P30BFx, PC28F512P30EFx, PC28F512P30TFx JS28F00AP30BFx, JS28F00AP30TFx, JS28F00AP30EFx, PC28F00AP30BFx, PC28F00AP30TFx, PC28F00AP30EFx, RC28F00AP30BFx, RC28F00AP30TFx, PC28F00BP30EFx
• High performance
• Easy BGA package features
100ns initial access for 512Mb, 1Gb Easy BGA 105ns initial access for 2Gb Easy BGA 25ns 16-word asychronous page read mode 52 MHz Easy BGA with zero WAIT states and
17ns clock-to-data output synchronous burst read mode 4-, 8-, 16-, and continuous word options for burst mode
• TSOP package features 110ns initial access for 512Mb, 1Gb TSOP
• Both Easy BGA and TSOP package features Buffered enhanced factory programming BEFP at 2 MB/s TYP using a 512-word buffer 1.8V buffered programming at MB/s TYP using a 512-word buffer
• Architecture MLC highest density at lowest cost Symmetrically blocked architecture 512Mb, 1Gb, 2Gb Asymmetrically blocked architecture 512Mb, 1Gb four 32KB parameter blocks top or bottom configuration 128KB main blocks Blank check to verify an erased block
• Voltage and power VCC core voltage VCCQ I/O voltage Standy current 70µA TYP for 512Mb 75µA TYP for 1Gb 52 MHz continuous synchronous read current 21mA TYP , 24mA MAX
• Security One-time programmable register 64 OTP bits, programmed with unique information from Micron 2112 OTP bits available for customer programming Absolute write protection VPP = VSS Power-transition erase/program lockout Individual zero-latency block locking Individual block lock-down Password access
• Software 25us TYP program suspend 25us TYP erase suspend Flash Data Integrator optimized Basic command set and extended function Interface EFI command set compatible Common flash interface
• Density and Packaging 56-lead TSOP package 512Mb, 1Gb 64-ball Easy BGA package 512Mb, 1Gb, 2Gb 16-bit wide data bus
• Quality and reliabilty JESD47 compliant Operating temperature to +85°C Minimum 100,000 ERASE cycles per block 65nm process technology

Micron Technology, Inc. reserves the right to change products or specifications without notice. 2013 Micron Technology, Inc. All rights reserved.

Products and specifications discussed herein are subject to change by Micron without notice.
512Mb, 1Gb, 2Gb P30-65nm Features

Discrete and MCP Part Numbering Information

Devices are shipped from the factory with memory content bits erased to For available options, such as packages or for further information, contact your Micron sales representative. Part numbers can be verified at Feature and specification comparison by device type is available at Contact the factory for devices not found.
Note Not all part numbers listed here are available for ordering.

Table 1 Discrete Part Number Information

Package

Part Number Category

Product Line Density

Product Family Parameter Location

Lithography Features

Category Details JS = 56-lead TSOP, lead free PC = 64-ball Easy BGA, lead-free RC = 64-ball Easy BGA, leaded 28F = Micron Flash memory 512 = 512Mb 00A = 1Gb 00B = 2Gb P30 VCC = VCCQ = B/T = Bottom/Top parameter E = Symmetrical Blocks F = 65nm *

Note The last digit is assigned randomly to cover packaging media, features, or other specific configuration information. Sample part number JS28F512P30EF*

Table 2 Standard Part Numbers

Density 512Mb

Configuration Bottom boot Top boot Uniform Bottom boot Top boot Uniform

Medium Tray

Tape & Reel Tray

Tape & Reel Tray

Tape & Reel Tray

Tape & Reel Tray

Tape & Reel Tray

Tape & Reel Tray

Tape & Reel

JS JS28F512P30BFA

JS28F512P30TFA

JS28F512P30EFA

JS28F00AP30BFA

JS28F00AP30BTFA

JS28F00AP30EFA

PC PC28F512P30BFA PC28F512P30BFB PC28F512P30TFA PC28F512P30TFB PC28F512P30EFA

PC28F00AP30BFA PC28F00AP30BFB PC28F00AP30TFA

PC28F00AP30EFA

PC28F00BP30EFA

RC RC28F00AP30BFA RC28F00AP30TFA

Micron Technology, Inc. reserves the right to change products or specifications without notice. 2013 Micron Technology, Inc. All rights reserved.
512Mb, 1Gb, 2Gb P30-65nm Features

Contents

General Description 7 Virtual Chip Enable Description 8 Memory Map 9 Package Dimensions 11 Pinouts and Ballouts 13 Signal Descriptions 15 Bus Operations 17

Read 17 Write 17 Output Disable 17 Standby 17 Reset 18 Device Command Codes 19 Device Command Bus Cycles 22 Read Operations 24 Asynchronous Single Word Read 24 Asynchronous Page Mode Read Easy BGA Only 24 Synchronous Burst Mode Read Easy BGA Only 25 Read CFI 25 Read Device ID 25 Device ID Codes 26 Program Operations 27 Word Programming 40h 27 Buffered Programming E8h, D0h 27 Buffered Enhanced Factory Programming 80h, D0h 28 Program Suspend 30 Program Resume 31 Program Protection 31 Erase Operations 32 BLOCK ERASE Command 32 BLANK CHECK Command 32 ERASE SUSPEND Command 33 ERASE RESUME Command 33 Erase Protection 33 Security Operations 34 Block Locking 34 BLOCK LOCK Command 34 BLOCK UNLOCK Command 34 BLOCK LOCK DOWN Command 34 Block Lock Status 34 Block Locking During Suspend 35 Selectable OTP Blocks 36 Password Access 36 Status Register 37 Read Status Register 37 Clear Status Register 38 Configuration Register 39 Read Configuration Register 39 Read Mode 39 Latency Count 40

Micron Technology, Inc. reserves the right to change products or specifications without notice. 2013 Micron Technology, Inc. All rights reserved.
512Mb, 1Gb, 2Gb P30-65nm Features

Micron Technology, Inc. reserves the right to change products or specifications without notice. 2013 Micron Technology, Inc. All rights reserved.
512Mb, 1Gb, 2Gb P30-65nm Features

List of Figures
Table 1 Discrete Part Number Information 2 Table 2 Standard Part Numbers 2 Table 3 Virtual Chip Enable Truth Table for Easy BGA Packages 8 Table 4 TSOP and Easy BGA Signal Descriptions 15 Table 5 Bus Operations 17 Table 6 Command Codes and Definitions 19 Table 7 Command Bus Cycles 22 Table 8 Device ID Information 25 Table 9 Device ID codes 26 Table 10 BEFP Requirements 29 Table 11 BEFP Considerations 29 Table 12 Status Register Description 37 Table 13 Read Configuration Register 39 Table 14 End of Wordline Data and WAIT State Comparison 42 Table 15 WAIT Functionality Table 42 Table 16 Burst Sequence Word Ordering 43 Table 17 Example of CFI Output x16 device as a Function of Device and Mode 48 Table 18 CFI Database Addresses and Sections 49 Table 19 CFI ID String 49 Table 20 System Interface Information 50 Table 21 Device Geometry 51 Table 22 Block Region Map Information 51 Table 23 Primary Vendor-Specific Extended Query 52 Table 24 Optional Features Field 54 Table 25 One Time Programmable OTP Space Information 54 Table 26 Burst Read Information 55 Table 27 Partition and Block Erase Region Information 56 Table 28 Partition Region 1 Information Top and Bottom Offset/Address 57 Table 29 Partition Region 1 Information 57 Table 30 Partition Region 1 Partition and Erase Block Map Information 60 Table 31 CFI Link Information 2Gb 61 Table 32 Power and Reset 71 Table 33 Maximum Ratings 73 Table 34 Operating Conditions 73 Table 35 DC Current Characteristics 74 Table 36 DC Voltage Characteristics 75 Table 37 Test Configuration Worst-Case Speed Condition 76 Table 38 Capacitance 77 Table 39 AC Read Specifications 78 Table 40 AC Write Specifications 85 Table 41 Program and Erase Specifications 91

Micron Technology, Inc. reserves the right to change products or specifications without notice. 2013 Micron Technology, Inc. All rights reserved.
512Mb, 1Gb, 2Gb P30-65nm General Description

The Micron Parallel NOR Flash memory is the latest generation of Flash memory devices. Benefits include more density in less space, high-speed interface device, and support for code and data storage. Features include high-performance synchronous-burst read mode, fast asynchronous access times, low power, flexible security options, and three industry-standard package choices. The product family is manufactured using Micron 65nm process technology.

The NOR Flash device provides high performance at low voltage on a 16-bit data bus. Individually erasable memory blocks are sized for optimum code and data storage.

Upon initial power up or return from reset, the device defaults to asynchronous pagemode read. Configuring the read configuration register enables synchronous burstmode reads. In synchronous burst mode, output data is synchronized with a user-supplied clock signal. A WAIT signal provides easy CPU-to-flash memory synchronization.

In addition to the enhanced architecture and interface, the device incorporates technology that enables fast factory PROGRAM and ERASE operations. Designed for low-voltage systems, the devIce supports READ operations with VCC at the low voltages, and ERASE and PROGRAM operations with VPP at the low voltages or VPPH. Buffered enhanced factory programming BEFP provides the fastest Flash array programming performance with VPP at VPPH, which increases factory throughput. With V PP at low voltages, VCC and VPP can be tied together for a simple, ultra low-power design. In addition to voltage flexibility, a dedicated VPP connection provides complete data protection when VPP VPPLK.

A command user interface is the interface between the system processor and all internal operations of the device. The device automatically executes the algorithms and timings necessary for block erase and program. A status register indicates ERASE or PROGRAM completion and any errors that may have occurred.

An industry-standard command sequence invokes program and erase automation. Each ERASE operation erases one block. The erase suspend feature enables system software to pause an ERASE cycle to read or program data in another block. Program suspend enables system software to pause programming to read other locations. Data is programmed in word increments 16 bits .

The protection register enables unique device identification that can be used to increase system security. The individual block lock feature provides zero-latency block locking and unlocking. The device includes enhanced protection via password access this new feature supports write and/or read access protection of user-defined blocks. In addition, the device also provides the full-device OTP security feature.

Micron Technology, Inc. reserves the right to change products or specifications without notice. 2013 Micron Technology, Inc. All rights reserved.
512Mb, 1Gb, 2Gb P30-65nm Virtual Chip Enable Description

Virtual Chip Enable Description

The 2Gb device employs a virtual chip enable feature, which combines two 1Gb die with a common chip enable, CE# for Easy BGA packages. The maximum address bit is then used to select between the die pair with CE# asserted. When CE# is asserted and the maximum address bit is LOW, the lower parameter die is selected when CE# is asserted and the maximum address bit is HIGH, the upper parameter die is selected.

Table 3 Virtual Chip Enable Truth Table for Easy BGA Packages

Die Selected

Lower parameter die

Upper parameter die

A[MAX] L H

Figure 1 Easy BGA Block Diagram

Easy BGA Dual Die Top/Bottom Parameter Configuration

CE# WP# OE# WE# CLK ADV#

A[MAX:1]

Top Parameter Die Bottom Parameter Die

RST# VCC VPP VCCQ VSS DQ[15:0]

WAIT

Micron Technology, Inc. reserves the right to change products or specifications without notice. 2013 Micron Technology, Inc. All rights reserved.

Memory Map

Figure 2 Memory Map 512Mb and 1Gb
512Mb, 1Gb, 2Gb P30-65nm Memory Map
3FF0000 -
64 KWord Block 1026

A[25:1] 512Mb and A[26:1] 1Gb 3FF0000 -
64 KWord Block 1023
1FF0000 -
64 KWord Block 514
1FF0000 -
64 KWord Block 511

FF0000 -
64 KWord Block 258
020000 - 02FFFF 010000 - 01FFFF 00C000 - 00FFFF 008000 - 00BFFF 004000 - 007FFF - 003FFF
Table 16 Burst Sequence Word Ordering

Start Address

DEC 0 1 2 3 4 5 6 7
14 15
0 1 2 3

Burst Wrap RCR3
4-Word Burst BL[2:0] = 0b001 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2
0-1-2-3 1-2-3-4 2-3-4-5 3-4-5-6

Burst Addressing Sequence DEC
8-Word Burst BL[2:0] = 0b010
0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6
0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-8 2-3-4-5-6-7-8-9 3-4-5-6-7-8-9-10
16-Word Burst BL[2:0] = 0b011

Continuous Burst BL[2:0] = 0b111

Micron Technology, Inc. reserves the right to change products or specifications without notice. 2013 Micron Technology, Inc. All rights reserved.
512Mb, 1Gb, 2Gb P30-65nm Configuration Register
Table 16 Burst Sequence Word Ordering Continued

Start Address

DEC 4 5 6 7
14 15

Burst Wrap RCR3
4-Word Burst BL[2:0] = 0b001

Burst Addressing Sequence DEC
8-Word Burst BL[2:0] = 0b010 4-5-6-7-8-9-10-11 5-6-7-8-9-10-11-12 6-7-8-9-10-11-12-13 7-8-9-10-11-12-13-14
16-Word Burst BL[2:0] = 0b011

Continuous Burst BL[2:0] = 0b111

Clock Edge

The clock edge CE bit selects either a rising default or falling clock edge for CLK. This clock edge is used at the start of a burst cycle to output synchronous data and to assert/de-assert WAIT.

Burst Wrap

The burst wrap BW bit determines whether 4-word, 8-word, or 16-word burst length accesses wrap within the selected word length boundaries or cross word length boundaries. When BW is set, burst wrapping does not occur default . When BW is cleared, burst wrapping occurs.

When performing synchronous burst reads with BW set no wrap , an output delay may occur when the burst sequence crosses its first device row 16-word boundary. If the burst sequence’s start address is 4-word aligned, then no delay occurs. If the start address is at the end of a 4-word boundary, the worst-case output delay is one clock cycle less than the first access latency count. This delay can take place only once and doesn’t occur if the burst sequence does not cross a device row boundary. WAIT informs the system of this delay when it occurs.

Burst Length

The burst length bits BL[2:0] select the linear burst length for all synchronous burst reads of the flash memory array. The burst lengths are 4-word, 8-word, 16-word, or continuous.

Continuous burst accesses are linear only and do not wrap within any word length boundaries. When a burst cycle begins, the device outputs synchronous burst data until it reaches the end of the “burstable” address space.

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512Mb, 1Gb, 2Gb P30-65nm One-Time Programmable Registers

One-Time Programmable Registers

Read OTP Registers

The device contains 17 OTP registers that can be used to implement system security measures and/or device identification. Each OTP register can be individually locked.

The first 128-bit OTP register is comprised of two 64-bit 8-word segments. The lower 64-bit segment is preprogrammed at the Micron factory with a unique 64-bit number. The upper 64-bit segment, as well as the other sixteen 128-bit OTP registers, are blank. Users can program them as needed. Once programmed, users can also lock the OTP register s to prevent additional bit programming see the OTP Register Map figure below .

The OTP registers contain OTP bits when programmed, PR bits cannot be erased. Each OTP register can be accessed multiple times to program individual bits, as long as the register remains unlocked.

Each OTP register has an associated lock register bit. When a lock register bit is programmed, the associated OTP register can only be read it can no longer be programmed. Additionally, because the lock register bits themselves are OTP, when programmed, they cannot be erased. Therefore, when an OTP register is locked, it cannot be unlocked.

The OTP registers can be read from an OTP-RA address. To read the OTP register, a READ DEVICE IDENTIFIER command is issued at an OTP-RA address to place the device in the read device identifier state. Next, a READ operation is performed using the address offset corresponding to the register to be read. The Device Identifier Information table shows the address offsets of the OTP registers and lock registers. PR data is read 16 bits at a time.

Micron Technology, Inc. reserves the right to change products or specifications without notice. 2013 Micron Technology, Inc. All rights reserved.

Figure 13 OTP Register Map
0x109 128-bit OTP Register 16
0x102
512Mb, 1Gb, 2Gb P30-65nm One-Time Programmable Registers

User Programmable
0x91 128-bit OTP Register 1

User Programmable
0x8A Lock Register 1
0x89 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
128-bit OTP Register 0
0x88 0x85 0x84
64-bit Segment User Programmable
64-bit Segment Factory Programed
• Initial Micron brand release
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This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization some-
times occur.

Micron Technology, Inc. reserves the right to change products or specifications without notice. 2013 Micron Technology, Inc. All rights reserved.

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Datasheet ID: PC28F512P30EFB 648276