PC28F128J3F75A

PC28F128J3F75A Datasheet

PC2 8 F 3 2 0 J 3 F 7 5 *

Part	Datasheet
PC28F128J3F75A	PC28F128J3F75A (pdf)

Related Parts	Information
JS28F640J3F75A	JS28F640J3F75A

PDF Datasheet Preview
Embedded Flash Memory J3 65 nm Single Bit per Cell SBC 32, 64, and 128 Mbit Datasheet Product Features - Architecture Symmetrical 128-KB blocks 128 Mbit 128 blocks 64 Mbit 64 blocks 32 Mbit 32 blocks Blank Check to verify an erased block - Performance Initial Access Speed 75ns 25 ns 8-word Asynchronous page-mode reads 256-Word write buffer for x16 mode, 256Byte write buffer for x8 mode µs per Byte Effective programming time - System Voltage VCC = V to V VCCQ = V to V - Packaging 56-Lead TSOP 64-Ball Easy BGA package - Security Enhanced security options for code protection Absolute protection with VPEN = Vss Individual block locking Block erase/program lockout during power transitions Password Access feature One-Time Programmable Register 64 OTP bits, programmed with unique information by Numonyx 64 OTP bits, available for customer programming - Software Program and erase suspend support Flash Data Integrator FDI Common Flash Interface CFI Compatible Scalable Command Set - Quality and Reliability Operating temperature -40 °C to +85 °C 100K Minimum erase cycles per block 65 nm Flash Technology JESD47E Compliant 208032-03 Jan 2011 Micron Technology, Inc., reserves the right to change products or specifications without notice. 2010 Micron Technology, Inc. All rights reserved. Legal Lines and Disclaime rs8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel 208-368-3900 Customer Comment Line 800-932-4992 Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. Datasheet 2 Jan 2011 208032-03 Embedded Flash Memory J3 65 nm Single Bit per Cell SBC Contents Introduction 6 Nomenclature 6 7 Conventions 7 Functional Overview 9 Block Diagram 11 Memory 12 Package Information 13 56-Lead TSOP Package for 32-, 64-, 128-Mbit 13 64-Ball Easy BGA Package for 32-, 64-, 128-Mbit 14 Ballouts/Pinouts and Signal Descriptions 16 Easy BGA Ballout for 32-, 64-, 128-Mbit 16 56-Lead TSOP Package Pinout for 32-, 64-,128-Mbit 17 Signal Descriptions 18 Maximum Ratings and Operating 19 Absolute Maximum Ratings 19 Operating Conditions 19 Power-Up/Down 19 Power-Up/Down 19 Power Supply Decoupling 20 Electrical Characteristics 21 DC Current Specifications 21 DC Voltage 22 AC Characteristics 23 Read 24 Program, Erase, Block-Lock Specifications 28 Reset 28 AC Test Conditions 29 Bus 30 Bus Reads 31 Asynchronous Page Mode Read 31 Output 32 Bus 32 Standby 33 Reset/Power-Down 33 Device 33 B Ordering Datasheet 4 Jan 2011 208032-03 Embedded Flash Memory J3 65 nm Single Bit per Cell SBC Date May 2009 March 2010 Jan 2011 Initial release Add Blank Check function and command. Add Blank Check specification tBC/MB, update Clear Block Lock-Bits Max Time and Program time in Table 13, “Configuration Performance” on page Update ICCR in Table 7, “DC Current Characteristics” on page Order information with device features digit. Update part number information in Valid Combination table. Add a note to clarify the SR output after E8 command in Figure 16, “Write to Buffer Flowchart” on page State JESD47E Compliant at front page. Update ECR.13 description in Table 18, “Enhanced Configuration Register” on page Correct the typo of comment for offset 24h at CFI from 2048µs to 1024µs. Correct the typo of tAVQV and tELQV to Max Specifications. Emphasize the valid and legal command usage at Section “Device Command Codes” on page Put a link for part numbers after Table 46, “Valid Combinations” on page Add Buffer Program Time for 128 Words 256 Bytes at Table 13, “Configuration Performance” on page Add JEDEC standard lead width for TSOP56 package at Table 1, “56-Lead TSOP Dimension Table” on page Jan 2011 208032-03 Datasheet 5 Embedded Flash Memory J3 65 nm Single Bit per Cell SBC Introduction This document contains information pertaining to the Embedded Flash Memory J3 65 nm Single Bit per Cell SBC device features, operation, and specifications. Unless otherwise indicated throughout the rest of this document, the Embedded Flash Memory J3 65 nm Single Bit per Cell SBC device is referred to as J3 65 nm SBC. The J3 65 nm SBC device provides improved mainstream performance with enhanced security features, taking advantage of the high quality and reliability of the NOR-based 65 nm technology. Offered in 128-Mbit, 64-Mbit, and 32-Mbit densities, the J3 65 nm SBC device brings reliable, low-voltage capability 3 V read, program, and erase with high speed, low-power operation. The J3 65 nm SBC device takes advantage of proven manufacturing experience and is ideal for code and data applications where high density and low cost are required, such as in networking, telecommunications, digital set top boxes, audio recording, and digital imaging. Numonyx Flash Memory components also deliver a new generation of forward-compatible software support. By using the Common Flash Interface CFI and Scalable Command Set SCS , customers can take advantage of density upgrades and optimized write capabilities of future Numonyx Flash Memory devices. Nomenclature J3 65 nm SBC Embedded Flash Memory J3 65 nm Single Bit per Cell SBC AMIN AMAX All Densities All Densities 32 Mbit 64 Mbit 128 Mbit AMIN = A0 for x8 AMIN = A1 for x16 AMAX = A21 AMAX = A22 AMAX = A23 Block A group of flash cells that share common erase circuitry and erase simultaneously. Clear Indicates a logic zero 0 Program Writes data to the flash array Indicates a logic one 1 VPEN Refers to a signal or package connection name VPEN Appendix B Ordering Information Figure 25 Decoder for 32-, 64-, 128-Mbit PC2 8 F 3 2 0 J 3 F 7 5 * Package JS = Pb-Free 56-TSOP RC = 64-Ball Easy BGA PC = 64-Ball Pb-Free Easy BGA Product Line Designator Flash Memory Device Density 128 = 128-Mbit 640 = 64-Mbit 320 = 32-Mbit Device Features * Access Speed 75ns Lithography F = 65nm Voltage VCC/VPEN 3 = 3 V/3 V Product Family J = Embedded Flash Memory Note: The last digit is randomly assigned to cover packing media and/or features or other specific configuration. Table 46 Valid Combinations 32-Mbit JS28F320J3F75* RC28F320J3F75* PC28F320J3F75* 64-Mbit JS28F640J3F75* RC28F640J3F75* PC28F640J3F75* 128-Mbit JS28F128J3F75* RC28F128J3F75* PC28F128J3F75* Note: For further information on ordering products or for product part numbers, go Jan 2011 208032-03 Datasheet 65 Embedded Flash Memory J3 65 nm Single Bit per Cell SBC 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel 208-368-3900 Customer Comment Line 800-932-4992 Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. Datasheet 66 Jan 2011 208032 Micron Technology, Inc., reserves the right to change products or specifications without notice. 2010 Micron Technology, Inc. All rights reserved.

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Embedded Flash Memory J3 65 nm Single Bit per Cell SBC
32, 64, and 128 Mbit

Datasheet

Product Features
- Architecture Symmetrical 128-KB blocks 128 Mbit 128 blocks 64 Mbit 64 blocks 32 Mbit 32 blocks Blank Check to verify an erased block
- Performance Initial Access Speed 75ns 25 ns 8-word Asynchronous page-mode reads 256-Word write buffer for x16 mode, 256Byte write buffer for x8 mode µs per Byte Effective programming time
- System Voltage VCC = V to V VCCQ = V to V
- Packaging 56-Lead TSOP 64-Ball Easy BGA package
- Security

Enhanced security options for code protection

Absolute protection with VPEN = Vss Individual block locking

Block erase/program lockout during power transitions

Password Access feature

One-Time Programmable Register 64 OTP bits, programmed with unique information by Numonyx 64 OTP bits, available for customer programming
- Software

Program and erase suspend support Flash Data Integrator FDI

Common Flash Interface CFI Compatible

Scalable Command Set
- Quality and Reliability

Operating temperature -40 °C to +85 °C
100K Minimum erase cycles per block
65 nm Flash Technology

JESD47E Compliant
208032-03 Jan 2011

Micron Technology, Inc., reserves the right to change products or specifications without notice. 2010 Micron Technology, Inc. All rights reserved.

Legal Lines and Disclaime
rs8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel 208-368-3900 Customer Comment Line 800-932-4992 Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners.

This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.

Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.

Datasheet 2

Jan 2011 208032-03

Embedded Flash Memory J3 65 nm Single Bit per Cell SBC

Contents

Introduction 6 Nomenclature 6 7 Conventions 7

Functional Overview 9 Block Diagram 11 Memory 12

Package Information 13 56-Lead TSOP Package for 32-, 64-, 128-Mbit 13 64-Ball Easy BGA Package for 32-, 64-, 128-Mbit 14

Ballouts/Pinouts and Signal Descriptions 16 Easy BGA Ballout for 32-, 64-, 128-Mbit 16 56-Lead TSOP Package Pinout for 32-, 64-,128-Mbit 17 Signal Descriptions 18

Maximum Ratings and Operating 19 Absolute Maximum Ratings 19 Operating Conditions 19 Power-Up/Down 19 Power-Up/Down 19 Power Supply Decoupling 20

Electrical Characteristics 21 DC Current Specifications 21 DC Voltage 22

AC Characteristics 23 Read 24 Program, Erase, Block-Lock Specifications 28 Reset 28 AC Test Conditions 29

Bus 30 Bus Reads 31 Asynchronous Page Mode Read 31 Output 32 Bus 32 Standby 33 Reset/Power-Down 33 Device 33
B Ordering

Datasheet 4

Jan 2011 208032-03

Embedded Flash Memory J3 65 nm Single Bit per Cell SBC

Date May 2009 March 2010

Jan 2011

Initial release

Add Blank Check function and command.

Add Blank Check specification tBC/MB, update Clear Block Lock-Bits Max Time and Program time in Table 13, “Configuration Performance” on page

Update ICCR in Table 7, “DC Current Characteristics” on page Order information with device features digit.

Update part number information in Valid Combination table.

Add a note to clarify the SR output after E8 command in Figure 16, “Write to Buffer Flowchart” on page

State JESD47E Compliant at front page.

Update ECR.13 description in Table 18, “Enhanced Configuration Register” on page

Correct the typo of comment for offset 24h at CFI from 2048µs to 1024µs.

Correct the typo of tAVQV and tELQV to Max Specifications. Emphasize the valid and legal command usage at Section “Device Command Codes” on page

Put a link for part numbers after Table 46, “Valid Combinations” on page

Add Buffer Program Time for 128 Words 256 Bytes at Table 13, “Configuration Performance” on page

Add JEDEC standard lead width for TSOP56 package at Table 1, “56-Lead TSOP Dimension Table” on page

Jan 2011 208032-03

Datasheet 5

Embedded Flash Memory J3 65 nm Single Bit per Cell SBC

Introduction

This document contains information pertaining to the Embedded Flash Memory J3 65 nm Single Bit per Cell SBC device features, operation, and specifications.

Unless otherwise indicated throughout the rest of this document, the Embedded Flash Memory J3 65 nm Single Bit per Cell SBC device is referred to as J3 65 nm SBC.

The J3 65 nm SBC device provides improved mainstream performance with enhanced security features, taking advantage of the high quality and reliability of the NOR-based 65 nm technology. Offered in 128-Mbit, 64-Mbit, and 32-Mbit densities, the J3 65 nm SBC device brings reliable, low-voltage capability 3 V read, program, and erase with high speed, low-power operation. The J3 65 nm SBC device takes advantage of proven manufacturing experience and is ideal for code and data applications where high density and low cost are required, such as in networking, telecommunications, digital set top boxes, audio recording, and digital imaging. Numonyx Flash Memory components also deliver a new generation of forward-compatible software support. By using the Common Flash Interface CFI and Scalable Command Set SCS , customers can take advantage of density upgrades and optimized write capabilities of future Numonyx Flash Memory devices.

Nomenclature

J3 65 nm SBC Embedded Flash Memory J3 65 nm Single Bit per Cell SBC

AMIN AMAX

All Densities All Densities 32 Mbit 64 Mbit 128 Mbit

AMIN = A0 for x8 AMIN = A1 for x16 AMAX = A21 AMAX = A22 AMAX = A23

Block

A group of flash cells that share common erase circuitry and erase simultaneously.

Clear

Indicates a logic zero 0

Program

Writes data to the flash array

Indicates a logic one 1

VPEN

Refers to a signal or package connection name

VPEN
Appendix B Ordering Information

Figure 25 Decoder for 32-, 64-, 128-Mbit

PC2 8 F 3 2 0 J 3 F 7 5 *

Package

JS = Pb-Free 56-TSOP RC = 64-Ball Easy BGA PC = 64-Ball Pb-Free Easy BGA

Product Line Designator

Flash Memory

Device Density
128 = 128-Mbit 640 = 64-Mbit 320 = 32-Mbit

Device Features *

Access Speed
75ns

Lithography F = 65nm

Voltage VCC/VPEN 3 = 3 V/3 V

Product Family J = Embedded

Flash Memory

Note:

The last digit is randomly assigned to cover packing media and/or features or other specific configuration.

Table 46 Valid Combinations
32-Mbit JS28F320J3F75* RC28F320J3F75* PC28F320J3F75*
64-Mbit JS28F640J3F75* RC28F640J3F75* PC28F640J3F75*
128-Mbit JS28F128J3F75* RC28F128J3F75* PC28F128J3F75*

Note:
For further information on ordering products or for product part numbers, go

Jan 2011 208032-03

Datasheet 65

Embedded Flash Memory J3 65 nm Single Bit per Cell SBC
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel 208-368-3900 Customer Comment Line 800-932-4992

Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners.

This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.

Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.

Datasheet 66

Jan 2011 208032

Micron Technology, Inc., reserves the right to change products or specifications without notice. 2010 Micron Technology, Inc. All rights reserved.

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived PC28F128J3F75A Datasheet file may be downloaded here without warranties.

Datasheet ID: PC28F128J3F75A 648275