TE28F160B3TD70A

TE28F160B3TD70A Datasheet

TE28F016B3TA90 3 TE28F016B3BA90 3 TE28F016B3TA110 3 TE28F016B3BA110 3 TE28F008B3TA90 3 TE28F008B3BA90 3 TE28F008B3TA110 3 TE28F008B3BA110 3

Part	Datasheet
TE28F160B3TD70A	TE28F160B3TD70A (pdf)

Related Parts	Information
GT28F320B3TA100	GT28F320B3TA100
TE28F160B3BD70A	TE28F160B3BD70A
GT28F320B3TA110	GT28F320B3TA110
GT28F320B3BA100	GT28F320B3BA100

PDF Datasheet Preview
3-Volt Advanced Boot Block Flash Memory 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 Datasheet Product Features • Flexible SmartVoltage Technology V Read/Program/Erase 12 V VPP Fast Production Programming • V or V I/O Option Reduces Overall System Power • High Performance V 70 ns Max Access Time • Optimized Block Sizes Eight 8-KB Blocks for Data,Top or Bottom Locations Up to One Hundred Twenty-Seven 64KB Blocks for Code • Block Locking VCC-Level Control through WP# • Low Power Consumption 9 mA Typical Read Current • Absolute Hardware-Protection VPP = GND Option VCC Lockout Voltage • Extended Temperature Operation °C to +85 °C • Automated Program and Block Erase Status Registers • Flash Data Integrator Software Flash Memory Manager System Interrupt Manager Supports Parameter Storage, Streaming Data e.g., Voice • Extended Cycling Capability Minimum 100,000 Block Erase Cycles Guaranteed • Automatic Power Savings Feature Typical ICCS after Bus Inactivity • Standard Surface Mount Packaging 48-Ball CSP Packages 40- and 48-Lead TSOP Packages • Density and Footprint Upgradeable for common package 8-, 16-, 32- and 64-Mbit Densities • ETOX VIII µm Flash Technology 16 and 32-Mbit Densities • ETOX VII µm Flash Technology 16-, 32- and 64-Mbit Densities • ETOX VI 0.25µm Flash Technology 8-, 16-, and 32-Mbit Densities • The x8 option not recommended for new Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800548-4725 or by visiting Intel's website at Copyright Intel Corporation Other names and brands may be claimed as the property of others. 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 Contents Introduction Product Overview Product Description Package Pinouts Block Organization Parameter Blocks Main Blocks Principles of Operation Bus Operation Read Output Standby Deep Power-Down / Write Modes of Read Array Read Identifier Read Status Register Clearing the Status Register Program Suspending and Resuming Program Erase Mode Suspending and Resuming Erase Block Locking WP# = VIL for Block Locking WP# = VIH for Block Unlocking VPP Program and Erase Voltages VPP = VIL for Complete Protection Power Consumption Active Power Automatic Power Savings APS Standby Power Deep Power-Down Mode Power and Reset Power-Up/Down Characteristics RP# Connected to System VCC, VPP and RP# Transitions Power Supply Decoupling Electrical Absolute Maximum Operating Capacitance DC Characteristics AC Characteristics 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 AC Characteristics Operations 32 Program and Erase Timings 36 Reset Operations 38 Ordering Information 39 Additional Information 41 Appendix A Write State Machine Current/Next States 42 Appendix B Architecture Block 43 Appendix C Word-Wide Memory Map 44 Appendix D Byte-Wide Memory Map Diagrams 50 Appendix E Program and Erase Flowcharts 53 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 Number -001 -002 -003 -004 -005 -006 -007 Original version Section VPP Program and Erase Voltages, added Updated Figure 9 Automated Block Erase Flowchart Updated Figure 10 Erase Suspend/Resume Flowchart added program to table Updated Figure 16 AC Waveform Program and Erase Operations updated notes IPPR maximum specification change from ±25 µA to ±50 µA Program and Erase Suspend Latency specification change Updated Appendix A Ordering Information included 8 M and 4 M information Updated Figure, Appendix D Architecture Block Diagram Block info. in words not bytes Minor wording changes Combined byte-wide specification previously 290605 with this document Improved speed specification to 80 ns V and 90 ns V Improved V I/O option to minimum V Section Improved several DC characteristics Section Improved several AC characteristics Sections and Combined V and V DC characteristics Section Added 5 V VPP read specification Section Removed 120 ns and 150 ns speed offerings Moved Ordering Information from Appendix to Section updated information Moved Additional Information from Appendix to Section Updated figure Appendix B, Access Time vs. Capacitive Load Updated figure Appendix C, Architecture Block Diagram Moved Program and Erase Flowcharts to Appendix E Updated Program Flowchart Updated Program Suspend/Resume Flowchart Minor text edits throughout Added 32-Mbit density Added 98H as a reserved command Table 4 = 0 when in read identifier mode Section Status register clarification for SR3 Table 7 VCC and VCCQ absolute maximum specification = V Section Combined IPPW and ICCW into one specification Section Combined IPPE and ICCE into one specification Section Max Parameter Block Erase Time tWHQV2/tEHQV2 reduced to 4 sec Section Max Main Block Erase Time tWHQV3/tEHQV3 reduced to 5 sec Section Erase suspend time 12 V tWHRH2/tEHRH2 changed to 5 µs typical and 20 µs maximum Section Ordering Information updated Section Write State Machine Current/Next States Table updated Appendix A Program Suspend/Resume Flowchart updated Appendix F Erase Suspend/Resume Flowchart updated Appendix F Text clarifications throughout µBGA package diagrams corrected Figures 3 and 4 IPPD test conditions corrected Section 32-Mbit ordering information corrected Section 6 µBGA package top side mark information added Section 6 VIH and VILSpecification change Section ICCS test conditions clarification Section Added Command Sequence Error Note Table 7 Data sheet renamed from Smart 3 Advanced Boot Block 4-Mbit, 8-Mbit, 16-Mbit Flash Memory Family. Added device ID information for 4-Mbit x8 device Removed 32-Mbit x8 to reflect product offerings Minor text changes Corrected RP# pin description in Table 2, 3 Volt Advanced Boot Block Pin Descriptions Corrected typographical error fixed in Ordering Information 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 Number -008 -009 -010 -011 -012 -013 -014 -015 -016 4-Mbit packaging and addressing information corrected throughout document Corrected 4-Mbit memory addressing tables in Appendices D and E Max ICCD changed to 25 µA VCCMax on 32 M 28F320B3 changed to V Added 64-Mbit density and faster speed offerings Removed access time vs. capacitance load curve Changed references of 32Mbit 80ns devices to 70ns devices to reflect the faster product offering. Changed VccMax=3.3V reference to indicate the affected product is the 0.25µm 32Mbit device. Minor text edits throughout document. Added New Pin-1 indicator information on 40 and 48Lead TSOP packages. Minor text edits throughout document. Added specifications for micron product offerings throughout document Minor text edits throughout document. 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 Introduction This datasheet contains the specifications for the 3-Volt Advanced Boot Block Flash Memory family, which is optimized for portable, low-power, systems. This family of products features V or V I/Os, and a low VCC/VPP operating range of V for Read, Program, and Erase operations. In addition, this family is capable of fast programming at 12 V. Throughout this document, the term V” refers to the full voltage range V except where noted otherwise and “VPP = 12 V” refers to 12 V Section and provide an overview of the Flash Memory family including applications, pinouts, and pin descriptions. Section describes the memory organization and operation for these products. Sections and contain the operating specifications. Finally, Sections and provide ordering and other reference information. The 3-Volt Advanced Boot Block Flash Memory features the following: • Enhanced blocking for easy segmentation of code and data or additional design flexibility • Program Suspend to Read command • VCCQ input of V or V on all I/Os. See Figures 1 through 4 for pinout diagrams and VCCQ location • Maximum program and erase time specification for improved data storage. Table 3-Volt Advanced Boot Block Feature Summary Feature VCC Read Voltage VCCQ I/O Voltage VPP Program/Erase Voltage Bus Width Speed Memory Arrangement Blocking top or bottom Locking Operating Temperature Program/Erase Cycling Packages 28F008B3, 28F016B3 28F800B3, 28F160B3, 28F320B3 3 , 28F640B3 V or V V or V 8 bit 16 bit 70 ns, 80 ns, 90 ns, 100 ns, 110 ns 1024 Kbit x 8 Mbit , 2048 Kbit x 8 16 Mbit 512 Kbit x 16 8 Mbit , 1024 Kbit x 16 Mbit , 2048 Kbit x 16 32 Mbit , 4096 Kbit x 16 64 Mbit Eight 8-Kbyte parameter blocks and Fifteen 64-Kbyte blocks 8 Mbit or Thirty-one 64-Kbyte main blocks 16 Mbit Sixty-three 64-Kbyte main blocks 32 Mbit One hundred twenty-seven 64-Kbyte main blocks 64 Mbit WP# locks/unlocks parameter blocks All other blocks protected using VPP Extended °C to +85 °C 100,000 cycles 40-lead TSOP 1 , 48-Ball µBGA CSP 2 48-Lead TSOP, 48-Ball µBGA CSP 2 , 48-Ball VF BGA 4 Reference Section Table 3 Section Section Section Appendix C Section Table 8 Section Figure 4, Figure 5 32-Mbit and 64-Mbit densities not available in 40-lead TSOP. 8-Mbit densities not available in µBGA* CSP. VCCMax is V on 0.25µm 32-Mbit devices. 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 Product Overview Intel provides the most flexible voltage solution in the flash industry, providing three discrete voltage supply pins VCC for Read operation, VCCQ for output swing, and VPP for Program and Erase operation. All 3-Volt Advanced Boot Block Flash Memory products provide program/erase capability at V or 12 V for fast production programming , and read with VCC at V. Since many designs read from the flash memory a large percentage of the time, V VCC operation can provide substantial power savings. The 3-Volt Advanced Boot Block Flash Memory products are available in either x8 or x16 packages in the following densities see Section “Ordering Information” on page 39 for availability. • 8-Mbit 8, 388, 608-bit flash memory organized as 512 Kwords of 16 bits each or 1024 Kbytes of 8-bits each • 16-Mbit 16, 777, 216-bit flash memory organized as 1024 Kwords of 16 bits each or 2048 Kbytes of 8-bits each • 32-Mbit 33, 554, 432-bit flash memory organized as 2048 Kwords of 16 bits each • 64-Mbit 67, 108, 864-bit flash memory organized as 4096 Kwords of 16 bits each The parameter blocks are located at either the top denoted by -T suffix or the bottom -B suffix of the address map in order to accommodate different microprocessor protocols for kernel code location. The upper two or lower two parameter blocks can be locked to provide complete code security for system initialization code. Locking and unlocking is controlled by WP# see Section “Block Locking” on page 17 for details . The Command User Interface CUI serves as the interface between the microprocessor or microcontroller and the internal operation of the flash memory. The internal Write State Machine WSM automatically executes the algorithms and timings necessary for Program and Erase operations, including verification, thereby unburdening the microprocessor or microcontroller. The status register indicates the status of the WSM by signifying block erase or word program completion and status. The 3-Volt Advanced Boot Block flash memory is also designed with an Automatic Power Savings APS feature, which minimizes system current drain and allows for very low power designs. This mode is entered following the completion of a read cycle approximately 300 ns later . The RP# pin provides additional protection against unwanted command writes that may occur during system reset and power-up/down sequences due to invalid system bus conditions see Section “Power-Up/Down Operation” on page Section “Principles of Operation” on page 10 gives detailed explanation of the different modes of operation. Section “DC Characteristics” on page 23 provides complete current and voltage specifications. Refer to Section “AC Characteristics Operations” on page 27 for read, program, and erase performance specifications. 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 Product Description This section explains device pin description and package pinouts. Package Pinouts The 3-Volt Advanced Boot Block flash memory is available in 40-lead TSOP x8, Figure 1 , 48-lead TSOP x16, Figure 2 , 48-ball µBGA x8 and x16, Figure 4 and Figure 5, respectively , and 48-ball VF BGA x16, Figure 5 packages. In all figures, pin changes necessary for density upgrades have been circled. Figure 40-Lead TSOP Package for x8 Configurations A16 A15 A14 A13 A12 A11 A9 A8 WE# VPP WP# 37 36 A19 A10 Advanced Boot Block 40-Lead TSOP 10 mm x 20 mm VCCQ 12 13 TOP VIEW 0580_01 40-Lead TSOP available for 8-Mbit and 16-Mbit densities only. Lower densities will have NC on the upper address pins. For example, an 8-Mbit device will have NC on 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 Figure 48-Lead TSOP Package for x16 Configurations 64 M 32 M A8 A21 A20 8 9 10 Advanced Boot Block 48-Lead TSOP 12 mm x 20 mm TOP VIEW VCCQ DQ15 DQ14 Products Affected are Intel Ordering Codes: 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 Ordering Information Valid Combinations 40-Lead TSOP Ext. Temp. 32 Mbit Ext. Temp. 16 Mbit Ext. Temp. 8 Mbit TE28F016B3TA90 3 TE28F016B3BA90 3 TE28F016B3TA110 3 TE28F016B3BA110 3 TE28F008B3TA90 3 TE28F008B3BA90 3 TE28F008B3TA110 3 TE28F008B3BA110 3 48-Lead TSOP TE28F320B3TC70 TE28F320B3BC70 TE28F320B3TC90 TE28F320B3BC90 TE28F320B3TA100 TE28F320B3BA100 TE28F320B3TA110 TE28F320B3BA110 TE28F160B3TC70 TE28F160B3BC70 TE28F160B3TC80 TE28F160B3BC80 TE28F160B3TA90 3 TE28F160B3BA90 3 TE28F160B3TA110 3 TE28F160B3BA110 3 TE28F800B3TA90 3 TE28F800B3BA90 3 TE28F800B3TA110 3 TE28F800B3BA110 3 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 Figure x8 48-Ball µBGA* Chip Size Package Top View, Ball Down VCCQ 0580_04 Shaded connections indicate the upgrade address connections. Lower density devices will not have the upper address solder balls. Routing is not recommended in this area. A20 is the upgrade address for the 16-Mbit device. 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 Figure x16 48-Ball Very Fine Pitch BGA and µBGA* Chip Size Package Top View, Ball Down A10 WE# RP# 64M 32M VCCQ 0580_03 Shaded connections indicate the upgrade address connections. Lower density devices will not have the upper address solder balls. Routing is not recommended in this area. A19 is the upgrade address for the 16-Mbit device. A20 is the upgrade address for the 32-Mbit device. A21 is the upgrade address for the 64-Mbit device. Table 2, “3-Volt Advanced Boot Block Pin Descriptions” on page 9 details the usage of each device pin. 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 Table 3-Volt Advanced Boot Block Pin Descriptions Type Name and Function DQ15 CE# OE# WE# RP# VCCQ VCC GND NC INPUT ADDRESS INPUTS for memory addresses. Addresses are internally latched during a program or erase cycle. 28F008B3 A[0-19], 28F016B3 A[0-20], 28F800B3 A[0-18], 28F160B3 A[0-19], 28F320B3 A[0-20], 28F640B3 A[0-21] INPUT/ OUTPUT DATA INPUTS/OUTPUTS Inputs array data on the second CE# and WE# cycle during a Program command. Inputs commands to the Command User Interface when CE# and WE# are active. Data is internally latched. Outputs array, identifier and status register data. The data pins float to tri-state when the chip is de-selected or the outputs are disabled. INPUT/ OUTPUT DATA INPUTS/OUTPUTS Inputs array data on the second CE# and WE# cycle during a Program command. Data is internally latched. Outputs array and identifier data. The data pins float to tri-state when the chip is de-selected. Not included on x8 products. INPUT CHIP ENABLE Activates the internal control logic, input buffers, decoders and sense amplifiers. CE# is active low. CE# high de-selects the memory device and reduces power consumption to standby levels. INPUT OUTPUT ENABLE Enables the device’s outputs through the data buffers during a Read operation. OE# is active low. INPUT WRITE ENABLE Controls writes to the Command Register and memory array. WE# is active low. Addresses and data are latched on the rising edge of the second WE# pulse. Ordering Information Figure Ordering Information T E2 8 F 3 2 0 B3 T C7 0 Package TE = 48-Lead TSOP GT = 48-Ball µBGA* CSP GE = VF BGA CSP Product line designator for all Flash products Device Density 640 = x16 64 Mbit 320 = x16 32 Mbit 160 = x16 16 Mbit 800 = x16 8 Mbit 016 = x8 16 Mbit 008 = x8 8 Mbit Access Speed ns 70, 80, 90, 100, 110 Lithography Not Present = µm A = µm C = µm D = µm T = Top Blocking B = Bottom Blocking Product Family B3 = 3 Volt Advanced+ Boot Block VCC = V VPP = V or 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 Table Ordering Information Valid Combinations Ext. Temp. 64 Mbit Ext. Temp. 32 Mbit Ext. Temp. 16 Mbit Ext. Temp. 8 Mbit 40-Lead TSOP TE28F016B3TA90 TE28F016B3BA90 TE28F016B3TA110 TE28F016B3BA110 TE28F008B3TA90 TE28F008B3BA90 TE28F008B3TA110 TE28F008B3BA110 48-Lead TSOP TE28F640B3TC80 TE28F640B3BC80 TE28F320B3TC70 TE28F320B3BC70 TE28F320B3TC90 TE28F320B3BC90 TE28F320B3TA100 TE28F320B3BA100 TE28F320B3TA110 TE28F320B3BA110 TE28F160B3TD70 TE28F160B3BD70 TE28F160B3TC70 TE28F160B3BC70 TE28F160B3TC80 TE28F160B3BC80 TE28F160B3TC90 TE28F160B3BC90 TE28F160B3TA90 TE28F160B3BA90 TE28F160B3TA110 TE28F160B3BA110 TE28F800B3TA90 TE28F800B3BA90 TE28F800B3TA110 TE28F800B3BA110 48-Ball µBGA CSP 1,2 48-Ball VF BGA GE28F640B3TC80 GE28F640B3BC80 GE28F320B3TD70 GE28F320B3BD70 GE28F320B3TC70 GE28F320B3BC70 GE28F320B3TC90 GE28F320B3BC90 GT28F160B3TA90 3 GT28F160B3BA90 3 GT28F160B3TA110 3 GT28F160B3BA110 3 GE28F160B3TD70 GE28F160B3BD70 GE28F160B3TC70 GE28F160B3BC70 GE28F160B3TC80 GE28F160B3BC80 GE28F160B3TC90 GE28F160B3BC90 GE28F800B3TA70 GE28F800B3BA70 GE28F008B3TA70 GE28F008B3BA70 GE28F800B3TA90 GE28F800B3BA90 GE28F008B3TA90 GE28F008B3BA90 The 48-ball µBGA package top side mark reads F160B3. This mark is identical for both x8 and x16 products. All product shipping boxes or trays provide the correct information regarding bus architecture. However, once the devices are removed from the shipping media, it may be difficult to differentiate based on the top side mark. The device identifier accessible through the Device ID command see Section for further details enables x8 and x16 µBGA package product differentiation. The second line of the 48-ball µBGA package top side mark specifies assembly codes. For samples only, the first character signifies either “E” for engineering samples or “S” for silicon daisy-chain samples. All other assembly codes without an “E” or “S” as the first character are production units. Intel recommends using µm Advanced Boot Block Products. 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 Additional Information Order Number 297948 292199 292200 Note 2 Contact your Intel Representative 297874 Document/Tool 3 Volt Advanced Boot Block Flash Memory Family Specification Update AP-641 Achieving Low Power with the 3 Volt Advanced Boot Block Flash Memory AP-642 Designing for Upgrade to the 3 Volt Advanced Boot Block Flash Memory 3 Volt Advanced Boot Block Algorithms ‘C’ and assembly Flash Data Integrator IFDI Software Developer’s Kit IFDI Interactive Play with Flash Data Integrator on Your PC NOTES Please call the Intel Literature Center at 800 548-4725 to request Intel documentation. International customers should contact their local Intel or distribution sales office. Visit Intel’s World Wide Web home page at or for technical documentation and tools. For the most current information on Intel Advanced and Advanced+ Boot Block Flash memory, visit our microsite at 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 Appendix A Write State Machine Current/Next States Command Input and Next State Current State SR.7 Data When Read Read Array FFH Program Setup 10/ Erase Setup 20H Erase Confirm Prog/Ers Suspend Prog/Ers Resume

PDF Datasheet Preview

3-Volt Advanced Boot Block Flash Memory
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

Datasheet

Product Features
• Flexible SmartVoltage Technology

V Read/Program/Erase 12 V VPP Fast Production Programming
• V or V I/O Option

Reduces Overall System Power
• High Performance

V 70 ns Max Access Time
• Optimized Block Sizes

Eight 8-KB Blocks for Data,Top or Bottom Locations

Up to One Hundred Twenty-Seven 64KB Blocks for Code
• Block Locking

VCC-Level Control through WP#
• Low Power Consumption
9 mA Typical Read Current
• Absolute Hardware-Protection

VPP = GND Option VCC Lockout Voltage
• Extended Temperature Operation
°C to +85 °C
• Automated Program and Block Erase

Status Registers
• Flash Data Integrator Software

Flash Memory Manager System Interrupt Manager Supports Parameter Storage, Streaming

Data e.g., Voice
• Extended Cycling Capability

Minimum 100,000 Block Erase Cycles Guaranteed
• Automatic Power Savings Feature

Typical ICCS after Bus Inactivity
• Standard Surface Mount Packaging
48-Ball CSP Packages 40- and 48-Lead TSOP Packages
• Density and Footprint Upgradeable for
common package 8-, 16-, 32- and 64-Mbit Densities
• ETOX VIII µm Flash

Technology 16 and 32-Mbit Densities
• ETOX VII µm Flash Technology
16-, 32- and 64-Mbit Densities
• ETOX VI 0.25µm Flash Technology
8-, 16-, and 32-Mbit Densities
• The x8 option not recommended for new
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800548-4725 or by visiting Intel's website at

Copyright Intel Corporation
*Other names and brands may be claimed as the property of others.
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

Contents

Introduction

Product Overview

Product Description

Package Pinouts Block Organization

Parameter Blocks Main Blocks

Principles of Operation

Bus Operation Read Output Standby Deep Power-Down / Write

Modes of Read Array Read Identifier Read Status Register Clearing the Status Register Program Suspending and Resuming Program Erase Mode Suspending and Resuming Erase

Block Locking WP# = VIL for Block Locking WP# = VIH for Block Unlocking

VPP Program and Erase Voltages VPP = VIL for Complete Protection

Power Consumption Active Power Automatic Power Savings APS Standby Power Deep Power-Down Mode

Power and Reset Power-Up/Down Characteristics RP# Connected to System VCC, VPP and RP# Transitions

Power Supply Decoupling

Electrical

Absolute Maximum Operating Capacitance DC Characteristics AC Characteristics
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

AC Characteristics Operations 32 Program and Erase Timings 36

Reset Operations 38
Ordering Information 39

Additional Information 41

Appendix A Write State Machine Current/Next States 42

Appendix B Architecture Block 43

Appendix C Word-Wide Memory Map 44

Appendix D Byte-Wide Memory Map Diagrams 50

Appendix E Program and Erase Flowcharts 53
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

Number -001 -002
-003
-004
-005 -006 -007

Original version
Section VPP Program and Erase Voltages, added Updated Figure 9 Automated Block Erase Flowchart Updated Figure 10 Erase Suspend/Resume Flowchart added program to table Updated Figure 16 AC Waveform Program and Erase Operations updated notes IPPR maximum specification change from ±25 µA to ±50 µA Program and Erase Suspend Latency specification change Updated Appendix A Ordering Information included 8 M and 4 M information Updated Figure, Appendix D Architecture Block Diagram Block info. in words not bytes Minor wording changes
Combined byte-wide specification previously 290605 with this document Improved speed specification to 80 ns V and 90 ns V Improved V I/O option to minimum V Section Improved several DC characteristics Section Improved several AC characteristics Sections and Combined V and V DC characteristics Section Added 5 V VPP read specification Section Removed 120 ns and 150 ns speed offerings Moved Ordering Information from Appendix to Section updated information Moved Additional Information from Appendix to Section Updated figure Appendix B, Access Time vs. Capacitive Load Updated figure Appendix C, Architecture Block Diagram Moved Program and Erase Flowcharts to Appendix E Updated Program Flowchart Updated Program Suspend/Resume Flowchart Minor text edits throughout
Added 32-Mbit density Added 98H as a reserved command Table 4 = 0 when in read identifier mode Section Status register clarification for SR3 Table 7 VCC and VCCQ absolute maximum specification = V Section Combined IPPW and ICCW into one specification Section Combined IPPE and ICCE into one specification Section Max Parameter Block Erase Time tWHQV2/tEHQV2 reduced to 4 sec Section Max Main Block Erase Time tWHQV3/tEHQV3 reduced to 5 sec Section Erase suspend time 12 V tWHRH2/tEHRH2 changed to 5 µs typical and 20 µs maximum Section Ordering Information updated Section Write State Machine Current/Next States Table updated Appendix A Program Suspend/Resume Flowchart updated Appendix F Erase Suspend/Resume Flowchart updated Appendix F Text clarifications throughout
µBGA package diagrams corrected Figures 3 and 4 IPPD test conditions corrected Section 32-Mbit ordering information corrected Section 6 µBGA package top side mark information added Section 6

VIH and VILSpecification change Section ICCS test conditions clarification Section Added Command Sequence Error Note Table 7 Data sheet renamed from Smart 3 Advanced Boot Block 4-Mbit, 8-Mbit, 16-Mbit Flash Memory Family. Added device ID information for 4-Mbit x8 device Removed 32-Mbit x8 to reflect product offerings Minor text changes
Corrected RP# pin description in Table 2, 3 Volt Advanced Boot Block Pin Descriptions Corrected typographical error fixed in Ordering Information
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

Number -008 -009 -010 -011
-012
-013 -014 -015
-016
4-Mbit packaging and addressing information corrected throughout document

Corrected 4-Mbit memory addressing tables in Appendices D and E

Max ICCD changed to 25 µA VCCMax on 32 M 28F320B3 changed to V Added 64-Mbit density and faster speed offerings Removed access time vs. capacitance load curve

Changed references of 32Mbit 80ns devices to 70ns devices to reflect the faster product offering. Changed VccMax=3.3V reference to indicate the affected product is the 0.25µm 32Mbit device. Minor text edits throughout document.

Added New Pin-1 indicator information on 40 and 48Lead TSOP packages. Minor text edits throughout document.

Added specifications for micron product offerings throughout document

Minor text edits throughout document.
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

Introduction

This datasheet contains the specifications for the 3-Volt Advanced Boot Block Flash Memory
family, which is optimized for portable, low-power, systems. This family of products features V or V I/Os, and a low VCC/VPP operating range of V for Read, Program, and Erase operations. In addition, this family is capable of fast programming at 12 V.

Throughout this document, the term V” refers to the full voltage range V except
where noted otherwise and “VPP = 12 V” refers to 12 V Section and provide an overview of the Flash Memory family including applications, pinouts, and pin descriptions.

Section describes the memory organization and operation for these products. Sections and
contain the operating specifications. Finally, Sections and provide ordering and other
reference information.

The 3-Volt Advanced Boot Block Flash Memory features the following:
• Enhanced blocking for easy segmentation of code and data or additional design flexibility
• Program Suspend to Read command
• VCCQ input of V or V on all I/Os. See Figures 1 through 4 for pinout
diagrams and VCCQ location
• Maximum program and erase time specification for improved data storage.

Table 3-Volt Advanced Boot Block Feature Summary

Feature VCC Read Voltage VCCQ I/O Voltage VPP Program/Erase Voltage Bus Width Speed

Memory Arrangement

Blocking top or bottom

Locking Operating Temperature Program/Erase Cycling Packages
28F008B3, 28F016B3
28F800B3, 28F160B3, 28F320B3 3 , 28F640B3

V or V

V or V
8 bit
16 bit
70 ns, 80 ns, 90 ns, 100 ns, 110 ns
1024 Kbit x 8 Mbit , 2048 Kbit x 8 16 Mbit
512 Kbit x 16 8 Mbit , 1024 Kbit x 16 Mbit , 2048 Kbit x 16 32 Mbit , 4096 Kbit x 16 64 Mbit

Eight 8-Kbyte parameter blocks and Fifteen 64-Kbyte blocks 8 Mbit or Thirty-one 64-Kbyte main blocks 16 Mbit Sixty-three 64-Kbyte main blocks 32 Mbit One hundred twenty-seven 64-Kbyte main blocks 64 Mbit

WP# locks/unlocks parameter blocks All other blocks protected using VPP

Extended °C to +85 °C
100,000 cycles
40-lead TSOP 1 , 48-Ball µBGA* CSP 2
48-Lead TSOP, 48-Ball µBGA CSP 2 ,
48-Ball VF BGA 4

Reference Section Table 3 Section

Section

Section Appendix C

Section Table 8 Section

Figure 4, Figure 5
32-Mbit and 64-Mbit densities not available in 40-lead TSOP. 8-Mbit densities not available in µBGA* CSP. VCCMax is V on 0.25µm 32-Mbit devices.
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

Product Overview

Intel provides the most flexible voltage solution in the flash industry, providing three discrete voltage supply pins VCC for Read operation, VCCQ for output swing, and VPP for Program and Erase operation. All 3-Volt Advanced Boot Block Flash Memory products provide program/erase capability at V or 12 V for fast production programming , and read with VCC at V. Since many designs read from the flash memory a large percentage of the time, V VCC operation can provide substantial power savings.
The 3-Volt Advanced Boot Block Flash Memory products are available in either x8 or x16 packages in the following densities see Section “Ordering Information” on page 39 for availability.
• 8-Mbit 8, 388, 608-bit flash memory organized as 512 Kwords of 16 bits each or 1024

Kbytes of 8-bits each
• 16-Mbit 16, 777, 216-bit flash memory organized as 1024 Kwords of 16 bits each or
2048 Kbytes of 8-bits each
• 32-Mbit 33, 554, 432-bit flash memory organized as 2048 Kwords of 16 bits each
• 64-Mbit 67, 108, 864-bit flash memory organized as 4096 Kwords of 16 bits each

The parameter blocks are located at either the top denoted by -T suffix or the bottom -B suffix of the address map in order to accommodate different microprocessor protocols for kernel code location. The upper two or lower two parameter blocks can be locked to provide complete code security for system initialization code. Locking and unlocking is controlled by WP# see Section “Block Locking” on page 17 for details .

The Command User Interface CUI serves as the interface between the microprocessor or microcontroller and the internal operation of the flash memory. The internal Write State Machine WSM automatically executes the algorithms and timings necessary for Program and Erase operations, including verification, thereby unburdening the microprocessor or microcontroller. The status register indicates the status of the WSM by signifying block erase or word program completion and status.

The 3-Volt Advanced Boot Block flash memory is also designed with an Automatic Power Savings APS feature, which minimizes system current drain and allows for very low power designs. This mode is entered following the completion of a read cycle approximately 300 ns later .

The RP# pin provides additional protection against unwanted command writes that may occur during system reset and power-up/down sequences due to invalid system bus conditions see Section “Power-Up/Down Operation” on page

Section “Principles of Operation” on page 10 gives detailed explanation of the different modes of operation. Section “DC Characteristics” on page 23 provides complete current and voltage specifications. Refer to Section “AC Characteristics Operations” on page 27 for read, program, and erase performance specifications.
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

Product Description

This section explains device pin description and package pinouts.

Package Pinouts

The 3-Volt Advanced Boot Block flash memory is available in 40-lead TSOP x8, Figure 1 , 48-lead TSOP x16, Figure 2 , 48-ball µBGA x8 and x16, Figure 4 and Figure 5, respectively , and 48-ball VF BGA x16, Figure 5 packages. In all figures, pin changes necessary for density upgrades have been circled.

Figure 40-Lead TSOP Package for x8 Configurations

A16 A15 A14 A13 A12 A11 A9 A8 WE#

VPP WP#
37 36

A19 A10

Advanced Boot Block
40-Lead TSOP
10 mm x 20 mm

VCCQ
12 13

TOP VIEW
0580_01
40-Lead TSOP available for 8-Mbit and 16-Mbit densities only.

Lower densities will have NC on the upper address pins. For example, an 8-Mbit device will have NC on
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

Figure 48-Lead TSOP Package for x16 Configurations
64 M 32 M

A8 A21 A20
8 9 10

Advanced Boot Block 48-Lead TSOP 12 mm x 20 mm

TOP VIEW

VCCQ

DQ15

DQ14
Products Affected are Intel Ordering Codes:
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Ordering Information Valid Combinations 40-Lead TSOP

Ext. Temp. 32 Mbit

Ext. Temp. 16 Mbit

Ext. Temp. 8 Mbit

TE28F016B3TA90 3 TE28F016B3BA90 3 TE28F016B3TA110 3 TE28F016B3BA110 3 TE28F008B3TA90 3 TE28F008B3BA90 3 TE28F008B3TA110 3 TE28F008B3BA110 3
48-Lead TSOP

TE28F320B3TC70 TE28F320B3BC70 TE28F320B3TC90 TE28F320B3BC90 TE28F320B3TA100 TE28F320B3BA100 TE28F320B3TA110 TE28F320B3BA110 TE28F160B3TC70 TE28F160B3BC70 TE28F160B3TC80 TE28F160B3BC80 TE28F160B3TA90 3 TE28F160B3BA90 3 TE28F160B3TA110 3 TE28F160B3BA110 3 TE28F800B3TA90 3 TE28F800B3BA90 3 TE28F800B3TA110 3 TE28F800B3BA110 3
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

Figure x8 48-Ball µBGA* Chip Size Package Top View, Ball Down

VCCQ
0580_04

Shaded connections indicate the upgrade address connections. Lower density devices will not have the
upper address solder balls. Routing is not recommended in this area. A20 is the upgrade address for the 16-Mbit device.
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

Figure x16 48-Ball Very Fine Pitch BGA and µBGA* Chip Size Package Top View, Ball Down

A10 WE# RP#
64M 32M

VCCQ
0580_03

Shaded connections indicate the upgrade address connections. Lower density devices will not have the
upper address solder balls. Routing is not recommended in this area. A19 is the upgrade address for the 16-Mbit device. A20 is the upgrade address for the 32-Mbit device. A21 is the upgrade address for the 64-Mbit device.

Table 2, “3-Volt Advanced Boot Block Pin Descriptions” on page 9 details the usage of each device pin.
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

Table 3-Volt Advanced Boot Block Pin Descriptions

Type

Name and Function

DQ15 CE# OE# WE# RP#

VCCQ VCC

GND NC

INPUT

ADDRESS INPUTS for memory addresses. Addresses are internally latched during a program or erase cycle. 28F008B3 A[0-19], 28F016B3 A[0-20], 28F800B3 A[0-18], 28F160B3 A[0-19], 28F320B3 A[0-20], 28F640B3 A[0-21]

INPUT/ OUTPUT

DATA INPUTS/OUTPUTS Inputs array data on the second CE# and WE# cycle during a Program command. Inputs commands to the Command User Interface when CE# and WE# are active. Data is internally latched. Outputs array, identifier and status register data. The data pins float to tri-state when the chip is de-selected or the outputs are disabled.

INPUT/ OUTPUT

DATA INPUTS/OUTPUTS Inputs array data on the second CE# and WE# cycle during a Program command. Data is internally latched. Outputs array and identifier data. The data pins float to tri-state when the chip is de-selected. Not included on x8 products.

INPUT

CHIP ENABLE Activates the internal control logic, input buffers, decoders and sense amplifiers. CE# is active low. CE# high de-selects the memory device and reduces power consumption to standby levels.

INPUT

OUTPUT ENABLE Enables the device’s outputs through the data buffers during a Read operation. OE# is active low.

INPUT

WRITE ENABLE Controls writes to the Command Register and memory array. WE# is active low. Addresses and data are latched on the rising edge of the second WE# pulse.
Ordering Information
Figure Ordering Information

T E2 8 F 3 2 0 B3 T C7 0

Package TE = 48-Lead TSOP GT = 48-Ball µBGA* CSP GE = VF BGA CSP

Product line designator for all Flash products

Device Density 640 = x16 64 Mbit 320 = x16 32 Mbit 160 = x16 16 Mbit 800 = x16 8 Mbit
016 = x8 16 Mbit 008 = x8 8 Mbit

Access Speed ns 70, 80, 90, 100, 110

Lithography Not Present = µm A = µm C = µm D = µm

T = Top Blocking B = Bottom Blocking

Product Family B3 = 3 Volt Advanced+ Boot Block VCC = V VPP = V or
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Table Ordering Information Valid Combinations

Ext. Temp. 64 Mbit Ext. Temp. 32 Mbit

Ext. Temp. 16 Mbit Ext. Temp. 8 Mbit
40-Lead TSOP

TE28F016B3TA90 TE28F016B3BA90 TE28F016B3TA110 TE28F016B3BA110

TE28F008B3TA90 TE28F008B3BA90 TE28F008B3TA110 TE28F008B3BA110
48-Lead TSOP

TE28F640B3TC80 TE28F640B3BC80

TE28F320B3TC70 TE28F320B3BC70 TE28F320B3TC90 TE28F320B3BC90 TE28F320B3TA100 TE28F320B3BA100 TE28F320B3TA110 TE28F320B3BA110

TE28F160B3TD70 TE28F160B3BD70 TE28F160B3TC70 TE28F160B3BC70 TE28F160B3TC80 TE28F160B3BC80 TE28F160B3TC90 TE28F160B3BC90 TE28F160B3TA90 TE28F160B3BA90 TE28F160B3TA110 TE28F160B3BA110

TE28F800B3TA90 TE28F800B3BA90 TE28F800B3TA110 TE28F800B3BA110
48-Ball µBGA CSP 1,2
48-Ball VF BGA

GE28F640B3TC80 GE28F640B3BC80

GE28F320B3TD70 GE28F320B3BD70 GE28F320B3TC70 GE28F320B3BC70 GE28F320B3TC90 GE28F320B3BC90

GT28F160B3TA90 3 GT28F160B3BA90 3 GT28F160B3TA110 3 GT28F160B3BA110 3

GE28F160B3TD70 GE28F160B3BD70 GE28F160B3TC70 GE28F160B3BC70 GE28F160B3TC80 GE28F160B3BC80 GE28F160B3TC90 GE28F160B3BC90

GE28F800B3TA70 GE28F800B3BA70 GE28F008B3TA70 GE28F008B3BA70 GE28F800B3TA90 GE28F800B3BA90 GE28F008B3TA90 GE28F008B3BA90

The 48-ball µBGA package top side mark reads F160B3. This mark is identical for both x8 and x16 products. All product shipping boxes or trays provide the correct information regarding bus architecture. However, once the devices are removed from the shipping media, it may be difficult to differentiate based on the top side mark. The device identifier accessible through the Device ID command see Section for further details enables x8 and x16 µBGA package product differentiation.

The second line of the 48-ball µBGA package top side mark specifies assembly codes. For samples only, the first character signifies either “E” for engineering samples or “S” for silicon daisy-chain samples. All other assembly codes without an “E” or “S” as the first character are production units.

Intel recommends using µm Advanced Boot Block Products.
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

Additional Information

Order Number 297948 292199 292200 Note 2

Contact your Intel Representative 297874

Document/Tool 3 Volt Advanced Boot Block Flash Memory Family Specification Update AP-641 Achieving Low Power with the 3 Volt Advanced Boot Block Flash Memory AP-642 Designing for Upgrade to the 3 Volt Advanced Boot Block Flash Memory 3 Volt Advanced Boot Block Algorithms ‘C’ and assembly Flash Data Integrator IFDI Software Developer’s Kit IFDI Interactive Play with Flash Data Integrator on Your PC

NOTES Please call the Intel Literature Center at 800 548-4725 to request Intel documentation. International
customers should contact their local Intel or distribution sales office. Visit Intel’s World Wide Web home page at or for technical
documentation and tools. For the most current information on Intel Advanced and Advanced+ Boot Block Flash memory, visit our
microsite at
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

Appendix A Write State Machine Current/Next States

Command Input and Next State

Current State SR.7

Data When Read

Read Array FFH

Program Setup 10/

Erase Setup 20H

Erase Confirm

Prog/Ers Suspend

Prog/Ers Resume

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Datasheet ID: TE28F160B3TD70A 638916