SST39WF800A-90-4C-M2QE-T

SST39WF800A-90-4C-M2QE-T Datasheet

SST39WF800A

Part	Datasheet
SST39WF800A-90-4C-M2QE-T	SST39WF800A-90-4C-M2QE-T (pdf)

Related Parts	Information
SST39WF800A-90-4I-B3KE	SST39WF800A-90-4I-B3KE
SST39WF800A-90-4I-M2QE	SST39WF800A-90-4I-M2QE
SST39WF800A-90-4I-B3KE-T	SST39WF800A-90-4I-B3KE-T
SST39WF800A-90-4I-M2QE-T	SST39WF800A-90-4I-M2QE-T
SST39WF800A-90-4C-B3KE-T	SST39WF800A-90-4C-B3KE-T
SST39WF800A-90-4C-B3KE	SST39WF800A-90-4C-B3KE
SST39WF800A-90-4C-M2QE	SST39WF800A-90-4C-M2QE

PDF Datasheet Preview
8 Mbit x16 Multi-Purpose Flash SST39WF800A FEATURES: SST39WF800A1.8V 8Mb x16 MPF memory EOL Data Sheet • Organized as 512K x16 • Single Voltage Read and Write Operations 1.65-1.95V • Superior Reliability Endurance 100,000 Cycles typical Greater than 100 years Data Retention • Low Power Consumption typical values at 5 MHz Active Current 5 mA typical Standby Current 5 µA typical • Sector-Erase Capability Uniform 2 KWord sectors • Block-Erase Capability Uniform 32 KWord blocks • Fast Read Access Time 90 ns • Latched Address and Data • Fast Erase and Word-Program Sector-Erase Time 36 ms typical Block-Erase Time 36 ms typical Chip-Erase Time 140 ms typical Word-Program Time 28 µs typical • Automatic Write Timing Internal VPP Generation • End-of-Write Detection Toggle Bit Data# Polling • CMOS I/O Compatibility • JEDEC Standard Flash EEPROM Pinouts and command sets • Packages Available 48-ball TFBGA 6mm x 8mm 48-ball WFBGA 5mm x 6mm Micro-Package 48-ball XFLGA 5mm x 6mm Micro-Package • All non-Pb lead-free devices are RoHS compliant PRODUCT DESCRIPTION The SST39WF800A device is a 512K x16 CMOS MultiPurpose Flash MPF manufactured with SST’s proprietary, high performance CMOS SuperFlash technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST39WF800A writes Program or Erase with a 1.65-1.95V power supply. This device conforms to JEDEC standard pin assignments for x16 memories. Featuring high-performance Word-Program, the SST39WF800A device provides a typical Word-Program time of 28 µsec. The device uses Toggle Bit or Data# Polling to detect the completion of the Program or Erase operation. To protect against inadvertent writes, it has on-chip hardware and software data protection schemes. Designed, manufactured, and tested for a wide spectrum of applications, this device is offered with a guaranteed typical endurance of 100,000 cycles. Data retention is rated at greater than 100 years. The SST39WF800A device is suited for applications that require convenient and economical updating of program, configuration, or data memory. For all system applications, it significantly improves performance and reliability, while lowering power consumption. It inherently uses less energy 2010 Silicon Storage Technology, Inc. S71258-08-EOL 01/10 during Erase and Program than alternative flash technologies. When programming a flash device, the total energy consumed is a function of the applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash technologies. These devices also improve flexibility while lowering the cost for program, data, and configuration storage applications. The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/Program cycles that have occurred. Therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles. To meet surface mount requirements, the SST39WF800A is offered in a 48-ball TFBGA package and a 48-ball MicroPackage. See Figure 3 and Figure 2 for pin assignments. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. MPF is a trademark of Silicon Storage Technology, Inc. These specifications are subject to change without notice. EOL Data Sheet Device Operation Commands are used to initiate the memory operation functions of the device. Commands are written to the device using standard microprocessor write sequences. A command is written by asserting WE# low while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first. Read The Read operation of the SST39WF800A is controlled by CE# and OE#, both have to be low for the system to obtain data from the outputs. CE# is used for device selection. When CE# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is high. Refer to the Read cycle timing diagram for further details Figure Word-Program Operation The SST39WF800A is programmed on a word-by-word basis. Before programming, the sector where the word exists must be fully erased. The Program operation is accomplished in three steps. The first step is the three-byte load sequence for Software Data Protection. The second step is to load word address and word data. During the Word-Program operation, the addresses are latched on the falling edge of either CE# or WE#, whichever occurs last. The data is latched on the rising edge of either CE# or WE#, whichever occurs first. The third step is the internal Program operation which is initiated after the rising edge of the fourth WE# or CE#, whichever occurs first. The Program operation, once initiated, will be completed within 40 µs. See Figures 5 and 6 for WE# and CE# controlled Program operation timing diagrams and Figure 17 for flowcharts. During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any commands issued during the internal Program operation are ignored. 8 Mbit Multi-Purpose Flash SST39WF800A Sector/Block-Erase Operation The Sector- or Block- Erase operation allows the system to erase the device on a sector-by-sector or block-byblock basis. The SST39WF800A offers both Sector-Erase and Block-Erase mode. The sector architecture is based on uniform sector size of 2 KWord. The Block-Erase mode is based on uniform block size of 32 KWord. The SectorErase operation is initiated by executing a six-byte command sequence with Sector-Erase command 30H and sector address SA in the last bus cycle. The Block-Erase operation is initiated by executing a six-byte command sequence with Block-Erase command 50H and block address BA in the last bus cycle. The sector or block address is latched on the falling edge of the sixth WE# pulse, while the command 30H or 50H is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. The End-ofErase operation can be determined using either Data# Polling or Toggle Bit methods. See Figures 10 and 11 for timing waveforms. Any commands issued during the Sector- or Block-Erase operation are ignored. PRODUCT ORDERING INFORMATION EOL Data Sheet SST 39 WF 800A - 90 - 4C - B3K E XX XXXX - XX - XX - XXX X Environmental Attribute E1 = non-Pb Package Modifier K = 48 balls Q = 48 balls 66 possible positions Package Type B3 = TFBGA 0.8mm pitch, 6mm x 8mm M2 = WFBGA 0.5mm pitch, 5mm x 6mm C2 = XFLGA 0.5mm pitch, 5mm x 6mm Temperature Range C = Commercial = 0°C to +70°C I = Industrial = -40°C to +85°C Minimum Endurance 4 = 10,000 cycles Read Access Speed 90 = 90 ns Device Density 800 = 8 Mbit Voltage W = 1.65-1.95V Product Series 39 = Multi-Purpose Flash Environmental suffix “E” denotes non-Pb solder. SST non-Pb solder devices are “RoHS Compliant”. Valid combinations for SST39WF800A-90-4C-B3KE SST39WF800A-90-4C-M2QE SST39WF800A-90-4I-B3KE SST39WF800A-90-4I-M2QE SST39WF800A-90-4C-C2QE SST39WF800A-90-4I-C2QE Note Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. 2010 Silicon Storage Technology, Inc. S71258-08-EOL 01/10 EOL Data Sheet PACKAGING DIAGRAMS 8 Mbit Multi-Purpose Flash SST39WF800A TOP VIEW ± 6 5 4 3 2 1 ABCDEFGH A1 CORNER SIDE VIEW ± ± BOTTOM VIEW ± 48X HGFEDCBA A1 CORNER SEATING PLANE Note: Complies with JEDEC Publication 95, MO-210, variant 'AB-1', although some dimensions may be more stringent. All linear dimensions are in millimeters. Coplanarity mm Ball opening size is mm ± mm 48-tfbga-B3K-6x8-450mic-4 FIGURE 21 48-Ball Thin-Profile, Fine-Pitch Ball Grid Array TFBGA 6mm x 8mm SST Package Code B3K TOP VIEW 6 5 4 3 2 1 • Added RoHS compliance information on page 1 and in the “Product Ordering Information” on page 23 • Corrected the solder temperature profile in “Absolute Maximum Stress Ratings” on page 9 03 • Added C2Q package information and relevant marketing part numbers. • Removed Pb-based package marketing part numbers from valid ordering list on page • Applied new style format. 04 • In Figure 20 title, changed XFBGA 6mm x 8mm to XFLGA 5mm x 6mm 05 • Changed package C2 size from 6mm x 8mm to 5mm x 6mm in Product Ordering Information on page 06 • Added Y1QE package information 07 • Removed Y1QE package information 08 • EOL of all SST39WF800A products. Replacement parts are the respective SST39WF800B parts found in S71344. Date Aug 2004 Nov 2004 Mar 2005 Feb 2006 Jun 2006 Jul 2006 Jul 2007 Nov 2007 Jan 2010 Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036 or 2010 Silicon Storage Technology, Inc. S71258-08-EOL 01/10

PDF Datasheet Preview

8 Mbit x16 Multi-Purpose Flash

SST39WF800A

FEATURES:

SST39WF800A1.8V 8Mb x16 MPF memory

EOL Data Sheet
• Organized as 512K x16
• Single Voltage Read and Write Operations
1.65-1.95V
• Superior Reliability

Endurance 100,000 Cycles typical Greater than 100 years Data Retention
• Low Power Consumption typical values at 5 MHz Active Current 5 mA typical Standby Current 5 µA typical
• Sector-Erase Capability Uniform 2 KWord sectors
• Block-Erase Capability Uniform 32 KWord blocks
• Fast Read Access Time 90 ns
• Latched Address and Data
• Fast Erase and Word-Program

Sector-Erase Time 36 ms typical Block-Erase Time 36 ms typical Chip-Erase Time 140 ms typical Word-Program Time 28 µs typical
• Automatic Write Timing

Internal VPP Generation
• End-of-Write Detection

Toggle Bit Data# Polling
• CMOS I/O Compatibility
• JEDEC Standard

Flash EEPROM Pinouts and command sets
• Packages Available
48-ball TFBGA 6mm x 8mm 48-ball WFBGA 5mm x 6mm Micro-Package 48-ball XFLGA 5mm x 6mm Micro-Package
• All non-Pb lead-free devices are RoHS compliant

PRODUCT DESCRIPTION

The SST39WF800A device is a 512K x16 CMOS MultiPurpose Flash MPF manufactured with SST’s proprietary, high performance CMOS SuperFlash technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST39WF800A writes Program or Erase with a 1.65-1.95V power supply. This device conforms to JEDEC standard pin assignments for x16 memories.

Featuring high-performance Word-Program, the SST39WF800A device provides a typical Word-Program time of 28 µsec. The device uses Toggle Bit or Data# Polling to detect the completion of the Program or Erase operation. To protect against inadvertent writes, it has on-chip hardware and software data protection schemes. Designed, manufactured, and tested for a wide spectrum of applications, this device is offered with a guaranteed typical endurance of 100,000 cycles. Data retention is rated at greater than 100 years.

The SST39WF800A device is suited for applications that require convenient and economical updating of program, configuration, or data memory. For all system applications, it significantly improves performance and reliability, while lowering power consumption. It inherently uses less energy
2010 Silicon Storage Technology, Inc.

S71258-08-EOL
01/10
during Erase and Program than alternative flash technologies. When programming a flash device, the total energy consumed is a function of the applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash technologies. These devices also improve flexibility while lowering the cost for program, data, and configuration storage applications.

The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/Program cycles that have occurred. Therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles.

To meet surface mount requirements, the SST39WF800A is offered in a 48-ball TFBGA package and a 48-ball MicroPackage. See Figure 3 and Figure 2 for pin assignments.

The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. MPF is a trademark of Silicon Storage Technology, Inc.

These specifications are subject to change without notice.

EOL Data Sheet

Device Operation

Commands are used to initiate the memory operation functions of the device. Commands are written to the device using standard microprocessor write sequences. A command is written by asserting WE# low while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first.

Read

The Read operation of the SST39WF800A is controlled by CE# and OE#, both have to be low for the system to obtain data from the outputs. CE# is used for device selection. When CE# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is high. Refer to the Read cycle timing diagram for further details Figure

Word-Program Operation

The SST39WF800A is programmed on a word-by-word basis. Before programming, the sector where the word exists must be fully erased. The Program operation is accomplished in three steps. The first step is the three-byte load sequence for Software Data Protection. The second step is to load word address and word data. During the Word-Program operation, the addresses are latched on the falling edge of either CE# or WE#, whichever occurs last. The data is latched on the rising edge of either CE# or WE#, whichever occurs first. The third step is the internal Program operation which is initiated after the rising edge of the fourth WE# or CE#, whichever occurs first. The Program operation, once initiated, will be completed within 40 µs. See Figures 5 and 6 for WE# and CE# controlled Program operation timing diagrams and Figure 17 for flowcharts. During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any commands issued during the internal Program operation are ignored.
8 Mbit Multi-Purpose Flash SST39WF800A

Sector/Block-Erase Operation

The Sector- or Block- Erase operation allows the system to erase the device on a sector-by-sector or block-byblock basis. The SST39WF800A offers both Sector-Erase and Block-Erase mode. The sector architecture is based on uniform sector size of 2 KWord. The Block-Erase mode is based on uniform block size of 32 KWord. The SectorErase operation is initiated by executing a six-byte command sequence with Sector-Erase command 30H and sector address SA in the last bus cycle. The Block-Erase operation is initiated by executing a six-byte command sequence with Block-Erase command 50H and block address BA in the last bus cycle. The sector or block address is latched on the falling edge of the sixth WE# pulse, while the command 30H or 50H is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. The End-ofErase operation can be determined using either Data# Polling or Toggle Bit methods. See Figures 10 and 11 for timing waveforms. Any commands issued during the Sector- or Block-Erase operation are ignored.
PRODUCT ORDERING INFORMATION

EOL Data Sheet

SST 39 WF 800A - 90 - 4C - B3K E XX XXXX - XX - XX - XXX X

Environmental Attribute E1 = non-Pb

Package Modifier K = 48 balls Q = 48 balls 66 possible positions

Package Type B3 = TFBGA 0.8mm pitch, 6mm x 8mm M2 = WFBGA 0.5mm pitch, 5mm x 6mm C2 = XFLGA 0.5mm pitch, 5mm x 6mm

Temperature Range C = Commercial = 0°C to +70°C I = Industrial = -40°C to +85°C

Minimum Endurance 4 = 10,000 cycles

Read Access Speed 90 = 90 ns

Device Density 800 = 8 Mbit

Voltage W = 1.65-1.95V

Product Series 39 = Multi-Purpose Flash

Environmental suffix “E” denotes non-Pb solder. SST non-Pb solder devices are “RoHS Compliant”.

Valid combinations for SST39WF800A-90-4C-B3KE SST39WF800A-90-4C-M2QE SST39WF800A-90-4I-B3KE SST39WF800A-90-4I-M2QE

SST39WF800A-90-4C-C2QE SST39WF800A-90-4I-C2QE

Note Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations.
2010 Silicon Storage Technology, Inc.

S71258-08-EOL
01/10

EOL Data Sheet

PACKAGING DIAGRAMS
8 Mbit Multi-Purpose Flash SST39WF800A

TOP VIEW ±
6 5 4 3 2 1

ABCDEFGH

A1 CORNER SIDE VIEW
± ±

BOTTOM VIEW
± 48X

HGFEDCBA

A1 CORNER

SEATING PLANE

Note:

Complies with JEDEC Publication 95, MO-210, variant 'AB-1', although some dimensions may be more stringent.

All linear dimensions are in millimeters.

Coplanarity mm

Ball opening size is mm ± mm
48-tfbga-B3K-6x8-450mic-4

FIGURE 21 48-Ball Thin-Profile, Fine-Pitch Ball Grid Array TFBGA 6mm x 8mm SST Package Code B3K

TOP VIEW
6 5 4 3 2 1
• Added RoHS compliance information on page 1 and in the “Product Ordering Information” on page 23
• Corrected the solder temperature profile in “Absolute Maximum Stress Ratings” on page 9
03
• Added C2Q package information and relevant marketing part numbers.
• Removed Pb-based package marketing part numbers from valid ordering list on page
• Applied new style format.
04
• In Figure 20 title, changed XFBGA 6mm x 8mm to XFLGA 5mm x 6mm
05
• Changed package C2 size from 6mm x 8mm to 5mm x 6mm in Product Ordering Information on page
06
• Added Y1QE package information
07
• Removed Y1QE package information
08
• EOL of all SST39WF800A products. Replacement parts are the respective SST39WF800B parts found in S71344.

Date Aug 2004 Nov 2004

Mar 2005

Feb 2006

Jun 2006 Jul 2006 Jul 2007 Nov 2007 Jan 2010

Silicon Storage Technology, Inc.
• 1171 Sonora Court
• Sunnyvale, CA 94086
• Telephone 408-735-9110
• Fax 408-735-9036 or
2010 Silicon Storage Technology, Inc.

S71258-08-EOL
01/10

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived SST39WF800A-90-4C-M2QE-T Datasheet file may be downloaded here without warranties.

Datasheet ID: SST39WF800A-90-4C-M2QE-T 648214