LAN91C113-NS

LAN91C113-NS Datasheet

LAN91C113

Part	Datasheet
LAN91C113-NS	LAN91C113-NS (pdf)

Related Parts	Information
LAN91C113-NU	LAN91C113-NU

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LAN91C113 16-Bit 10/100 Non-PCI Ethernet Single Chip MAC + PHY Product Features Single Chip Ethernet Controller Dual Speed - 10/100 Mbps Fully Supports Full Duplex Switched Ethernet 8 Kbytes Internal Memory for Receive and Transmit FIFO Buffers Enhanced Power Management Features Optional Configuration via Serial EEPROM Interface Supports 8, 16 Bit CPU Accesses Internal 16 Bit Wide Data Path Into Packet Buffer Memory Early TX, Early RX Functions Built-in Transparent Arbitration for Slave Sequential Access Architecture Flat MMU Architecture with Symmetric Transmit and Receive Structures and Queues 3.3V Operation with 5V Tolerant IO Buffers See Pin List Description for Additional Details Single 25 MHz Reference Clock for Both PHY and MAC External 25Mhz-output pin for an external PHY supporting PHYs physical media. Low Power CMOS Design Supports Multiple Embedded Processor Host Interfaces − ARM − SH − Power PC − Coldfire − 680X0, 683XX − MIPS R3000 Datasheet 3.3V MII Media Independent Interface MACPHY Interface Running at Nibble Rate MII Management Serial Interface 128 Pin QFP Package Green, Lead-Free Package also available 128 Pin TQFP Package, mm height Green, Lead-Free Package also available Temperature Range from 0°C to 85°C Network Interface Fully Integrated IEEE 802.3/802.3u-100Base-TX / 10Base-T Physical Layer Auto Negotiation 10/100, Full / Half Duplex On Chip Wave Shaping - No External Filters Required Adaptive Equalizer Baseline Wander Correction LED Outputs User selectable Up to 2 LED functions at one time − Link − Activity − Full Duplex − 10/100 − Transmit − Receive SMSC LAN91C113 DATASHEET 16-Bit 10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet ORDERING INFORMATION Order Number s : LAN91C113-NC for 128 Pin QFP Package LAN91C113-NE for 128 Pin TQFP Package mm height LAN91C113-NS for 128 Pin QFP Package Green, Lead-Free LAN91C113-NU for 128 Pin TQFP Package mm height Green, Lead-Free 80 Arkay Drive Hauppauge, NY 11788 631 435-6000 FAX 631 273-3123 Copyright SMSC All rights reserved. Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard Terms of Sale Agreement dated before the date of your order the "Terms of Sale Agreement" . The product may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC’s website at SMSC is a registered trademark of Standard Microsystems Corporation “SMSC” . Product names and company names are the trademarks of their respective holders. SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE. DATASHEET SMSC LAN91C113 16-Bit 10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Table of Contents Chapter 1 General Description 7 Chapter 2 Pin Configurations 8 Chapter 3 Block Diagrams 10 Chapter 4 Signal 13 Chapter 5 Description of Pin Functions 14 Signal Description Parameters 18 Buffer 18 Chapter 6 Functional 19 Clock Generator Block 19 CSMA/CD 19 DMA Block Arbiter Block MMU 20 BIU Block 20 MAC-PHY 20 Management Data Software Management Data Timing MI Serial Port Frame Structure MII Packet Data Communication with External Serial EEPROM Interface 24 Internal Physical 24 MII Encoder Decoder Clock and Data Recovery Scrambler Descrambler Twisted Pair Transmitter Twisted Pair Receiver Collision Start of End of Link Integrity & Jabber Receive Polarity Full Duplex Mode PHY Powerdown PHY Interrupt Chapter 7 Data Structures and Registers 43 Frame Format In Buffer 43 Receive Frame Status 44 I/O Space 45 Bank Select Register 46 Bank 0 - Transmit Control Register 47 Bank 0 - EPH Status 48 Bank 0 - Receive Control Register 49 Bank 0 - Counter Register 50 Bank 0 - Memory Information Register 50 Bank 0 - Receive/PHY Control Register 51 SMSC LAN91C113 DATASHEET 16-Bit 10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Chapter 8 PHY MII 67 Register Control 70 Register Status Register 71 Register PHY Identifier Register 72 Register Auto-Negotiation Advertisement Register 72 Register Auto-Negotiation Remote End Capability Register 73 Register Configuration 1-- Structure and Bit 73 Register Configuration 2 - Structure and Bit 74 Register Status Output - Structure and Bit Definition 74 Register Mask - Structure and Bit 75 Register Reserved - Structure and Bit 76 Chapter 9 Software Driver and Hardware Sequence 77 Software Driver and Hardware Sequence Flow for Power 77 Typical Flow of Events for Transmit Auto Release = 0 78 Typical Flow of Events for Transmit Auto Release = 1 79 Typical Flow of Event For Receive 80 Chapter 10 Board Setup Information 89 Chapter 11 Application 92 Chapter 12 Operational Description 98 Maximum Guaranteed 98 DC Electrical Characteristics 98 Twisted Pair Characteristics, Transmit 101 Twisted Pair Characteristics, Receive 102 Chapter 13 Timing Diagrams 103 DATASHEET SMSC LAN91C113 16-Bit 10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet List of Figures Figure - Pin Configuration - LAN91C113 128 Pin TQFP Figure - Pin Configuration - LAN91C113 128 Pin QFP Figure - LAN91C113 - Basic Functional Block Figure - Block Figure - LAN91C113 Physical Layer to Internal Mac Block Diagram Figure - MI Serial Port Frame Timing Figure - MII Frame Format & MII Nibble Figure - TX/10BT Frame Format Figure - TP Output Voltage Template 10 MBPS Figure - TP Input Voltage Template 10 MBPS Figure - SOI Outage Voltage Template Figure - Link Pulse Output Voltage Template NLP, FLP Figure - NLP VS. FLP Link Pulse Figure - Data Frame Figure - Interrupt Structure Figure - Interrupt Service Routine Figure - RX INTR Figure - TX Figure - TXEMPTY INTR Assumes Auto Release Option Figure Drive Send and Allocate Figure Interrupt Generation for Transmit, Receive, Figure - 64 X 16 Serial EEPROM Map Figure - LAN91C113 on VL Bus Figure - LAN91C113 on ISA Bus Figure - LAN91C113 On EISA Bus Figure Asynchronous Cycle - nADS=0 Figure - Asynchronous Cycle - Using Figure Asynchronous Ready Figure Address Latching for all Modes Figure Synchronous Write Cycle - nVLBUS=0 Figure Synchronous Read Cycle - nVLBUS=0 Figure - MII Timing Figure Transit Timing Figure Receive Timing, End of Packet - 10 MBPS Figure Collision Timing, Receive Figure Collision Timing, Transmit Figure Jam Figure Link Pulse Figure - FLP Link Pulse Timing Figure - 128 Pin TQFP Package Outline, 14X14X1.0 Body Figure - 128 Pin QFP Package Outline, MM Footprint SMSC LAN91C113 canceling packet transmissions, and reordering or bypassing the transmit queue. The RESET TX FIFOs command should only be used when the transmitter is disabled. Unlike the RESET MMU command, the RESET TX FIFOs does not release any memory. Notes When using the RESET TX FIFOS command, the CPU is responsible for releasing the memory associated with outstanding packets, or re-enqueuing them. Packet numbers in the completion FIFO can be read via the FIFO ports register before issuing the command. SMSC LAN91C113 Page 57 DATASHEET 16-Bit 10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet MMU commands releasing memory commands 4 and 5 should only be issued if the corresponding packet number has memory allocated to it. COMMAND SEQUENCING A second allocate command 1 should not be issued until the present one has completed. Completion is determined by reading the FAILED bit of the allocation result register or through the allocation interrupt. A second release command commands 4, 5 should not be issued if the previous one is still being processed. The BUSY bit indicates that a release command is in progress. After issuing command 5, the contents of the PNR should not be changed until BUSY goes low. After issuing command 4, command 3 should not be issued until BUSY goes low. BUSY BIT - Readable at bit 0 of the MMU command register address. When set indicates that MMU is still processing a release command. When clear, MMU has already completed last release command. BUSY and FAILED bits are set upon the trailing edge of command. Bank 2 - Packet Number Register OFFSET 2 NAME PACKET NUMBER REGISTER TYPE READ/WRITE SYMBOL PNR Reserved PACKET NUMBER AT TX AREA PACKET NUMBER AT TX AREA - The value written into this register determines which packet number is accessible through the TX area. Some MMU commands use the number stored in this register as the packet number parameter. This register is cleared by a RESET or a RESET MMU Command. OFFSET 3 NAME ALLOCATION RESULT REGISTER TYPE READ ONLY SYMBOL ARR This register is updated upon an ALLOCATE MEMORY MMU command. FAILED Reserved ALLOCATED PACKET NUMBER FAILED - A zero indicates a successful allocation completion. If the allocation fails the bit is set and only cleared when the pending allocation is satisfied. Defaults high upon reset and reset MMU command. For polling purposes, the ALLOC_INT in the Interrupt Status Register should be used because it is synchronized to the read operation. Sequence: 1 Allocate Command 2 Poll ALLOC_INT bit until set 3 Read Allocation Result Register ALLOCATED PACKET NUMBER - Packet number associated with the last memory allocation request. The value is only valid if the FAILED bit is clear. Note: For software compatibility with future versions, the value read from the ARR after an allocation request is intended to be written into the PNR as is, without masking higher bits provided FAILED = Page 58 DATASHEET SMSC LAN91C113 16-Bit 10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet

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LAN91C113
16-Bit 10/100 Non-PCI Ethernet Single Chip MAC + PHY

Product Features

Single Chip Ethernet Controller Dual Speed - 10/100 Mbps Fully Supports Full Duplex Switched Ethernet 8 Kbytes Internal Memory for Receive and

Transmit FIFO Buffers Enhanced Power Management Features Optional Configuration via Serial EEPROM

Interface Supports 8, 16 Bit CPU Accesses Internal 16 Bit Wide Data Path Into Packet

Buffer Memory Early TX, Early RX Functions Built-in Transparent Arbitration for Slave

Sequential Access Architecture Flat MMU Architecture with Symmetric Transmit
and Receive Structures and Queues 3.3V Operation with 5V Tolerant IO Buffers See

Pin List Description for Additional Details Single 25 MHz Reference Clock for Both PHY
and MAC External 25Mhz-output pin for an external PHY
supporting PHYs physical media. Low Power CMOS Design Supports Multiple Embedded Processor Host

Interfaces
− ARM − SH − Power PC − Coldfire − 680X0, 683XX − MIPS R3000

Datasheet
3.3V MII Media Independent Interface MACPHY Interface Running at Nibble Rate

MII Management Serial Interface 128 Pin QFP Package Green, Lead-Free

Package also available 128 Pin TQFP Package, mm height Green,

Lead-Free Package also available Temperature Range from 0°C to 85°C

Network Interface Fully Integrated IEEE 802.3/802.3u-100Base-TX
/ 10Base-T Physical Layer Auto Negotiation 10/100, Full / Half Duplex On Chip Wave Shaping - No External Filters

Required Adaptive Equalizer Baseline Wander Correction LED Outputs User selectable Up to 2 LED
functions at one time
− Link − Activity − Full Duplex − 10/100 − Transmit − Receive

SMSC LAN91C113

DATASHEET
16-Bit 10/100 Non-PCI Ethernet Single Chip MAC + PHY

Datasheet
ORDERING INFORMATION

Order Number s :

LAN91C113-NC for 128 Pin QFP Package LAN91C113-NE for 128 Pin TQFP Package mm height LAN91C113-NS for 128 Pin QFP Package Green, Lead-Free LAN91C113-NU for 128 Pin TQFP Package mm height Green, Lead-Free
80 Arkay Drive Hauppauge, NY 11788 631 435-6000 FAX 631 273-3123

Copyright SMSC All rights reserved.

Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard Terms of Sale Agreement dated before the date of your order the "Terms of Sale Agreement" . The product may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC’s website at SMSC is a registered trademark of Standard Microsystems Corporation “SMSC” . Product names and company names are the trademarks of their respective holders.

SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE.

DATASHEET

SMSC LAN91C113
16-Bit 10/100 Non-PCI Ethernet Single Chip MAC + PHY

Datasheet

Table of Contents

Chapter 1 General Description 7

Chapter 2 Pin Configurations 8

Chapter 3 Block Diagrams 10

Chapter 4 Signal 13

Chapter 5 Description of Pin Functions 14 Signal Description Parameters 18 Buffer 18

Chapter 6 Functional 19 Clock Generator Block 19 CSMA/CD 19

DMA Block Arbiter Block

MMU 20 BIU Block 20 MAC-PHY 20

Management Data Software Management Data Timing MI Serial Port Frame Structure MII Packet Data Communication with External

Serial EEPROM Interface 24 Internal Physical 24

MII Encoder Decoder Clock and Data Recovery Scrambler Descrambler Twisted Pair Transmitter Twisted Pair Receiver Collision Start of End of Link Integrity & Jabber Receive Polarity Full Duplex Mode PHY Powerdown PHY Interrupt

Chapter 7 Data Structures and Registers 43 Frame Format In Buffer 43 Receive Frame Status 44 I/O Space 45 Bank Select Register 46 Bank 0 - Transmit Control Register 47 Bank 0 - EPH Status 48 Bank 0 - Receive Control Register 49 Bank 0 - Counter Register 50 Bank 0 - Memory Information Register 50 Bank 0 - Receive/PHY Control Register 51

SMSC LAN91C113

DATASHEET
16-Bit 10/100 Non-PCI Ethernet Single Chip MAC + PHY

Datasheet

Chapter 8 PHY MII 67 Register Control 70 Register Status Register 71 Register PHY Identifier Register 72 Register Auto-Negotiation Advertisement Register 72 Register Auto-Negotiation Remote End Capability Register 73 Register Configuration 1-- Structure and Bit 73 Register Configuration 2 - Structure and Bit 74 Register Status Output - Structure and Bit Definition 74 Register Mask - Structure and Bit 75 Register Reserved - Structure and Bit 76

Chapter 9 Software Driver and Hardware Sequence 77 Software Driver and Hardware Sequence Flow for Power 77 Typical Flow of Events for Transmit Auto Release = 0 78 Typical Flow of Events for Transmit Auto Release = 1 79 Typical Flow of Event For Receive 80

Chapter 10 Board Setup Information 89

Chapter 11 Application 92

Chapter 12 Operational Description 98 Maximum Guaranteed 98 DC Electrical Characteristics 98 Twisted Pair Characteristics, Transmit 101 Twisted Pair Characteristics, Receive 102

Chapter 13 Timing Diagrams 103

DATASHEET

SMSC LAN91C113
16-Bit 10/100 Non-PCI Ethernet Single Chip MAC + PHY

Datasheet

List of Figures

Figure - Pin Configuration - LAN91C113 128 Pin TQFP Figure - Pin Configuration - LAN91C113 128 Pin QFP Figure - LAN91C113 - Basic Functional Block Figure - Block Figure - LAN91C113 Physical Layer to Internal Mac Block Diagram Figure - MI Serial Port Frame Timing Figure - MII Frame Format & MII Nibble Figure - TX/10BT Frame Format Figure - TP Output Voltage Template 10 MBPS Figure - TP Input Voltage Template 10 MBPS Figure - SOI Outage Voltage Template Figure - Link Pulse Output Voltage Template NLP, FLP Figure - NLP VS. FLP Link Pulse Figure - Data Frame Figure - Interrupt Structure Figure - Interrupt Service Routine Figure - RX INTR Figure - TX Figure - TXEMPTY INTR Assumes Auto Release Option Figure Drive Send and Allocate Figure Interrupt Generation for Transmit, Receive, Figure - 64 X 16 Serial EEPROM Map Figure - LAN91C113 on VL Bus Figure - LAN91C113 on ISA Bus Figure - LAN91C113 On EISA Bus Figure Asynchronous Cycle - nADS=0 Figure - Asynchronous Cycle - Using Figure Asynchronous Ready Figure Address Latching for all Modes Figure Synchronous Write Cycle - nVLBUS=0 Figure Synchronous Read Cycle - nVLBUS=0 Figure - MII Timing Figure Transit Timing Figure Receive Timing, End of Packet - 10 MBPS Figure Collision Timing, Receive Figure Collision Timing, Transmit Figure Jam Figure Link Pulse Figure - FLP Link Pulse Timing Figure - 128 Pin TQFP Package Outline, 14X14X1.0 Body Figure - 128 Pin QFP Package Outline, MM Footprint

SMSC LAN91C113
canceling packet transmissions, and reordering or bypassing the transmit
queue. The RESET TX FIFOs command should only be used when the
transmitter is disabled. Unlike the RESET MMU command, the RESET

TX FIFOs does not release any memory.

Notes When using the RESET TX FIFOS command, the CPU is responsible for releasing the memory associated with
outstanding packets, or re-enqueuing them. Packet numbers in the completion FIFO can be read via the FIFO ports
register before issuing the command.

SMSC LAN91C113

Page 57

DATASHEET
16-Bit 10/100 Non-PCI Ethernet Single Chip MAC + PHY

Datasheet

MMU commands releasing memory commands 4 and 5 should only be issued if the corresponding packet number has memory allocated to it.

COMMAND SEQUENCING

A second allocate command 1 should not be issued until the present one has completed. Completion is determined by reading the FAILED bit of the allocation result register or through the allocation interrupt.

A second release command commands 4, 5 should not be issued if the previous one is still being processed. The BUSY bit indicates that a release command is in progress. After issuing command 5, the contents of the PNR should not be changed until BUSY goes low. After issuing command 4, command 3 should not be issued until BUSY goes low.

BUSY BIT - Readable at bit 0 of the MMU command register address. When set indicates that MMU is still processing a release command. When clear, MMU has already completed last release command. BUSY and FAILED bits are set upon the trailing edge of command.

Bank 2 - Packet Number Register

OFFSET 2

NAME PACKET NUMBER REGISTER

TYPE READ/WRITE

SYMBOL PNR

Reserved

PACKET NUMBER AT TX AREA

PACKET NUMBER AT TX AREA - The value written into this register determines which packet number is accessible through the TX area. Some MMU commands use the number stored in this register as the packet number parameter. This register is cleared by a RESET or a RESET MMU Command.

OFFSET 3

NAME ALLOCATION RESULT REGISTER

TYPE READ ONLY

SYMBOL ARR

This register is updated upon an ALLOCATE MEMORY MMU command.

FAILED Reserved

ALLOCATED PACKET NUMBER

FAILED - A zero indicates a successful allocation completion. If the allocation fails the bit is set and only cleared when the pending allocation is satisfied. Defaults high upon reset and reset MMU command. For polling purposes, the ALLOC_INT in the Interrupt Status Register should be used because it is synchronized to the read operation. Sequence:
1 Allocate Command 2 Poll ALLOC_INT bit until set 3 Read Allocation Result Register

ALLOCATED PACKET NUMBER - Packet number associated with the last memory allocation request. The value is only valid if the FAILED bit is clear.

Note:

For software compatibility with future versions, the value read from the ARR after an allocation request is intended to be written into the PNR as is, without masking higher bits provided FAILED =

Page 58

DATASHEET

SMSC LAN91C113
16-Bit 10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet

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Datasheet ID: LAN91C113-NS 648121