DSPIC33EP64GS502-E/MX

DSPIC33EP64GS502-E/MX Datasheet

dsPIC33EPXXGS50X FAMILY

Part	Datasheet
DSPIC33EP64GS502-E/MX	DSPIC33EP64GS502-E/MX (pdf)

Related Parts	Information
DSPIC33EP64GS502T-E/MX	DSPIC33EP64GS502T-E/MX
DSPIC33EP32GS502T-E/MX	DSPIC33EP32GS502T-E/MX
DSPIC33EP16GS502T-E/MX	DSPIC33EP16GS502T-E/MX
DSPIC33EP32GS502-I/MX	DSPIC33EP32GS502-I/MX
DSPIC33EP32GS502-E/MX	DSPIC33EP32GS502-E/MX
DSPIC33EP64GS502T-I/MX	DSPIC33EP64GS502T-I/MX
DSPIC33EP32GS502T-I/MX	DSPIC33EP32GS502T-I/MX
DSPIC33EP64GS502-I/MX	DSPIC33EP64GS502-I/MX

PDF Datasheet Preview
dsPIC33EPXXGS50X FAMILY 16-Bit Digital Signal Controllers for Digital Power Applications with Interconnected High-Speed PWM, ADC, PGA and Comparators Operating Conditions • 3.0V to 3.6V, -40°C to +85°C, DC to 70 MIPS • 3.0V to 3.6V, -40°C to +125°C, DC to 60 MIPS Flash Architecture • Dual Partition Flash Program Memory with Live Update 64-Kbyte devices - Supports programming while operating - Supports partition soft swap Core 16-Bit dsPIC33E CPU • Code-Efficient C and Assembly Architecture • Two 40-Bit Wide Accumulators • Single-Cycle MAC/MPY with Dual Data Fetch • Single-Cycle Mixed-Sign MUL Plus Hardware Divide • 32-Bit Multiply Support • Two Additional Working Register Sets reduces context switching Clock Management • Internal Oscillator • Programmable PLLs and Oscillator Clock Sources • Fail-Safe Clock Monitor FSCM • Independent Watchdog Timer WDT • Fast Wake-up and Start-up Power Management • Low-Power Management modes Sleep, Idle, Doze • Integrated Power-on Reset and Brown-out Reset • mA/MHz Dynamic Current typical • 10 uA IPD Current typical High-Speed PWM • Five PWM Generators two outputs per generator • Individual Time Base and Duty Cycle for each PWM • ns PWM Resolution frequency, duty cycle, dead time and phase • Supports Center-Aligned, Redundant, Complementary and True Independent Output modes • Independent Fault and Current-Limit Inputs • Output Override Control • PWM Support for AC/DC, DC/DC, Inverters, PFC and Lighting Advanced Analog Features • High-Speed ADC module - 12-bit with 4 dedicated SAR ADC cores and one shared SAR ADC core - Configurable resolution up to 12-bit for each ADC core - Up to Msps conversion rate per channel at 12-bit resolution - 12 to 22 single-ended inputs - Dedicated result buffer for each analog channel - Flexible and independent ADC trigger sources - Two digital comparators - Two oversampling filters for increased resolution • Four Rail-to-Rail Comparators with Hysteresis - Dedicated 12-bit Digital-to-Analog Converter DAC for each analog comparator - Up to two DAC reference outputs - Up to two external reference inputs • Two Programmable Gain Amplifiers - Single-ended or independent ground reference - Five selectable gains 4x, 8x, 16x, 32x and 64x - 40 MHz gain bandwidth Interconnected SMPS Peripherals • Reduces CPU Interaction to Improve Performance • Flexible PWM Trigger Options for ADC Conversions • High-Speed Comparator Truncates PWM 15 ns typical - Supports Cycle-by-Cycle Current mode control - Current Reset mode variable frequency Timers/Output Compare/Input Capture • Five 16-Bit and up to Two 32-Bit Timers/Counters • Four Output Compare OC modules, Configurable as Timers/Counters • Four Input Capture IC modules 2013-2015 Microchip Technology Inc. DS70005127C-page 1 dsPIC33EPXXGS50X FAMILY Communication Interfaces • Two UART modules 15 Mbps - Supports LIN/J2602 protocols and • Two 4-Wire SPI modules 15 Mbps • Two I2C modules up to 1 Mbaud with SMBus Support Input/Output • Constant-Current Source 10 µA nominal • Sink/Source up to 12mA/15mA, respectively; Pin-Specific for Standard VOH/VOL • 5V Tolerant Pins • Selectable, Open-Drain Pull-ups and Pull-Downs • External Interrupts on All I/O Pins • Peripheral Pin Select PPS to allow Function On dsPIC33EPXXGS50X devices, overhead-free circular buffers Modulo Addressing are supported in both X and Y address spaces. The Modulo Addressing removes the software boundary checking overhead for DSP algorithms. The X AGU Circular Addressing can be used with any of the MCU class of instructions. The X AGU also supports Bit-Reversed Addressing to greatly simplify input or output data re-ordering for radix-2 FFT algorithms. Addressing Modes The CPU supports these addressing modes: • Inherent no operand • Relative • Literal • Memory Direct • Register Direct • Register Indirect Each instruction is associated with a predefined addressing mode group, depending upon its functional requirements. As many as six addressing modes are supported for each instruction. 2013-2015 Microchip Technology Inc. DS70005127C-page 21 dsPIC33EPXXGS50X FAMILY FIGURE 3-1: dsPIC33EPXXGS50X FAMILY CPU BLOCK DIAGRAM X Address Bus Y Data Bus X Data Bus Interrupt Controller PSV and Table Data Access 24 Control Block Data Latch Data Latch Y Data RAM X Data RAM Address Address Latch Latch 24 Address Latch PCU PCH PCL Program Counter Stack Control Logic Loop Control Logic Y Address Bus X RAGU 16 X WAGU Program Memory Y AGU Data Latch EA MUX 16 24 ROM Latch IR Literal Data 16-Bit Working Register Arrays DSP Engine Divide Support Bit-Reversed Addressing mode is intended to simplify data reordering for radix-2 FFT algorithms. It is supported by the X AGU for data writes only. BIT-REVERSED ADDRESSING IMPLEMENTATION Bit-Reversed Addressing mode is enabled when all of these situations are met: • BWMx bits W register selection in the MODCON register are any value other than ‘1111’ the stack cannot be accessed using Bit-Reversed Addressing • The BREN bit is set in the XBREV register • The addressing mode used is Register Indirect with Pre-Increment or Post-Increment If the length of a bit-reversed buffer is M = 2N bytes, the last ‘N’ bits of the data buffer start address must be zeros. XB<14:0> is the Bit-Reversed Addressing modifier, or ‘pivot point’, which is typically a constant. In the case of an FFT computation, its value is equal to half of the FFT data buffer size. Note: All bit-reversed EA calculations assume word-sized data LSb of every EA is always clear . The XB value is scaled accordingly to generate compatible byte addresses. When enabled, Bit-Reversed Addressing is executed only for Register Indirect with Pre-Increment or PostIncrement Addressing and word-sized data writes. It does not function for any other addressing mode or for byte-sized data and normal addresses are generated instead. When Bit-Reversed Addressing is active, the W Address Pointer is always added to the address modifier XB and the offset associated with the Register Indirect Addressing mode is ignored. In addition, as word-sized data is a requirement, the LSb of the EA is ignored and always clear . Note: Modulo Addressing and Bit-Reversed Addressing can be enabled simultaneously using the same W register, but BitReversed Addressing operation will always take precedence for data writes when enabled. If Bit-Reversed Addressing has already been enabled by setting the BREN XBREV<15> bit, a write to the XBREV register should not be immediately followed by an indirect read operation using the W register that has been designated as the Bit-Reversed Pointer. 2013-2015 Microchip Technology Inc. DS70005127C-page 73 dsPIC33EPXXGS50X FAMILY FIGURE 4-13: BIT-REVERSED ADDRESSING EXAMPLE Sequential Address b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 0 Bit Locations Swapped Left-to-Right Around Center of Binary Value b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b1 b2 b3 b4 0 Bit-Reversed Address Pivot Point XB = 0x0008 for a 16-Word Bit-Reversed Buffer TABLE 4-39: BIT-REVERSED ADDRESSING SEQUENCE 16-ENTRY Normal Address Bit-Reversed Address Decimal Decimal DS70005127C-page 74 2013-2015 Microchip Technology Inc. dsPIC33EPXXGS50X FAMILY Interfacing Program and Data Memory Spaces The dsPIC33EPXXGS50X family architecture uses a 24-bit wide Program Space PS and a 16-bit wide Data Space DS . The architecture is also a modified Harvard scheme, meaning that data can also be present in the Program Space. To use this data successfully, it must be accessed in a way that preserves the alignment of information in both spaces. Aside from normal execution, the architecture of the dsPIC33EPXXGS50X family devices provides two methods by which Program Space can be accessed during operation: • Using table instructions to access individual bytes or words anywhere in the Program Space • Remapping a portion of the Program Space into the Data Space Program Space Visibility Table instructions allow an application to read or write to small areas of the program memory. This capability makes the method ideal for accessing data tables that need to be updated periodically. It also allows access to all bytes of the program word. The remapping method allows an application to access a large block of data on a read-only basis, which is ideal for look-ups from a large table of static data. The application can only access the least significant word of the program word. TABLE 4-40 PROGRAM SPACE ADDRESS CONSTRUCTION Access Type • Business of Microchip Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE To register, access the Microchip web site at Under “Support”, click on “Customer Change Notification” and follow the registration instructions. CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels: • Distributor or Representative • Local Sales Office • Field Application Engineer FAE • Technical Support Customers should contact their distributor, representative or Field Application Engineer FAE for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: 2013-2015 Microchip Technology Inc. DS70005127C-page 385 dsPIC33EPXXGS50X FAMILY DS70005127C-page 386 2013-2015 Microchip Technology Inc. dsPIC33EPXXGS50X FAMILY PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. dsPIC 33 EP 64 GS5 04 T - I / PT XXX Microchip Trademark Architecture Flash Memory Family Program Memory Size Kbyte Product Group Pin Count Tape and Reel Flag if applicable Temperature Range Package Pattern Examples: dsPIC33EP64GS504-I/PT dsPIC33, Enhanced Performance, 64-Kbyte Program Memory, SMPS, 44-Pin, Industrial Temperature, TQFP Package. Architecture: 33 = 16-Bit Digital Signal Controller Flash Memory Family EP = Enhanced Performance Product Group: GS = SMPS Family Pin Count: 02 = 28-pin 04 = 44-pin 05 = 48-pin 06 = 64-pin Temperature Range: I = -40C to +85C Industrial E = -40C to +125C Extended Package: ML = Plastic Quad, No Lead Package 44-pin 8x8 mm body QFN MM = Plastic Quad, No Lead Package 28-pin 6x6 mm body QFN-S MX = Plastic Quad Flat, No Lead Package 28-pin 6x6 mm body UQFN PT = Plastic Thin Quad Flatpack 44-pin 10x10 mm body TQFP PT = Plastic Thin Quad Flatpack 48-pin 7x7 mm body TQFP PT = Plastic Thin Quad Flatpack 64-pin 10x10 mm body TQFP SO = Plastic Small Outline, Wide 28-pin mm body SOIC 2013-2015 Microchip Technology Inc. DS70005127C-page 387 dsPIC33EPXXGS50X FAMILY DS70005127C-page 388 2013-2015 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

PDF Datasheet Preview

dsPIC33EPXXGS50X FAMILY
16-Bit Digital Signal Controllers for Digital Power Applications with Interconnected High-Speed PWM, ADC, PGA and Comparators

Operating Conditions
• 3.0V to 3.6V, -40°C to +85°C, DC to 70 MIPS
• 3.0V to 3.6V, -40°C to +125°C, DC to 60 MIPS

Flash Architecture
• Dual Partition Flash Program Memory with Live Update 64-Kbyte devices - Supports programming while operating - Supports partition soft swap

Core 16-Bit dsPIC33E CPU
• Code-Efficient C and Assembly Architecture
• Two 40-Bit Wide Accumulators
• Single-Cycle MAC/MPY with Dual Data Fetch
• Single-Cycle Mixed-Sign MUL Plus

Hardware Divide
• 32-Bit Multiply Support
• Two Additional Working Register Sets reduces
context switching

Clock Management
• Internal Oscillator
• Programmable PLLs and Oscillator Clock Sources
• Fail-Safe Clock Monitor FSCM
• Independent Watchdog Timer WDT
• Fast Wake-up and Start-up

Power Management
• Low-Power Management modes Sleep, Idle, Doze
• Integrated Power-on Reset and Brown-out Reset
• mA/MHz Dynamic Current typical
• 10 uA IPD Current typical

High-Speed PWM
• Five PWM Generators two outputs per generator
• Individual Time Base and Duty Cycle for each PWM
• ns PWM Resolution frequency, duty cycle,
dead time and phase
• Supports Center-Aligned, Redundant, Complementary
and True Independent Output modes
• Independent Fault and Current-Limit Inputs
• Output Override Control
• PWM Support for AC/DC, DC/DC, Inverters, PFC
and Lighting

Advanced Analog Features
• High-Speed ADC module - 12-bit with 4 dedicated SAR ADC cores and one shared SAR ADC core - Configurable resolution up to 12-bit for each ADC core - Up to Msps conversion rate per channel at 12-bit resolution - 12 to 22 single-ended inputs - Dedicated result buffer for each analog channel - Flexible and independent ADC trigger sources - Two digital comparators - Two oversampling filters for increased resolution
• Four Rail-to-Rail Comparators with Hysteresis - Dedicated 12-bit Digital-to-Analog Converter DAC for each analog comparator - Up to two DAC reference outputs - Up to two external reference inputs
• Two Programmable Gain Amplifiers - Single-ended or independent ground reference - Five selectable gains 4x, 8x, 16x, 32x and 64x - 40 MHz gain bandwidth

Interconnected SMPS Peripherals
• Reduces CPU Interaction to Improve Performance
• Flexible PWM Trigger Options for

ADC Conversions
• High-Speed Comparator Truncates PWM
15 ns typical - Supports Cycle-by-Cycle Current mode control - Current Reset mode variable frequency

Timers/Output Compare/Input Capture
• Five 16-Bit and up to Two 32-Bit Timers/Counters
• Four Output Compare OC modules, Configurable
as Timers/Counters
• Four Input Capture IC modules
2013-2015 Microchip Technology Inc.

DS70005127C-page 1
dsPIC33EPXXGS50X FAMILY

Communication Interfaces
• Two UART modules 15 Mbps - Supports LIN/J2602 protocols and
• Two 4-Wire SPI modules 15 Mbps
• Two I2C modules up to 1 Mbaud with SMBus

Support

Input/Output
• Constant-Current Source 10 µA nominal
• Sink/Source up to 12mA/15mA, respectively;

Pin-Specific for Standard VOH/VOL
• 5V Tolerant Pins
• Selectable, Open-Drain Pull-ups and Pull-Downs
• External Interrupts on All I/O Pins
• Peripheral Pin Select PPS to allow Function
On dsPIC33EPXXGS50X devices, overhead-free circular buffers Modulo Addressing are supported in both X and Y address spaces. The Modulo Addressing removes the software boundary checking overhead for DSP algorithms. The X AGU Circular Addressing can be used with any of the MCU class of instructions. The X AGU also supports Bit-Reversed Addressing to greatly simplify input or output data re-ordering for radix-2 FFT algorithms.

Addressing Modes

The CPU supports these addressing modes:
• Inherent no operand
• Relative
• Literal
• Memory Direct
• Register Direct
• Register Indirect

Each instruction is associated with a predefined addressing mode group, depending upon its functional requirements. As many as six addressing modes are supported for each instruction.
2013-2015 Microchip Technology Inc.

DS70005127C-page 21
dsPIC33EPXXGS50X FAMILY

FIGURE 3-1:
dsPIC33EPXXGS50X FAMILY CPU BLOCK DIAGRAM

X Address Bus

Y Data Bus

X Data Bus

Interrupt Controller

PSV and Table

Data Access 24 Control Block

Data Latch Data Latch

Y Data RAM

X Data RAM

Address

Address

Latch

Latch
24 Address Latch

PCU PCH PCL

Program Counter

Stack Control Logic

Loop Control Logic

Y Address Bus

X RAGU 16 X WAGU

Program Memory

Y AGU

Data Latch

EA MUX
16 24

ROM Latch IR

Literal Data
16-Bit

Working Register Arrays

DSP Engine

Divide Support
Bit-Reversed Addressing mode is intended to simplify data reordering for radix-2 FFT algorithms. It is supported by the X AGU for data writes only.

BIT-REVERSED ADDRESSING IMPLEMENTATION

Bit-Reversed Addressing mode is enabled when all of these situations are met:
• BWMx bits W register selection in the MODCON register are any value other than ‘1111’ the stack cannot be accessed using Bit-Reversed Addressing
• The BREN bit is set in the XBREV register
• The addressing mode used is Register Indirect with Pre-Increment or Post-Increment

If the length of a bit-reversed buffer is M = 2N bytes, the last ‘N’ bits of the data buffer start address must be zeros.

XB<14:0> is the Bit-Reversed Addressing modifier, or ‘pivot point’, which is typically a constant. In the case of an FFT computation, its value is equal to half of the FFT data buffer size.

Note:

All bit-reversed EA calculations assume word-sized data LSb of every EA is always clear . The XB value is scaled accordingly to generate compatible byte addresses.

When enabled, Bit-Reversed Addressing is executed only for Register Indirect with Pre-Increment or PostIncrement Addressing and word-sized data writes. It does not function for any other addressing mode or for byte-sized data and normal addresses are generated instead. When Bit-Reversed Addressing is active, the W Address Pointer is always added to the address modifier XB and the offset associated with the Register Indirect Addressing mode is ignored. In addition, as word-sized data is a requirement, the LSb of the EA is ignored and always clear .

Note:

Modulo Addressing and Bit-Reversed Addressing can be enabled simultaneously using the same W register, but BitReversed Addressing operation will always take precedence for data writes when enabled.

If Bit-Reversed Addressing has already been enabled by setting the BREN XBREV<15> bit, a write to the XBREV register should not be immediately followed by an indirect read operation using the W register that has been designated as the Bit-Reversed Pointer.
2013-2015 Microchip Technology Inc.

DS70005127C-page 73
dsPIC33EPXXGS50X FAMILY

FIGURE 4-13:

BIT-REVERSED ADDRESSING EXAMPLE

Sequential Address b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 0

Bit Locations Swapped Left-to-Right Around Center of Binary Value
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b1 b2 b3 b4 0 Bit-Reversed Address

Pivot Point

XB = 0x0008 for a 16-Word Bit-Reversed Buffer

TABLE 4-39:

BIT-REVERSED ADDRESSING SEQUENCE 16-ENTRY

Normal Address

Bit-Reversed Address

Decimal

Decimal

DS70005127C-page 74
2013-2015 Microchip Technology Inc.
dsPIC33EPXXGS50X FAMILY

Interfacing Program and Data Memory Spaces

The dsPIC33EPXXGS50X family architecture uses a 24-bit wide Program Space PS and a 16-bit wide Data Space DS . The architecture is also a modified Harvard scheme, meaning that data can also be present in the Program Space. To use this data successfully, it must be accessed in a way that preserves the alignment of information in both spaces.

Aside from normal execution, the architecture of the dsPIC33EPXXGS50X family devices provides two methods by which Program Space can be accessed during operation:
• Using table instructions to access individual bytes or words anywhere in the Program Space
• Remapping a portion of the Program Space into the Data Space Program Space Visibility

Table instructions allow an application to read or write to small areas of the program memory. This capability makes the method ideal for accessing data tables that need to be updated periodically. It also allows access to all bytes of the program word. The remapping method allows an application to access a large block of data on a read-only basis, which is ideal for look-ups from a large table of static data. The application can only access the least significant word of the program word.

TABLE 4-40 PROGRAM SPACE ADDRESS CONSTRUCTION

Access Type
• Business of Microchip Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives

CUSTOMER CHANGE NOTIFICATION SERVICE

To register, access the Microchip web site at Under “Support”, click on “Customer Change Notification” and follow the registration instructions.

CUSTOMER SUPPORT

Users of Microchip products can receive assistance through several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer FAE
• Technical Support

Customers should contact their distributor, representative or Field Application Engineer FAE for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document.

Technical support is available through the web site at:
2013-2015 Microchip Technology Inc.

DS70005127C-page 385
dsPIC33EPXXGS50X FAMILY

DS70005127C-page 386
2013-2015 Microchip Technology Inc.
dsPIC33EPXXGS50X FAMILY

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
dsPIC 33 EP 64 GS5 04 T - I / PT XXX

Microchip Trademark Architecture Flash Memory Family Program Memory Size Kbyte Product Group Pin Count Tape and Reel Flag if applicable Temperature Range Package Pattern

Examples:
dsPIC33EP64GS504-I/PT dsPIC33, Enhanced Performance, 64-Kbyte Program Memory, SMPS, 44-Pin, Industrial Temperature, TQFP Package.

Architecture:
33 = 16-Bit Digital Signal Controller

Flash Memory Family EP = Enhanced Performance

Product Group:

GS = SMPS Family

Pin Count:
02 = 28-pin 04 = 44-pin
05 = 48-pin 06 = 64-pin

Temperature Range:

I = -40C to +85C Industrial E = -40C to +125C Extended

Package:

ML = Plastic Quad, No Lead Package 44-pin 8x8 mm body QFN

MM = Plastic Quad, No Lead Package 28-pin 6x6 mm body QFN-S MX = Plastic Quad Flat, No Lead Package 28-pin 6x6 mm body UQFN PT = Plastic Thin Quad Flatpack 44-pin 10x10 mm body TQFP

PT = Plastic Thin Quad Flatpack 48-pin 7x7 mm body TQFP PT = Plastic Thin Quad Flatpack 64-pin 10x10 mm body TQFP SO = Plastic Small Outline, Wide 28-pin mm body SOIC
2013-2015 Microchip Technology Inc.

DS70005127C-page 387
dsPIC33EPXXGS50X FAMILY

DS70005127C-page 388
2013-2015 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived DSPIC33EP64GS502-E/MX Datasheet file may be downloaded here without warranties.

Datasheet ID: DSPIC33EP64GS502-E/MX 648102