SY87813LHG-TR

SY87813LHG-TR Datasheet

SY87813L

Part	Datasheet
SY87813LHG-TR	SY87813LHG-TR (pdf)

Related Parts	Information
SY87813LHG	SY87813LHG

PDF Datasheet Preview
SY87813L 3.3V, 28Mbps to 1.3Gbps Clock and Data Recovery The SY87813L is a complete clock recovery and data retiming integrated circuit for data rates from 28Mbps up to 1.3Gbps NRZ. The device is ideally suited for SONET/SDH/ATM and Fibre Channel applications and other high-speed data transmission systems. Clock recovery and data retiming is performed by synchronizing the on-chip VCO directly to the incoming data stream. The VCO center frequency is controlled by the reference clock frequency and the selected divide ratio. On-chip clock generation is performed through the use of a frequency multiplier PLL with a byte rate source as reference. The SY87813L also includes a link fault detection circuit. Datasheets and support documentation can be found on Micrel’s web site at: • 3.3V power supply • SONET/SDH/ATM compatible • Clock and data recovery from 28Mbps up to 1.3Gbps NRZ data stream clock generation from 28MHz to 1.3GHz • Two on-chip PLLs one for clock generation and another for clock recovery • Selectable reference frequencies • Differential PECL high-speed serial I/O • Line receiver input no external buffering needed • Link fault indication • 100K ECL-compatible I/O • Industrial temperature range to +85°C • Available in 32-pin EPAD-TQFP • SONET/SDH/ATM OC-1 and OC-3, OC-12, OC-24 • Fibre Channel, ESCON, SMPTE 259 • Gigabit Ethernet/Fast Ethernet • Proprietary architecture up to 1.3Gbps • CEPT E-3/E-4/E-5 Markets • Telecom/Datacom • Fiber optics • Storage networks AnyRate is a registered trademark of Micrel, Inc. Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 408 944-0800 • fax + 1 408 474-1000 • November 2006 M9999-112806-B or 408 955-1690 Micrel, Inc. Ordering Information 1 Package Type Operating Range Package Marking SY87813LHG SY87813LHGTR 2 H32-1 H32-1 Industrial SY87813LHG with Pb-Free bar-line indicator SY87813LHG with Pb-Free bar-line indicator Notes Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC Electricals only. Tape and Reel. Pin Configuration SY87813L Lead Finish NiPdAu Pb-Free NiPdAu Pb-Free 32-Pin EPAD-TQFP H32-1 November 2006 M9999-112806-B or 408 955-1690 Micrel, Inc. SY87813L Pin Description Pin Number Pin Name Pin Name REFCLKSEL REFCLK Select TTL Input . This input selects the single-ended TTL REFCLK input or the differential PECL REFCLKP/REFCLKN inputs. REFCLKSEL = HIGH selects PECL inputs. RDINP, Serial Data Input. Differential PECL These built-in line receiver inputs are connected to the RDINN differential receive serial data stream. An internal receive PLL recovers the embedded clock RCLK and data RDOUT information. The incoming data rate can be within one of eight frequency ranges depending upon the state of the FREQSEL pins. See “Frequency Selection” Table. FREQSEL1 Frequency Select. TTL Inputs These inputs select the output clock frequency range as FREQSEL2 shown in the “Frequency Selection” Table. FREQSEL3 REFCLK, Reference Clock. Input These inputs are used as the reference for the internal frequency REFCLKP, synthesizer and the “training” frequency for the receiver PLL to keep it centered in the REFCLKN absence of data coming in on the RDIN inputs. REFCLK is single-ended TTL and REFCLKP and REFCLKN are differential PECL inputs selected by the REFCLKSEL pin Carrier Detect. PECL Input This input controls the recovery function of the Receive PLL and can be driven by the carrier detect output of optical modules or from external transition detection circuitry. When this input is HIGH, the input data stream RDIN is recovered normally by the Receive PLL. When this input is LOW the data on the inputs RDIN will be

PDF Datasheet Preview

SY87813L
3.3V, 28Mbps to 1.3Gbps Clock and Data Recovery

The SY87813L is a complete clock recovery and data retiming integrated circuit for data rates from 28Mbps up to 1.3Gbps NRZ. The device is ideally suited for SONET/SDH/ATM and Fibre Channel applications and other high-speed data transmission systems.

Clock recovery and data retiming is performed by synchronizing the on-chip VCO directly to the incoming data stream. The VCO center frequency is controlled by the reference clock frequency and the selected divide ratio. On-chip clock generation is performed through the use of a frequency multiplier PLL with a byte rate source as reference.

The SY87813L also includes a link fault detection circuit.

Datasheets and support documentation can be found on Micrel’s web site at:
• 3.3V power supply
• SONET/SDH/ATM compatible
• Clock and data recovery from 28Mbps up to 1.3Gbps

NRZ data stream clock generation from 28MHz to 1.3GHz
• Two on-chip PLLs one for clock generation and another for clock recovery
• Selectable reference frequencies
• Differential PECL high-speed serial I/O
• Line receiver input no external buffering needed
• Link fault indication
• 100K ECL-compatible I/O
• Industrial temperature range to +85°C
• Available in 32-pin EPAD-TQFP
• SONET/SDH/ATM OC-1 and OC-3, OC-12, OC-24
• Fibre Channel, ESCON, SMPTE 259
• Gigabit Ethernet/Fast Ethernet
• Proprietary architecture up to 1.3Gbps
• CEPT E-3/E-4/E-5

Markets
• Telecom/Datacom
• Fiber optics
• Storage networks

AnyRate is a registered trademark of Micrel, Inc.

Micrel Inc.
• 2180 Fortune Drive
• San Jose, CA 95131
• USA
• tel +1 408 944-0800
• fax + 1 408 474-1000
•

November 2006

M9999-112806-B or 408 955-1690

Micrel, Inc.
Ordering Information 1

Package Type

Operating Range

Package Marking

SY87813LHG SY87813LHGTR 2

H32-1 H32-1

Industrial

SY87813LHG with Pb-Free bar-line indicator

SY87813LHG with Pb-Free bar-line indicator

Notes Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC Electricals only. Tape and Reel.

Pin Configuration

SY87813L

Lead Finish NiPdAu Pb-Free NiPdAu Pb-Free
32-Pin EPAD-TQFP H32-1

November 2006

M9999-112806-B
or 408 955-1690

Micrel, Inc.

SY87813L

Pin Description

Pin Number Pin Name Pin Name

REFCLKSEL REFCLK Select TTL Input . This input selects the single-ended TTL REFCLK input or the
differential PECL REFCLKP/REFCLKN inputs. REFCLKSEL = HIGH selects PECL inputs.

RDINP,

Serial Data Input. Differential PECL These built-in line receiver inputs are connected to the

RDINN
differential receive serial data stream. An internal receive PLL recovers the embedded clock

RCLK and data RDOUT information. The incoming data rate can be within one of eight
frequency ranges depending upon the state of the FREQSEL pins. See “Frequency

Selection” Table.

FREQSEL1 Frequency Select. TTL Inputs These inputs select the output clock frequency range as

FREQSEL2 shown in the “Frequency Selection” Table.

FREQSEL3

REFCLK, Reference Clock. Input These inputs are used as the reference for the internal frequency

REFCLKP, synthesizer and the “training” frequency for the receiver PLL to keep it centered in the

REFCLKN absence of data coming in on the RDIN inputs. REFCLK is single-ended TTL and REFCLKP
and REFCLKN are differential PECL inputs selected by the REFCLKSEL pin

Carrier Detect. PECL Input This input controls the recovery function of the Receive PLL and
can be driven by the carrier detect output of optical modules or from external transition
detection circuitry. When this input is HIGH, the input data stream RDIN is recovered
normally by the Receive PLL. When this input is LOW the data on the inputs RDIN will be

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived SY87813LHG-TR Datasheet file may be downloaded here without warranties.

Datasheet ID: SY87813LHG-TR 647948