SY58038UMG

SY58038UMG Datasheet

SY58038U

Part	Datasheet
SY58038UMG	SY58038UMG (pdf)

Related Parts	Information
SY58038UMG TR	SY58038UMG TR

PDF Datasheet Preview
Micrel, Inc. ULTRA PRECISION 8:1 MUX WITH INTERNAL TERMINATION AND 1:2 LVPECL FANOUT BUFFER Precision Precision SY58038U s Selects between 1 of 8 inputs, and provides 2 precision, low skew LVPECL output copies s Guaranteed AC performance over temperature and voltage: • DC to 4.5Gbps throughput • <500ps propagation delay IN-to-Q VIN 100mV • <100ps tr / tf time • <15ps skew output-to-output s Unique, patent-pending, channel-to-channel isolation design provides superior crosstalk performance s Ultra-low jitter design • <1psRMS random jitter • <10psPP deterministic jitter • <10psPP total jitter clock • <1psRMS cycle-to-cycle jitter • <0.7psRMS crosstalk-induced jitter s Unique, patent-pending, input termination and VT pin accepts DC- and AC-coupled inputs CML, PECL, LVDS s 800mV LVPECL output swing s Power supply 2.5V ±5% or 3.3V ±10% s to +85°C temperature range s Available in 44-pin 7mm x 7mm MLF package Precision The SY58038U is a low jitter, low skew, high-speed 8:1 multiplexer with a 1:2 differential fanout buffer optimized for precision telecom and enterprise server distribution applications. The SY58038U distributes clock frequencies from DC to 3.5GHz, and data rates to 4.5Gpbs guaranteed over temperature and voltage. The SY58038U differential input includes Micrel’s unique, 3-pin input termination architecture that directly interfaces to any differential signal AC- or DC-coupled as small as 100mV without any level shifting or termination resistor networks in the signal path. The outputs are 800mV, 100K compatible LVPECL with extremely fast rise/fall times guaranteed to be less than 100ps. The SY58038U features a patent-pending isolation design that significantly improves channel-to-channel crosstalk performance. The SY58038U operates from a 2.5V ±5% or 3.3V ±10% supply and is guaranteed over the full industrial temperature range of to +85°C. The SY58038U is part of Micrel’s high-speed, Precision product line. Data sheets and support documentation can be found on Micrel’s web site at s Data communication systems s All SONET/SDH data/clock applications s All Fibre Channel applications s All Gigabit Ethernet applications Precision Edge is a registered trademark of Micrel, Inc. MLF and MicroLeadFrame are trademarks of Amkor Technology, Inc. M9999-051305 or 408 955-1690 Micrel, Inc. FUNCTIONAL BLOCK DIAGRAM /IN0 VREF-AC0 /IN1 /IN2 VREF-AC1 /IN3 /IN4 VREF-AC2 /IN5 /IN6 VREF-AC3 /IN7 SEL0 CMOS/TTL SEL1 CMOS/TTL SEL3 CMOS/TTL Precision SY58038U 8:1 MUX 0 1 2 3 4 MUX PACKAGE/ORDERING INFORMATION VT5 /IN5 /IN6 VT6 /IN6 VREF-AC3 IN7 VT7 /IN7 SEL2 NC IN5 VREF-AC2 /IN4 VT4 IN4 NC /IN3 VT3 IN3 VREF-AC1 /IN2 44 43 42 41 40 39 38 37 36 35 34 12 13 14 15 16 17 18 19 20 21 22 GND VCC /Q1 VCC GND VCC /Q0 VCC GND Ordering Information 1 Part Number SY58038UMI SY58038UMITR 2 SY58038UMG Package Type MLF-44 MLF-44 MLF-44 Operating Range Industrial SY58038UMGTR 2 MLF-44 Industrial Package Marking SY58038U SY58038U with Pb-Free bar-line indicator SY58038U with Pb-Free bar-line indicator Lead Finish Sn-Pb Sn-Pb-Free NiPdAu Pb-Free NiPdAu Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC electricals only. Tape and Reel. VT2 IN2 /IN1 VT1 IN1 VREF-AC0 /IN0 VT0 IN0 SEL1 SEL2 44-Pin MLF-44 PIN DESCRIPTION Pin Number 20, 18, 16, 14, 13, 11, 9, 7, 5, 3, 1, 43, 42, 40, 38, 36 19,15, 12, 8, 4, 44, 41, 37 17, 10, 2 39 21, 22, 35 24, 27, 29, 32 25, 26, 30, 31 23, 28, 33 Pin Name IN0, /IN0, IN1, /IN1, IN2, /IN2, IN3, /IN3, IN4, /IN4, IN5,/IN5, IN6, /IN6, IN7, /IN7 VT0, VT1 VT2, VT3, VT4, VT5, VT6, VT7 VREF-AC0, VREF-AC1, VREF-AC2, VREF-AC3 SEL0, SEL1, SEL2 Q0,/Q0, Q1,/Q1 GND, Exposed Pad Pin Function Differential Inputs These input pairs are the differential signal inputs to the device. Inputs accept AC or DC-coupled signals as small as 100mV. Each pin of a pair internally terminates to a VT pin through Note that these inputs will default to an indeterminate state if left open. Please refer to the “Input Interface Applications” section for more details. Input Termination Center-Tap Each side of the differential input pair terminates to a VT pin. The VT pins provide a center-tap to a termination network for maximum interface flexibility. See “Input Interface Applications” section for more details. For a CML or LVDS inputs, the VT pin is left floating. Reference Voltage This output biases to It is used when AC coupling the inputs IN, /IN . For AC-coupled applications, connect VREF_AC to the VT pin and bypass with a 0.01µF low ESR capacitor to VCC. See “Input Interface Applications” section for more details. The single-ended TTL/CMOS-compatible inputs select the inputs to the multiplexer. Note that this input is internally connected to a pull-up resistor and will default to a logic HIGH state if left open. Positive Power Supply. Bypass with low ESR capacitors as close to each VCC pin. Differential Outputs These LVPECL output pairs are the outputs of the device. Unused output pairs may be left open. Each output is designed to drive 800mV into terminated to or if AC-coupled . Ground. GND and exposed pad must both be connected to the most negative potential of chip ground. Micrel, Inc. Precision SY58038U Absolute Maximum Ratings 1

PDF Datasheet Preview

Micrel, Inc.

ULTRA PRECISION 8:1 MUX WITH INTERNAL TERMINATION AND 1:2 LVPECL FANOUT BUFFER

Precision

Precision

SY58038U
s Selects between 1 of 8 inputs, and provides 2 precision, low skew LVPECL output copies
s Guaranteed AC performance over temperature and voltage:
• DC to 4.5Gbps throughput
• <500ps propagation delay IN-to-Q VIN 100mV
• <100ps tr / tf time
• <15ps skew output-to-output
s Unique, patent-pending, channel-to-channel isolation design provides superior crosstalk performance
s Ultra-low jitter design
• <1psRMS random jitter
• <10psPP deterministic jitter
• <10psPP total jitter clock
• <1psRMS cycle-to-cycle jitter
• <0.7psRMS crosstalk-induced jitter
s Unique, patent-pending, input termination and VT pin accepts DC- and AC-coupled inputs CML, PECL, LVDS
s 800mV LVPECL output swing
s Power supply 2.5V ±5% or 3.3V ±10%
s to +85°C temperature range
s Available in 44-pin 7mm x 7mm MLF package

Precision

The SY58038U is a low jitter, low skew, high-speed 8:1 multiplexer with a 1:2 differential fanout buffer optimized for precision telecom and enterprise server distribution applications. The SY58038U distributes clock frequencies from DC to 3.5GHz, and data rates to 4.5Gpbs guaranteed over temperature and voltage.

The SY58038U differential input includes Micrel’s unique, 3-pin input termination architecture that directly interfaces to any differential signal AC- or DC-coupled as small as 100mV without any level shifting or termination resistor networks in the signal path. The outputs are 800mV, 100K compatible LVPECL with extremely fast rise/fall times guaranteed to be less than 100ps.

The SY58038U features a patent-pending isolation design that significantly improves channel-to-channel crosstalk performance.

The SY58038U operates from a 2.5V ±5% or 3.3V ±10% supply and is guaranteed over the full industrial temperature range of to +85°C. The SY58038U is part of Micrel’s high-speed, Precision product line.

Data sheets and support documentation can be found on Micrel’s web site at
s Data communication systems s All SONET/SDH data/clock applications s All Fibre Channel applications s All Gigabit Ethernet applications

Precision Edge is a registered trademark of Micrel, Inc. MLF and MicroLeadFrame are trademarks of Amkor Technology, Inc.

M9999-051305
or 408 955-1690

Micrel, Inc.

FUNCTIONAL BLOCK DIAGRAM
/IN0 VREF-AC0
/IN1
/IN2 VREF-AC1
/IN3
/IN4 VREF-AC2
/IN5
/IN6 VREF-AC3
/IN7

SEL0 CMOS/TTL

SEL1 CMOS/TTL

SEL3 CMOS/TTL

Precision SY58038U
8:1 MUX
0 1 2 3 4 MUX
PACKAGE/ORDERING INFORMATION

VT5 /IN5 /IN6 VT6 /IN6 VREF-AC3 IN7 VT7 /IN7 SEL2 NC

IN5 VREF-AC2
/IN4 VT4 IN4 NC /IN3 VT3 IN3 VREF-AC1 /IN2
44 43 42 41 40 39 38 37 36 35 34
12 13 14 15 16 17 18 19 20 21 22

GND VCC /Q1 VCC GND VCC /Q0 VCC GND
Ordering Information 1

Part Number SY58038UMI SY58038UMITR 2 SY58038UMG

Package Type

MLF-44 MLF-44 MLF-44

Operating Range

Industrial

SY58038UMGTR 2 MLF-44 Industrial

Package Marking

SY58038U

SY58038U with Pb-Free bar-line indicator

SY58038U with Pb-Free bar-line indicator

Lead Finish

Sn-Pb

Sn-Pb-Free NiPdAu

Pb-Free NiPdAu

Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC electricals only. Tape and Reel.

VT2 IN2 /IN1 VT1 IN1 VREF-AC0 /IN0 VT0 IN0 SEL1 SEL2
44-Pin MLF-44

PIN DESCRIPTION

Pin Number
20, 18, 16, 14, 13, 11,
9, 7, 5, 3, 1, 43, 42, 40, 38, 36
19,15, 12, 8, 4, 44, 41, 37
17, 10, 2 39
21, 22, 35
24, 27, 29, 32
25, 26, 30, 31
23, 28, 33

Pin Name

IN0, /IN0, IN1, /IN1, IN2, /IN2, IN3, /IN3, IN4, /IN4, IN5,/IN5, IN6, /IN6, IN7, /IN7

VT0, VT1 VT2, VT3, VT4, VT5, VT6, VT7

VREF-AC0, VREF-AC1, VREF-AC2, VREF-AC3

SEL0, SEL1, SEL2

Q0,/Q0, Q1,/Q1

GND, Exposed Pad

Pin Function Differential Inputs These input pairs are the differential signal inputs to the device. Inputs accept AC or DC-coupled signals as small as 100mV. Each pin of a pair internally terminates to a VT pin through Note that these inputs will default to an indeterminate state if left open. Please refer to the “Input Interface Applications” section for more details.

Input Termination Center-Tap Each side of the differential input pair terminates to a VT pin. The VT pins provide a center-tap to a termination network for maximum interface flexibility. See “Input Interface Applications” section for more details. For a CML or LVDS inputs, the VT pin is left floating. Reference Voltage This output biases to It is used when AC coupling the inputs IN, /IN . For AC-coupled applications, connect VREF_AC to the VT pin and bypass with a 0.01µF low ESR capacitor to VCC. See “Input Interface Applications” section for more details.

The single-ended TTL/CMOS-compatible inputs select the inputs to the multiplexer. Note that this input is internally connected to a pull-up resistor and will default to a logic HIGH state if left open. Positive Power Supply. Bypass with low ESR capacitors as close to each VCC pin. Differential Outputs These LVPECL output pairs are the outputs of the device. Unused output pairs may be left open. Each output is designed to drive 800mV into terminated to or if AC-coupled . Ground. GND and exposed pad must both be connected to the most negative potential of chip ground.

Micrel, Inc.

Precision SY58038U

Absolute Maximum Ratings 1

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived SY58038UMG Datasheet file may be downloaded here without warranties.

Datasheet ID: SY58038UMG 647941