SY100EL34ZC

SY100EL34ZC Datasheet

ClockWorks SY10EL34/L

Part	Datasheet
SY100EL34ZC	SY100EL34ZC (pdf)

Related Parts	Information
SY10EL34ZC	SY10EL34ZC
SY10EL34ZC-TR	SY10EL34ZC-TR
SY100EL34ZC-TR	SY100EL34ZC-TR

PDF Datasheet Preview
5V/3.3V ÷2, ÷4, ÷8 CLOCK GENERATION CHIP ClockWorks SY10EL34/L SY100EL34/L FINAL s 3.3V and 5V power supply options s 50ps output-to-output skew s Synchronous enable/disable s Master Reset for synchronization s Internal input pull-down resistors s Available in 16-pin SOIC package PIN CONFIGURATION/BLOCK DIAGRAM Q0 1 Q0 2 VCC 3 Q1 4 Q1 5 VCC 6 Q2 7 Q2 8 Q ÷2 R Q ÷4 Q ÷8 16 VCC 15 EN 14 NC 13 CLK 12 CLK 11 VBB 10 MR 9 VEE SOIC TOP VIEW The SY10/100EL34/L are low skew ÷2, ÷4, ÷8 clock generation chips designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The devices can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal. In addition, by using the VBB output, a sinusoidal source can be ACcoupled into the device. If a single-ended input is to be used, the VBB output should be connected to the CLK input and bypassed to ground via a 0.01µF capacitor. The VBB output is designed to act as the switching reference for the input of the EL34/L under single-ended input conditions. As a result, this pin can only source/ sink up to 0.5mA of current. The common enable EN is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. An internal runt pulse could lead to losing synchronization between the internal divider stages. The internal enable flip-flop is clocked on the falling edge of the divider stages. The internal enable flip-flop is clocked on the falling edge of the input clock, therefore, all associated specification limits are referenced to the negative edge of the clock input. Upon start-up, the internal flip-flops will attain a random state the master reset MR input allows for the synchronization of the internal dividers, as well as for multiple EL34/Ls in a system. PIN NAMES Function Differential Clock Inputs Synchronous Enable Master Reset Reference Output Differential ÷2 Outputs Differential ÷4 Outputs Differential ÷8 Outputs Issue Date August, 1998 Micrel TRUTH TABLE NOTE Z = LOW-to-HIGH transition ZZ = HIGH-to-LOW transition Function Divide Hold Reset ClockWorks SY10EL34/L SY100EL34/L DC ELECTRICAL CHARACTERISTICS 1 VEE = VEE Min. to VEE Max. VCC = GND TA = 0°C PRODUCT ORDERING CODE 3.3V Ordering Code SY10EL34LZC Package Type Z16-2 Operating Range Commercial SY10EL34LZCTR Z16-2 Commercial SY100EL34LZC Z16-2 Commercial SY100EL34LZCTR Z16-2 Commercial VEE Range V Ordering Code SY10EL34ZC SY10EL34ZCTR SY100EL34ZC SY100EL34ZCTR Package Type Z16-2 Z16-2 Z16-2 Z16-2 Operating Range Commercial VEE Range V Micrel 16 LEAD SOIC WIDE Z16-2 ClockWorks SY10EL34/L SY100EL34/L MICREL-SYNERGY 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA TEL + 1 408 980-9191 FAX + 1 408 914-7878 WEB This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. 2000 Micrel Incorporated

PDF Datasheet Preview

5V/3.3V ÷2, ÷4, ÷8 CLOCK GENERATION CHIP

ClockWorks SY10EL34/L

SY100EL34/L FINAL
s 3.3V and 5V power supply options s 50ps output-to-output skew s Synchronous enable/disable s Master Reset for synchronization s Internal input pull-down resistors s Available in 16-pin SOIC package

PIN CONFIGURATION/BLOCK DIAGRAM

Q0 1 Q0 2 VCC 3 Q1 4 Q1 5 VCC 6 Q2 7 Q2 8

Q ÷2 R

Q ÷4

Q ÷8
16 VCC 15 EN
14 NC
13 CLK
12 CLK 11 VBB
10 MR
9 VEE

SOIC TOP VIEW

The SY10/100EL34/L are low skew ÷2, ÷4, ÷8 clock generation chips designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The devices can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal. In addition, by using the VBB output, a sinusoidal source can be ACcoupled into the device. If a single-ended input is to be used, the VBB output should be connected to the CLK input and bypassed to ground via a 0.01µF capacitor. The VBB output is designed to act as the switching reference for the input of the EL34/L under single-ended input conditions. As a result, this pin can only source/ sink up to 0.5mA of current.

The common enable EN is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. An internal runt pulse could lead to losing synchronization between the internal divider stages. The internal enable flip-flop is clocked on the falling edge of the divider stages. The internal enable flip-flop is clocked on the falling edge of the input clock, therefore, all associated specification limits are referenced to the negative edge of the clock input.

Upon start-up, the internal flip-flops will attain a random state the master reset MR input allows for the synchronization of the internal dividers, as well as for multiple EL34/Ls in a system.

PIN NAMES

Function

Differential Clock Inputs

Synchronous Enable

Master Reset

Reference Output

Differential ÷2 Outputs

Differential ÷4 Outputs

Differential ÷8 Outputs

Issue Date August, 1998

Micrel

TRUTH TABLE

NOTE Z = LOW-to-HIGH transition ZZ = HIGH-to-LOW transition

Function

Divide

Hold

Reset

ClockWorks SY10EL34/L

SY100EL34/L

DC ELECTRICAL CHARACTERISTICS 1

VEE = VEE Min. to VEE Max. VCC = GND

TA = 0°C
PRODUCT ORDERING CODE
3.3V
Ordering Code

SY10EL34LZC

Package Type

Z16-2

Operating Range

Commercial

SY10EL34LZCTR

Z16-2 Commercial

SY100EL34LZC

Z16-2 Commercial

SY100EL34LZCTR Z16-2 Commercial

VEE Range V
Ordering Code

SY10EL34ZC SY10EL34ZCTR SY100EL34ZC SY100EL34ZCTR

Package Type Z16-2 Z16-2 Z16-2 Z16-2

Operating Range

Commercial

VEE Range V

Micrel
16 LEAD SOIC WIDE Z16-2

ClockWorks SY10EL34/L

SY100EL34/L

MICREL-SYNERGY 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA TEL + 1 408 980-9191 FAX + 1 408 914-7878 WEB

This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. 2000 Micrel Incorporated

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived SY100EL34ZC Datasheet file may be downloaded here without warranties.

Datasheet ID: SY100EL34ZC 647920