TSPC603RVGS12LC

TSPC603RVGS12LC Datasheet


603e RISC Microprocessor Family PID7t-603e TSPC603R

Part Datasheet
TSPC603RVGS12LC TSPC603RVGS12LC TSPC603RVGS12LC (pdf)
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• Superscalar 3 Instructions per Clock Peak
• Dual 16 KB Caches
• Selectable Bus Clock
• 32-bit Compatibility PowerPC Implementation
• On-chip Debug Support
• Nap, Doze and Sleep Power Saving Modes
• Device Offered in Cerquad, CBGA 255, HiTCE CBGA 255 and CI-CGA 255

Features Specific to CBGA 255, HiTCE CBGA 255 and CI-CGA 255
• SPECint95, SPECfp95 at 300 MHz Estimated
• PD Typically = 3.5W 266 MHz , Full Operating Conditions
• Branch Folding
• 64-bit Data Bus 32-bit Data Bus Option
• 4-Gbytes Direct Addressing Range
• Pipelined Single/Double Precision Float Unit
• IEEE 754 Compatible FPU
• IEEE P 1149-1 Test Mode JTAG/C0P
• fINT Max = 300 MHz
• fBUS Max = 75 MHz
• Compatible CMOS Input/TTL Output

Features Specific to Cerquad
• SPECint95, 4 SPECfp95 and 200 MHz Estimated
• PD Typically = 2.5W 200 MHz , Full Operating Conditions

The PID7t-603e implementation of the PowerPC 603e renamed after the 603R is a low-power implementation of the Reduced Instruction Set Computer RISC microprocessor PowerPC family. The 603R is pin-to-pin compatible with the PowerPC 603e and 603P in a Cerquad package. The 603R implements 32-bit effective addresses, integer data types of 8, 16 and 32 bits, and floating-point data types of 32 and 64 bits.

The 603R is a low-power 2.5/3.3V design and provides four software controllable power-saving modes. This device is a superscalar processor capable of issuing and retiring as many as three instructions per clock. Instructions can be executed in any order for increased performance, but, the 603R makes completion appear sequential. It integrates five execution units and is able to execute five instructions in parallel.

The 603R provides independent on-chip, 16-Kbyte, four-way set-associative, physically addressed caches for instructions and data, as well as on-chip instructions, and data Memory Management Units MMUs . The MMUs contain 64-entry, two-way set-associative, data and instruction translation look aside buffers that provide support for demand-paged virtual memory address translation and variable-sized block translation. The 603R has a selectable 32- or 64-bit data bus and a 32-bit address bus. The interface protocol allows multiple masters to compete for system resources through a central external arbiter. The device supports single-beat and burst data transfers for memory accesses, and supports memory-mapped I/Os.
603e RISC Microprocessor Family PID7t-603e TSPC603R

The 603R uses an advanced, 2.5/3.3V CMOS process technology and maintains full interface compatibility with TTL devices. It also integrates in-system testability and debugging features through JTAG boundary-scan capabilities.

Screening/Quality/Packaging

This product is manufactured in full compliance with:
• HiTCE CBGA according to Atmel Standards
• CI-CGA 255 and Cerquad MIL-PRF-38535 class Q or according to Atmel standards
• CBGA 255 Upscreenings based upon Atmel standards
• CBGA, CI-CGA, HiTCE packages:

Full military temperature range TC = -55°C, Tj = +125°C Industrial temperature range TC = -40°C, Tj = +110°C
• Cerquad Full military temperature range TC = -55°C, Tc = +125°C Industrial temperature range TC = -40°C, Tc = +110°C Commercial temperature ranges TC = 0°C, TC = +70°C
• Internal I/O Power Supply = ±5% // 3.3V ±5%

A suffix CERQUAD 240 Ceramic Leaded Chip Carrier

Cavity up

G suffix CBGA 255 Ceramic Ball Grid Array

GS suffix CI-CGA 255 Ceramic Ball Grid Array with Solder Column Interposer SCI

CERQUAD 240

GH suffix HiTCE 255 Ceramic Ball Grid Array
2 TSPC603R

Block Diagram

Figure Block Diagram

Completion Unit

Integer Gen Unit Reg ReUnit name

TSPC603R

Fetch Unit

Dispatch Unit

Branch Unit

Load/ Store Unit

Re- Reg
name File

Float Unit

D MMU 16K Data Cache

I MMU 16K Inst. Cache

Overview

Bus Interface Unit
32b Address

System Bus
64b Data

The 603R is a low-power implementation of the PowerPC microprocessor family of Reduced Instruction Set Computing RISC microprocessors. The 603R implements the 32-bit portion of the PowerPC architecture, which provides 32-bit effective addresses, integer data types of 8, 16 and 32 bits, and floating-point data types of 32 and 64 bits. For 64-bit PowerPC microprocessors, the PowerPC architecture provides 64-bit integer data types, 64-bit addressing, and other features required to complete the 64-bit architecture.
Ordering Information
Ordering Information of the CBGA, CI-CGA and HiTCE Packages

TS X PC603R M G B /Q 12 L C

Prefix

Prototype

Type

Temperature range TC M Tc = -55, Tj = V Tc = -40, Tj =

Package G CBGA GS CI-CGA GH HiTCE CBGA

Bus divider to be confirmed L any bus at 75 MHz

Screening level __ Standard

B/Q MIL-PRF-38535, class Q U Upscreening

Maximum internal processor speed 6 166 MHz 8 200 MHz 10 233 MHz 12 266 MHz 14 300 MHz
Ordering Information of the CERQUAD 240 Package

TS X PC603R M A B /Q 8 L C

Prefix

Prototype

Type

Temperature range TC M -55, V -40, C 0,

Package A CERQUAD

Bus divider to be confirmed L any bus 66 MHz

Maximum internal processor speed 8 200 MHz

Note:

Screening level __ Standard B/Q MIL-PRF-38535, class Q

For availability of the different versions, contact your Atmel sales office.

Definitions

Datasheet Status

Validity

Objective specification Target specification

This datasheet contains target and goal specifications for discussion with the customer and application validation

This datasheet contains target or goal specifications for product development

Before design phase Valid during the design phase

Preliminary specification α site Preliminary specification site

This datasheet contains preliminary data. Additional data may be published at a later date and could include simulation results

This datasheet also contains characterization results

Valid before characterization phase

Valid before the industrialization phase

Product specification Limiting Values

This datasheet contains final product specifications

Valid for production purpose

Limiting values given are in accordance with the Absolute Maximum Rating System IEC Stresses above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application Information

Where application information is given, it is advisory and does not form part of the specification

Life Support Applications

These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Atmel customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Atmel for any damages resulting from such improper use or sale.

Date 07/2005 10/2004

Substantive Change s

Added HiTCE package for PowerPC 603R

This document is a merge of TSPC603R in CBGA255/CI-CGA 255 package ref 2125B and TSPC603R in Cerquad package ref 2127A
54 TSPC603R

TSPC603R

Table of Contents

Features 1 Features Specific to CBGA 255, CBGA HiTCE 255 and CI-CGA 255 1 Features Specific to Cerquad 1 Description 1 2 Screening/Quality/Packaging 2 3 Block Diagram 3 4 Overview 3 5 Signal Description 4 6 Detailed Specifications 5 7 Applicable Documents 5

Design and Construction Absolute Maximum Ratings
16 Ordering Information 53
Ordering Information of the CBGA, CI-CGA and HiTCE Packages Ordering Information of the CERQUAD 240 Package
17 Definitions 54

Life Support Applications
ii TSPC603R

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iv TSPC603R
More datasheets: TSPC603RVGH12LC | TSPC603RVGH8LC | TSPC603RVGS10LC | TSPC603RVGS6LC | TSPC603RVGU6LC | TSPC603RVGU10LC | TSPC603RVGU12LC | TSPC603RVA8LC | TSPC603RVGU14LC | TSPC603RVGU8LC


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Datasheet ID: TSPC603RVGS12LC 519446