TSPC106AVGU66CG

TSPC106AVGU66CG Datasheet

The TSPC106 provides an integrated, high-bandwidth, high-performance, TTL-compatible interface between a 60x processor, a secondary L2 cache or up to a total of four additional 60x processors, the PCI bus and main memory.

Part	Datasheet
TSPC106AVGU66CG	TSPC106AVGU66CG (pdf)

Related Parts	Information
TSPC106AVGU83CG	TSPC106AVGU83CG

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• Processor Bus Frequency Up to 66 MHz and MHz • 64-bit Data Bus and 32-bit Address Bus • L2 Cache Control for 256-Kbyte, 512-Kbyte, 1-Mbyte Sizes • Provides Support for Either Asynchronous SRAM, Burst SRAM Industrial Temperature Range -40°C Tj +110°C • VCC = 3.3V ± 5% • Available in a 303-ball CBGA or a 303-ball CBGA with Solder Column Interposer SCI CI-CGA Package The TSPC106 provides an integrated, high-bandwidth, high-performance, TTL-compatible interface between a 60x processor, a secondary L2 cache or up to a total of four additional 60x processors, the PCI bus and main memory. PCI support allows system designers to rapidly design systems using peripherals already designed for PCI. The TSPC106 uses an advanced 3.3V CMOS-process technology and maintains full interface compatibility with TTL devices. The TSPC106 integrates system testability and debugging features via JTAG boundary-scan capability. PCI Bus Bridge Memory Controller 66-83 MHz TSPC106 G suffix CBGA 303 Ceramic Ball Grid Array GS suffix CI-CGA 303 Ceramic Ball Grid Array with Solder Column Interposer SCI Figure TSPC106 Block Diagram Memory Memory Interface Power Management Error/Interrupt Control L2 Cache Interface 60x Processor Interface L2 60x Bus Target Master PCI Interface Configuration Registers PCI Bus Functional Description The TSPC106 provides a microprocessor CHRP-compliant bridge between the PowerPC microprocessor family and the PCI bus. CHRP is a set of specifications that defines a unified personal computer architecture and brings the combined advantages of the Power platform and the standard PC environment to both system vendors and users. PCI support allows system designers to rapidly design systems using peripherals already designed for PCI and other standard interfaces available in the personal computer hardware environment. These open specifications make it easier for system vendors to design computers capable of running multiple operating systems. The TSPC106 integrates secondary cache control and a high-performance memory controller. The TSPC106 uses an advanced 3.3V CMOS process technology and is fully compatible with TTL devices. The TSPC106 supports a programmable interface to a variety of PowerPC microprocessors operating at select bus speeds. The 60x address bus is 32 bits wide the data bus is 64 bits wide. The 60x processor interface of the TSPC106 uses a subset of the 60x bus protocol, supporting single-beat and burst data transfers. The address and data buses are decoupled to support pipelined transactions. 2 TSPC106A TSPC106A The TSPC106 provides support for the following configurations of 60x processors and L2 cache • Up to four 60x processors with no L2 cache • A single 60x processor plus a direct-mapped, lookaside L2 cache using the internal L2 cache controller of the TSPC106 • Up to four 60x processors plus an externally controlled L2 cache e.g., the Freescale Pin Description Figure TSPC106 in 303-ball CBGA Package 16 W DL26 15 DL28 14 DL30 13 DH31 12 DH29 11 DH27 10 DH25 9 DH23 Ordering Information TS PC106A M GS B/Q Manufacturer's Prefix Type Temperature Range Tj M -55 C, +125 C V -40 C, +110 C Package G CBGA GS CI_CGA Operating Frequency 1 66 MHz 83 MHz Screening Level 1 _ Standard B/Q MIL-STD-883, Class Q B/T According to MIL-STD-883 U Upscreening U/T Upscreening + burn-in Note For availability of different versions, contact your Atmel sales office. Definitions Datasheet Status Validity Objective specification This datasheet contains target and goal specifications for discussion with the customer and application validation Before design phase Target specification This datasheet contains target or goal specifications for product development Valid during the design phase Preliminary specification α site This datasheet contains preliminary data. Additional data may be published at a later date and could include simulation results Valid before characterization phase Preliminary specification site This datasheet also contains characterization results Valid before the industrialization phase Product specification Limiting Values This datasheet contains final product specifications Valid for production purpose Limiting values given are in accordance with the Absolute Maximum Rating System IEC Stresses above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application Information Where application information is given, it is advisory and does not form part of the specification Life Support Applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Atmel customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Atmel for any damages resulting from such improper use or sale. 2102C Date 11/2004 Substantive Change s Preliminary specification site changed to product qualification Motorola changed to Freescale 40 TSPC106A Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel 1 408 441-0311 Fax 1 408 487-2600 Regional Headquarters

PDF Datasheet Preview

• Processor Bus Frequency Up to 66 MHz and MHz
• 64-bit Data Bus and 32-bit Address Bus
• L2 Cache Control for 256-Kbyte, 512-Kbyte, 1-Mbyte Sizes
• Provides Support for Either Asynchronous SRAM, Burst SRAM

Industrial Temperature Range -40°C Tj +110°C
• VCC = 3.3V ± 5%
• Available in a 303-ball CBGA or a 303-ball CBGA with Solder Column Interposer SCI

CI-CGA Package

The TSPC106 provides an integrated, high-bandwidth, high-performance, TTL-compatible interface between a 60x processor, a secondary L2 cache or up to a total of four additional 60x processors, the PCI bus and main memory.

PCI support allows system designers to rapidly design systems using peripherals already designed for PCI.

The TSPC106 uses an advanced 3.3V CMOS-process technology and maintains full interface compatibility with TTL devices.

The TSPC106 integrates system testability and debugging features via JTAG boundary-scan capability.

PCI Bus Bridge Memory Controller 66-83 MHz

TSPC106

G suffix CBGA 303 Ceramic Ball Grid Array

GS suffix CI-CGA 303 Ceramic Ball Grid Array with Solder Column Interposer SCI

Figure TSPC106 Block Diagram

Memory

Memory Interface

Power Management

Error/Interrupt Control

L2 Cache Interface
60x Processor Interface

L2 60x Bus

Target

Master

PCI Interface

Configuration Registers

PCI Bus

Functional Description

The TSPC106 provides a microprocessor CHRP-compliant bridge between the PowerPC microprocessor family and the PCI bus. CHRP is a set of specifications that defines a unified personal computer architecture and brings the combined advantages of the Power platform and the standard PC environment to both system vendors and users. PCI support allows system designers to rapidly design systems using peripherals already designed for PCI and other standard interfaces available in the personal computer hardware environment. These open specifications make it easier for system vendors to design computers capable of running multiple operating systems. The TSPC106 integrates secondary cache control and a high-performance memory controller. The TSPC106 uses an advanced 3.3V CMOS process technology and is fully compatible with TTL devices.

The TSPC106 supports a programmable interface to a variety of PowerPC microprocessors operating at select bus speeds. The 60x address bus is 32 bits wide the data bus is 64 bits wide. The 60x processor interface of the TSPC106 uses a subset of the 60x bus protocol, supporting single-beat and burst data transfers. The address and data buses are decoupled to support pipelined transactions.
2 TSPC106A

TSPC106A

The TSPC106 provides support for the following configurations of 60x processors and L2 cache
• Up to four 60x processors with no L2 cache
• A single 60x processor plus a direct-mapped, lookaside L2 cache using the internal

L2 cache controller of the TSPC106
• Up to four 60x processors plus an externally controlled L2 cache e.g., the Freescale

Pin Description

Figure TSPC106 in 303-ball CBGA Package
16 W DL26
15 DL28
14 DL30
13 DH31
12 DH29
11 DH27
10 DH25
9 DH23
Ordering Information

TS PC106A M

GS B/Q

Manufacturer's Prefix

Type

Temperature Range Tj M -55 C, +125 C V -40 C, +110 C

Package G CBGA GS CI_CGA

Operating Frequency 1 66 MHz 83 MHz

Screening Level 1 _ Standard B/Q MIL-STD-883, Class Q B/T According to MIL-STD-883 U Upscreening U/T Upscreening + burn-in

Note For availability of different versions, contact your Atmel sales office.

Definitions

Datasheet Status

Validity

Objective specification

This datasheet contains target and goal specifications for discussion with the customer and application validation

Before design phase

Target specification

This datasheet contains target or goal specifications for product development

Valid during the design phase

Preliminary specification α site

This datasheet contains preliminary data. Additional data may be published at a later date and could include simulation results

Valid before characterization phase

Preliminary specification site

This datasheet also contains characterization results

Valid before the industrialization phase

Product specification Limiting Values

This datasheet contains final product specifications

Valid for production purpose

Limiting values given are in accordance with the Absolute Maximum Rating System IEC Stresses above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application Information

Where application information is given, it is advisory and does not form part of the specification

Life Support Applications

These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Atmel customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Atmel for any damages resulting from such improper use or sale.
2102C

Date 11/2004

Substantive Change s

Preliminary specification site changed to product qualification Motorola changed to Freescale
40 TSPC106A

Atmel Corporation
2325 Orchard Parkway San Jose, CA 95131, USA Tel 1 408 441-0311 Fax 1 408 487-2600

Regional Headquarters

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Datasheet ID: TSPC106AVGU66CG 519444