TS88915TVW70

TS88915TVW70 Datasheet


The TS88915T Clock Driver utilizes a phazed-locked loop PLL technology to lock its low skew outputs’ frequency and phase onto an input reference clock. It is designed to provide clock distribution for high performance microprocessors such as TS68040, TSPC603E,TSPC603P,TSPC603R, PCI bridge, RAM’s, MMU’s.

Part Datasheet
TS88915TVW70 TS88915TVW70 TS88915TVW70 (pdf)
Related Parts Information
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TS88915TMW70 TS88915TMW70 TS88915TMW70
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• Vcc = 5V ± 5%
• Military Temperature Range
• Fully Compatible with the TS68040
• Five Low Skew Outputs

Five Outputs Q0-Q4 with Output-to-Output Skew < 500 ps Each Being Phase End Frequency Locked to the SYNC Input
• Three Additional Outputs are Available The 2X_Q Output Runs Twice the System “Q” Frequency The Q/2 Output Runs At 1/2 the System “Q” Frequency The Q5 Output is Inverted 180° Phase Shift
• Two Selectable Clock Inputs Two Selectable CLOCK Inputs are Available for Test or Redundancy Purposes Test Mode Pin PLL_EN Provided for Low Frequency Testing All Outputs Can Go Into High Impedance 3-state for Board Test Purposes
• Input Frequency Range From 5 MHz to 2X_Q FMAX
• Three Input/Output Ratios

Input/Output Phase-locked Frequency Ratios of 1:2, 1:1 and 2:1 are Available
• Low Part-to-part Skew

The Phase Variation from Part-to-part Between the SYNC and FEEDBACK Inputs is Less than 550 ps Derived From the tPD Specification, which Defines the Part-to-part Skew
• CMOS and TTL Compatible All Outputs Can Drive Either CMOS or TTL Inputs All Inputs are TTL-level Compatible
• LOCK Indicator LOCK Indicates a Phase-locked State

The TS88915T Clock Driver utilizes a phazed-locked loop PLL technology to lock its low skew outputs’ frequency and phase onto an input reference clock. It is designed to provide clock distribution for high performance microprocessors such as TS68040, TSPC603E,TSPC603P,TSPC603R, PCI bridge, RAM’s, MMU’s.

Low Skew CMOS PLL Clock Driver Tri-State 70 and 100 MHz Versions

TS88915T

Screening/Quality

This Product is Manufactured
• Based Upon the Generic Flow of MIL-STD-883
• or According to Atmel-Grenoble Standard

R suffix PGA 29 Ceramic Pin Grid Array

W suffix LDCC 28 Leaded Ceramic Chip Carrier

Introduction

The TS88915T is a CMOS PLL Clock Driver using phase-locked loop PLL technology. The PLL allows the high current and low skew outputs to lock onto a single input and distribute it with essentially zero delay to multiple components on a board. The PLL also allows the TS88915T to multiply a low frequency input clock and distribute it locally at a higher 2X system frequency. Multiple 88915’s can lock onto a single reference clock, which is ideal for applications when a central system clock must be distributed synchronously to multiple boards see Figure

Figure TS88915T Block Diagram All Versions

FEEDBACK

LOCK

SYNC[0] SYNC[1]

REF_SEL

PHASE/FREQ. DETECTOR

CHARGE PUMP/ LOOP FILTER

VOLTAGE CONTROLLED OSCILLATOR

EXT. REC NETWORK RC1 pin

PLL_EN

FREQ_SEL OE/RST
01 MUX

DIVIDE

BY TWO

DQ CP Q

DQ CP Q

DQ CP Q
2X_Q Q0 Q1 Q2

CP Q R

CP Q R

CP Q R

CP Q R
2 TS88915T
Ordering Information

TS88915T M R B / T 70

Device Type

Temperature range Tc M -55, +125°C V -40, +85°C

Package R PGA W LDCC Note For availability of the different versions, contact your Atmel sales office.

Maximum Output Frequency 70 MHz 100 MHz

Screening level __ Standard B/T according to MIL-STD-883 D/T Burn-in
18 TS88915T

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Datasheet ID: TS88915TVW70 519443