TS68020MF1-16

TS68020MF1-16 Datasheet


• Object Code Compatible with Earlier TS68000 Microprocessors<br>• Addressing Mode Extensions for Enhanced Support of High Level Languages<br>• New Bit Field Data Type Accelerates Bit-oriented Application, i.e. Video Graphics<br>• Fast on-chip Instruction Cache Speed Instructions and Improves Bus Bandwidth<br>• Co-processor Interface to Companion 32-bit Peripherals TS68881 and TS68882

Part Datasheet
TS68020MF1-16 TS68020MF1-16 TS68020MF1-16 (pdf)
Related Parts Information
TS68020VF1-20 TS68020VF1-20 TS68020VF1-20
TS68020VF25 TS68020VF25 TS68020VF25
TS68020VF20 TS68020VF20 TS68020VF20
TS68020VR25 TS68020VR25 TS68020VR25
TS68020VR20 TS68020VR20 TS68020VR20
TS68020VR16 TS68020VR16 TS68020VR16
TS68020VR1-25 TS68020VR1-25 TS68020VR1-25
TS68020MR20 TS68020MR20 TS68020MR20
TS68020VR1-16 TS68020VR1-16 TS68020VR1-16
TS68020MF1-20 TS68020MF1-20 TS68020MF1-20
TS68020MR25 TS68020MR25 TS68020MR25
TS68020MR16 TS68020MR16 TS68020MR16
TS68020MR1-20 TS68020MR1-20 TS68020MR1-20
TS68020MF25 TS68020MF25 TS68020MF25
TS68020MF20 TS68020MF20 TS68020MF20
TS68020MF16 TS68020MF16 TS68020MF16
TS68020VR1-20 TS68020VR1-20 TS68020VR1-20
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• Object Code Compatible with Earlier TS68000 Microprocessors
• Addressing Mode Extensions for Enhanced Support of High Level Languages
• New Bit Field Data Type Accelerates Bit-oriented Application, i.e. Video Graphics
• Fast on-chip Instruction Cache Speed Instructions and Improves Bus Bandwidth
• Co-processor Interface to Companion 32-bit Peripherals TS68881 and TS68882

Floating Point Co-processors
• Pipelined Architecture with High Degree of Internal Parallelism Allowing Multiple

Instructions to be Executed Concurrently
• High Performance Asynchronous Bus in Non-multiplexed and Full 32 Bits
• Dynamic Bus Sizing Efficiently Supports 8-, 16-, 32-bit Memories and Peripherals
• Full Support of Virtual Memory and Virtual Machine
• Sixteen 32-bit General-purpose Data and Address Registers
• Two 32-bit Supervisor Stack Pointers and 5 Special Purpose Control Registers
• 18 Addressing Modes and 7 Data Types
• 4-Gbyte Direct Addressing Range
• Processor Speed MHz - 20 MHz - 25 MHz
• Power Supply VDC ± 10%

The TS68020 is the first full 32-bit implementation of the TS68000 family of microprocessors. Using HCMOS technology, the TS68020 is implemented with 32-bit registers and data paths, 32-bit addresses, a rich instruction set, and versatile addressing modes.

HCMOS 32-bit Virtual Memory Microprocessor

TS68020

Screening/Quality
This product is manufactured in full compliance with either
• MIL-STD-883 class B
• DESC 5962 - 860320
• or according to Atmel standards See “Ordering Information” on page Pin connection see page

R suffix PGA 114

Ceramic Pin Grid Array

F suffix CQFP 132

Ceramic Quad Flat Pack

Introduction

The TS68020 is a high-performance 32-bit microprocessor. It is the first microprocessor to have evolved from a 16-bit machine to a full 32-bit machine that provides 32-bit address and data buses as well as 32-bit internal structures. Many techniques were utilized to improve performance and at the same time maintain compatibility with other processors of the TS68000 Family. Among the improvements are new addressing modes which better support high-level language structures, an expanded instruction set which provides 32-bit operations for the limited cases not supported by the TS68000 and several new instructions which support new data types. For special-purpose applications when a general-purpose processor alone is not adequate, a co-processor interface is provided.

The TS68020 is a high-performance microprocessor implemented in HCMOS, low power, small geometry process. This process allows CMOS and HMOS high density NMOS gates to be combined on the same device. CMOS structures are used where speed and low power is required, and HMOS structures are used where minimum silicon area is desired. This technology enables the TS68020 to be very fast while consuming less power less than watts and still have a reasonably small die size. It utilizes about transistors, of which are actually implemented. The package is a pin-grid array PGA with 114 pins, arranged 13 pins on a side with a depopulated center and 132 pins ceramic quad flat pack.

Figure 1 is a block diagram of the TS68020. The processor can be divided into two main sections the bus controller and the micromachine. This division reflects the autonomy with which the sections operate.

Figure TS68020 Block Diagram

The bus controller consists of the address and data pads and multiplexers required to support dynamic bus sizing, a macro bus controller which schedules the bus cycles on the basis of priority with two state machines one to control the bus cycles for operated accesses and the other to control the bus cycles for instruction accesses , and the instruction cache with its associated control.
2 TS68020

TS68020

The micromachine consists of an execution unit, nanorom and microrom storage, an instruction decoder, an instruction pipe, and associated control sections. The execution unit consists of an address section, an operand address section, and a data section. Microcode control is provided by a modified two-level store of microrom and nanorom. Programmed logical arrays PLAs are used to provide instruction decode and sequencing information. The instruction pipe and other individual control sections provide the secondary decode of instructions and generated the actual control signals that result in the decoding and interpretation of nanorom and micorom information. Figure PGA Terminal Designation

Figure CQFP Terminal Designation

Figure Functional Signal Groups

Signal Description

Group Address Bus Data Bus Logic Clock

Figure 4 illustrates the functional signal groups and Table 1 lists the signals and their function.

The VCC and GND pins are separated into four groups to provide individual power supply connections for the address bus buffers, data bus buffers, and all other output buffers and internal logic.

VCC A9, D3 M8, N8, N13 D1, D2, E3, G11, G13

GND A10, B9,C3, F12 L7, L11, N7, K3 G12, H13, J3, K1 B1
4 TS68020

TS68020

Table Signal Index Signal Name Address Bus Data Bus Function Codes Size

Read-Modify-Write Cycle

External Cycle Start Operand Cycle Start

Address Strobe Data Strobe

Read/Write Data Buffer Enable Data Transfer and Size Acknowledge

Cache Disable Interrupt Priority Level Autovector Interrupt Pending Bus Request Bus Grant Bus Grant Acknowledge Reset Halt Bus Error Clock Power Supply Ground

Mnemonic A0-A31 D0-D31 FC0-FC2 SIZ0/SIZ1

ECS OCS

AS DS

R/W DBEN DSACK0/DSACK1

CDIS IPL0-IPL2 AVEC IPEND BR BG BGACK RESET HALT BERR CLK VCC GND

Function 32-bit Address Bus Used to address any of 4, 294, 967, 296 bytes. 32-bit Data Bus Used to Transfer 8, 16, 24 or 32 bits of Data Per Bus Cycle. 3-bit Function Case Used to Identify the Address Space of Each Bus Cycle. Indicates the Number of Bytes Remaining to be Transferred for this Cycle. These Signals, Together with A0 And A1, Define the Active Sections of the Data Bus. Provides an Indicator that the Current Bus Cycle is Part of an Indivisiblereadmodify-write Operation. Provides an Indication that a Bus Cycle is Beginning. Identical Operation to that of ECS Except that OCS Is Asserted Only During the First Bus Cycle of an Operand Transfer. Indicates that a Valid Address is on The Bus. Indicates that Valid Data is to be Placed on the Data Bus by an External Device or has been Laced on the Data Bus by the TS68020. Defines the Bus Transfer as an MPU Read or Write. Provides an Enable Signal for External Data Buffers. Bus Response Signals that Indicate the Requested Data Transfer Operation is Completed. In Addition, these Two Lines Indicate the Size of the External Bus Port on a Cycle-by-cycle Basis. Dynamically Disables the On-chip Cache to Assist Emulator Support. Provides an Encoded Interrupt Level to the Processor. Requests an Autovector During an Interrupt Acknowledge Cycle. Indicates that an Interrupt is Pending. Indicates that an External Device Requires Bus Mastership. Indicates that an External Device may Assume Bus Mastership. Indicates that an External Device has Assumed Bus Mastership. System Reset. Indicates that the Processor Should Suspend Bus Activity. Indicates an Invalid or Illegal Bus Operation is Being Attempted. Clock Input to the Processor. +5-volt ± 10% Power Supply. Ground Connection.

Detailed Specifications

Scope

This drawing describes the specific requirements for the microprocessor 68020, MHz, 20 MHz and 25 MHz, in compliance with the MIL-STD-883 class B.

Applicable Documents

MIL-STD-883
Ordering Information

Hi-REL Product

Commercial Atmel Part-Number TS68020MRB/C16 TS68020MR1B/C16 TS68020MRB/C20 TS68020MR1B/C20 TS68020MRB/C25 TS68020MR1B/C25 TS68020MFB/C16 TS68020MF1B/C16 TS68020MFB/C20 TS68020MF1B/C20 TS68020MFB/C25 TS68020MF1B/C25 TS68020DESC02XA TS68020DESC03XA TS68020DESC04XA TS68020DESC02XC TS68020DESC03XC TS68020DESC04XC TS68020DESC02YA TS68020DESC03YA TS68020DESC04YA TS68020DESC02YC TS68020DESC03YC TS68020DESC04YC

Norms MIL-STD-883 MIL-STD-883 MIL-STD-883 MIL-STD-883 MIL-STD-883 MIL-STD-883 MIL-STD-883 MIL-STD-883 MIL-STD-883 MIL-STD-883 MIL-STD-883 MIL-STD-883

DESC

Package PGA 114 PGA 114/tin PGA 114 PGA 114/tin PGA 114 PGA 114/tin CQFP 132 CQFP 132/tin CQFP 132 CQFP 132/tin CQFP 132 CQFP 132/tin PGA 114/tin PGA 114/tin PGA 114/tin PGA 114 PGA 114 PGA 114 CQFP 132/tin CQFP 132/tin CQFP 132/tin CQFP 132 CQFP 132 CQFP 132

Temperature Range Tc °C -55/+125 -55/+125 -55/+125 -55/+125 -55/+125 -55/+125 -55/+125 -55/+125 -55/+125 -55/+125 -55/+125 -55/+125 -55/+125 -55/+125 -55/+125 -55/+125 -55/+125 -55/+125 -55/+125 -55/+125 -55/+125 -55/+125 -55/+125 -55/+125

Frequency MHz 20 25 20 25 20 25 20 25 20 25 20 25

Drawing Number -
5962-8603202XA 5962-8603203XA 5962-8603204XA 5962-8603202XC 5962-8603203XC 5962-8603204XC 5962-8603202YA 5962-8603203YA 5962-8603204YA 5962-8603202YC 5962-8603203YC 5962-8603204YC

Standard Product

Commercial Atmel Part-Number TS68020VR16 TS68020VR20 TS68020VR25 TS68020MR16 TS68020MR20 TS68020MR25

Norms Internal Standard Internal Standard Internal Standard Internal Standard Internal Standard Internal Standard

Package PGA 114 PGA 114 PGA 114 PGA 114 PGA 114 PGA 114

Temperature Range Tc °C -40/+85 -40/+85 -40/+85 -55/+125 -55/+125 -55/+125

Frequency MHz 20 25 20 25

Drawing Number Internal

Standard Product

Commercial Atmel Part-Number TS68020VF16 TS68020VF120 TS68020VF25 TS68020MF16 TS68020MF20 TS68020MF25

Norms Internal Standard Internal Standard Internal Standard Internal Standard Internal Standard Internal Standard

Package CQFP 132 CQFP 132 CQFP 132 CQFP 132 CQFP 132 CQFP 132

Temperature Range Tc °C -40/+85 -40/+85 -40/+85 -55/+125 -55/+125 -55/+125

Frequency MHz 20 25 20 25

Drawing Number Internal

TS68020

B/C 20

Device Type

Temperature range M -55, +125°C V -40, +85

Package R = Pin grid array 114 F = CQFP 132

Hirel lead finish - Gold 1 Hot solder dip 883C

Note For availability of the different versions, contact your Atmel sales office.

Speed MHz

Screening - = Standard B/C = MIL STD 883 Class B
44 TS68020

Atmel Headquarters

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Atmel Operations

Memory 2325 Orchard Parkway San Jose, CA 95131 TEL 1 408 441-0311 FAX 1 408 436-4314
More datasheets: 26501-AL3 | 2590 | 2074 | 5100 | M213203 SL005 | M213203 SL001 | M213203 SL002 | SD103ASDM-7 | POLYGUN-EC-EUROPEAN | TS68020VF1-20


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Datasheet ID: TS68020MF1-16 519433