ATV750B-10DM/883

ATV750B-10DM/883 Datasheet

Part	Datasheet
ATV750B-10DM/883	ATV750B-10DM/883 (pdf)

Related Parts	Information
ATV750B-15LM/883	ATV750B-15LM/883
ATV750B-10LM/883	ATV750B-10LM/883
ATV750B-15DM/883	ATV750B-15DM/883
ATV750BL-15DM/883	ATV750BL-15DM/883
ATV750BL-15LM/883	ATV750BL-15LM/883

PDF Datasheet Preview
• Advanced, High-speed Programmable Logic Device Superset of 22V10 Improved Performance - ns tPD, 95 MHz External Operation Enhanced Logic Flexibility Backward Compatible with ATV750 L Software and Hardware • New Flip-flop Features D- or T-type Product Term or Direct Input Pin Clocking • High-speed Erasable Programmable Logic Devices ns Maximum Pin-to-pin Delay Device ATV750B ATV750BL ICC, Standby 125 mA 15 mA • Highest Density Programmable Logic Available in a 24-pin Package • Increased Logic Flexibility 42 Array Inputs, 20 Sum Terms and 20 Flip-flops • Enhanced Output Logic Flexibility All 20 Flip-flops Feed Back Internally 10 Flip-flops are Also Available as Outputs • Full Military, Commercial and Industrial Temperature Ranges Logic Diagram The ATV750B L is twice as powerful as most other 24-pin programmable logic devices. Increased product terms, sum terms, flip-flops and output logic configurations translate into more usable gates. High-speed logic and uniform, predictable delays guarantee fast in-system performance. High-speed UV Erasable Programmable Logic Device ATV750B ATV750BL Commercial and industrial versions are obsolete. Please use ATF750C. Military versions continue to be available, but please do not use for new designs. For new military applications, recommend multiple ATF22V10s. Pin Configurations Pin Name CLK IN Function Clock Logic Inputs Bi-directional Buffers No Internal Connection +5V Supply DIP/SOIC PLCC/LCC 4 IN 3 IN 2 CLK/IN 1* 28 VCC 27 I/O 26 I/O CLK/IN 1 IN 2 IN 3 IN 4 IN 5 IN 6 IN 7 IN 8 IN 9 IN 10 IN 11 GND 12 24 VCC 23 I/O 22 I/O 21 I/O 20 I/O 19 I/O 18 I/O 17 I/O 16 I/O 15 I/O 14 I/O 13 IN IN 5 IN 6 IN 7 8 IN 9 IN 10 IN 11 25 I/O 24 I/O 23 I/O 22 21 I/O 20 I/O 19 I/O IN 12 IN 13 GND 14 * 15 IN 16 I/O 17 I/O 18 Each of the ATV750B L 22 logic pins can be used as an input. Ten of these can be used as inputs, outputs or bi-directional I/O pins. Each flip-flop is individually configurable as either Dor T-type. Each flip-flop output is fed back into the array independently. This allows burying of all the sum terms and flip-flops. There are 171 total product terms available. A variable format is used to assign between four to eight product terms per sum term. There are two sum terms per output, providing added flexibility. Much more logic can be replaced by this device than by any other 24-pin PLD. With 20 sum terms and flip-flops, complex state machines are easily implemented with logic to spare. Product terms provide individual clocks and asynchronous resets for each flip-flop. Each flipflop may also be individually configured to have direct input pin controlled clocking. Each output has its own enable product term. One product term provides a common synchronous preset for all flip-flops. Register preload functions are provided to simplify testing. All registers automatically reset upon power-up. The ATV750BL is a low-power device with speeds as fast as 15 ns. The ATV750BL provides the optimum low-power PLD solution, with full CMOS output levels. This device significantly reduces total system power, thereby allowing battery-powered operation. Absolute Maximum Ratings* Temperature Under Bias................................ -55°C to +125°C Storage Temperature -65°C to +150°C Voltage on Any Pin with Respect to Ground to +7.0V 1 Voltage on Input Pins with Respect to Ground During to +14.0V 1 Programming Voltage with Respect to Ground to +14.0V 1 Note See ordering information for valid speed and temperature combination. Industrial -40°C - 85°C Ambient 5V ± 10% Military -55°C - 125°C Case 5V ± 10% DC Characteristics Symbol Parameter Condition Input Load Current VIN = -0.1V to VCC + 1V Output Leakage Current VOUT = -0.1V to VCC + 0.1V Com. B-7, -10 Ind., Mil. Com. ICC IOS 1 VIL VIH VOH Note: Power Supply Current, Standby VCC = MAX, VIN = MAX, Outputs Open B-15, -25 BL-15 Ind., Mil. Com. Ind., Mil. Output Short Circuit Current VOUT = 0.5V -120 Input Low Voltage VCC 5.5V Input High Voltage VCC + IOL = 16 mA Com., Ind. Output Low VIN = VIH or VIL, IOL = 12 mA Mil. Voltage VCC = MIN IOL = 24 mA Com. Output High Voltage VIN = VIH or VIL, VCC = MIN IOH = -100 µA IOH = mA See ordering information for valid part numbers. -10 Min Max B/BL-15 Min Max 8/12 50/41 B/BL-25 Min Max Units ns ns MHz ns AC Waveforms, Input Pin Clock 1 Note Timing measurement reference is 1.5V. Input AC driving levels are 0.0V and 3.0V, unless otherwise specified. AC Characteristics, Input Pin Clock tPD tEA tER tCOS tCFS tSS tSFS tHS tPS tWS fMAXS tAW tARS tSPS Parameter Input or Feedback to Non-Registered Output Input to Output Enable Input to Output Disable Clock to Output Clock to Feedback Input Setup Time Feedback Setup Time Hold Time Clock Period Clock Width External Feedback 1/ tSS+tCOS Internal Feedback 1/ tSFS+tCFS No Feedback 1/ tPS Asynchronous Reset Width Asynchronous Reset Recovery Time Asynchronous Reset to Registered Output Reset Setup Time, Synchronous Preset -7 Min Max -10 Min Max B/BL -15 0 7 0 12 6 15 10 55/44 80 83 B/BL -25 Min Max 9/15 48/37 Units ns ns MHz ns 6 ATV750B L Functional Logic Diagram ATV750B, Upper Half ATV750B L Functional Logic Diagram ATV750B, Lower Half 8 ATV750B L Preload of Registered Outputs ATV750B L The ATV750B L registers are provided with circuitry to allow loading of each register asynchronously with either a high or a low. This feature will simplify testing since any state can be forced into the registers to control test sequencing. A VIH level on the I/O pin will force the register high a VIL will force it low, independent of the output polarity. The PRELOAD state is entered by placing a 10.25V to 10.75V signal on pin 8 on DIPs, and lead 10 on SMDs. When the clock term is pulsed high, the data on the I/O pins is placed into the register chosen by the Select Pin. Level Forced on Registered Output Pin during PRELOAD Cycle VIH VIL VIH VIL Select Pin State Low High Register #0 State after Cycle High Low X Register #1 State after Cycle X High Low Power-up Reset Ordering Information tPD ns tCOS ns Ext. fMAXS MHz Ordering Code Package Operation Range ATV750B-7JC 1 ATV750B-7PC 1 28J 24P3 Commercial 0°C to 70°C ATV750B-10JC 1 ATV750B-10PC 1 ATV750B-10SC 1 28J 24P3 24S Commercial 0°C to 70°C ATV750B-10JI 1 ATV750B-10PI 1 ATV750B-10SI 1 28J 24P3 24S Industrial -40°C to 85°C ATV750B-10DM/883 2 ATV750B-10LM/883 2 24DW3 28LW Military/883C -55°C to 125°C Class B, Fully Compliant ATV750B-15JC 1 ATV750B-15PC 1 ATV750B-15SC 1 28J 24P3 24S Commercial 0°C to 70°C ATV750B-15JI 1 ATV750B-15PI 1 ATV750B-15SI 1 28J 24P3 24S Industrial -40°C to 85°C ATV750B-15DM/883 2 ATV750B-15LM/883 2 24DW3 28LW Military/883C -55°C to 125°C Class B, Fully Compliant ATV750B-25JC 1 ATV750B-25PC 1 ATV750B-25SC 1 28J 24P3 24S Commercial 0°C to 70°C ATV750B-25JI 1 ATV750B-25PI 1 ATV750B-25SI 1 28J 24P3 24S Industrial -40°C to 85°C 5962-88726 08 LA 2 5962-88726 08 3X 2 24DW3 28LW Military/883C -55°C to 125°C Class B, Fully Compliant 5962-88726 09 LA 2 5962-88726 09 3X 2 24DW3 28LW Military/883C -55°C to 125°C Class B, Fully Compliant Notes Obsolete, please use ATF750C versions. Continue to be available, but please do not use for new designs. For new designs recommend multiple ATF22V10s. Ordering Information Continued tPD ns tCOS ns Ext. fMAXS MHz Ordering Code ATV750BL-15JC 1 ATV750BL-15PC 1 ATV750BL-15SC 1 ATV750BL-15JI 1 ATV750BL-15PI 1 ATV750BL-15SI 1 ATV750BL-15DM/883 2 ATV750BL-15LM/883 2 ATV750BL-25JC 1 ATV750BL-25PC 1 ATV750BL-25SC 1 Package 28J 24P3 24S 28J 24P3 24S 24DW3 28LW 28J 24P3 24S Operation Range Commercial 0°C to 70°C Industrial -40°C to 85°C Military/883C -55°C to 125°C Class B, Fully Compliant Commercial 0°C to 70°C 15 Notes: ATV750BL-25JI19 ATV750BL-25PI 1 ATV750BL-25SI 1 28J 24P3 24S Industrial -40°C to 85°C 5962-88726 11 LX 2 5962-88726 11 3X 2 24DW3 28LW Military/883C -55°C to 125°C Class B, Fully Compliant Obsolete, please use ATF750C versions. Continue to be available, but please do not use for new designs. For new designs recommend multiple ATF22V10s. Using “C” Product for Industrial To use commercial product for Industrial temperature ranges, down-grade one speed grade from the “I” to the “C” device 7 ns “C” = 10 ns “I” and de-rate power by 24DW3 28J 28LW 24P3 24S Package Type 24-lead, Wide, Windowed, Ceramic Dual Inline Package Cerdip 28-lead, Plastic J-leaded Chip Carrier OTP PLCC 28-pad, Windowed, Ceramic Leadless Chip Carrier LCC 24-lead, Wide, Plastic Dual Inline Package OTP PDIP 24-lead, Wide, Plastic Gull Wing Small Outline OTP SOIC 16 ATV750B L ATV750B L Packaging Information 24DW3, 24-lead, Wide, WIndowed, Ceramic Dual Inline Package Cerdip Dimensions in Inches and Millimeters MIL-STD-1835 D-9 CONFIG A 28J, 28-lead, Plastic J-leaded Chip Carrier PLCC Dimensions in Inches and Millimeters JEDEC STANDARD MS-018 AB X 45° PIN NO. 1 IDENTIFY X 30° - 45° .485 12.3 SQ REF SQ X 45° MAX 3X 28LW, 28-pad, Windowed, Ceramic Leadless Chip Carrier LCC Dimensions in Inches and Millimeters * MIL-STD-1835 C-4 *Controlling dimension millimeters 24P3, 24-lead, Wide, Plastic Dual Inline Package PDIP Dimensions in Inches and Millimeters JEDEC STANDARD MS-001 AF SEATING PLANE 0 REF 15 Packaging Information 24S, 24-lead, Wide, Plastic Gull Wing Small Outline SOIC Dimensions in Inches and Millimeters

PDF Datasheet Preview

• Advanced, High-speed Programmable Logic Device Superset of 22V10 Improved Performance - ns tPD, 95 MHz External Operation Enhanced Logic Flexibility Backward Compatible with ATV750 L Software and Hardware
• New Flip-flop Features D- or T-type Product Term or Direct Input Pin Clocking
• High-speed Erasable Programmable Logic Devices ns Maximum Pin-to-pin Delay

Device ATV750B ATV750BL

ICC, Standby 125 mA 15 mA
• Highest Density Programmable Logic Available in a 24-pin Package
• Increased Logic Flexibility
42 Array Inputs, 20 Sum Terms and 20 Flip-flops
• Enhanced Output Logic Flexibility

All 20 Flip-flops Feed Back Internally 10 Flip-flops are Also Available as Outputs
• Full Military, Commercial and Industrial Temperature Ranges

Logic Diagram

The ATV750B L is twice as powerful as most other 24-pin programmable logic devices. Increased product terms, sum terms, flip-flops and output logic configurations translate into more usable gates. High-speed logic and uniform, predictable delays guarantee fast in-system performance.

High-speed UV Erasable Programmable Logic Device

ATV750B ATV750BL

Commercial and industrial versions are obsolete. Please use ATF750C.

Military versions continue to be available, but please do not use for new designs. For new military applications, recommend multiple ATF22V10s.

Pin Configurations

Pin Name CLK IN

Function Clock Logic Inputs

Bi-directional Buffers

No Internal Connection
+5V Supply

DIP/SOIC

PLCC/LCC
4 IN 3 IN 2 CLK/IN 1* 28 VCC 27 I/O 26 I/O

CLK/IN 1 IN 2 IN 3 IN 4 IN 5 IN 6 IN 7 IN 8 IN 9 IN 10 IN 11

GND 12
24 VCC 23 I/O 22 I/O 21 I/O 20 I/O 19 I/O 18 I/O 17 I/O 16 I/O 15 I/O 14 I/O 13 IN

IN 5 IN 6 IN 7
*8 IN 9 IN 10 IN 11
25 I/O 24 I/O 23 I/O 22 * 21 I/O 20 I/O 19 I/O

IN 12 IN 13 GND 14
* 15 IN 16 I/O 17 I/O 18

Each of the ATV750B L 22 logic pins can be used as an input. Ten of these can be used as inputs, outputs or bi-directional I/O pins. Each flip-flop is individually configurable as either Dor T-type. Each flip-flop output is fed back into the array independently. This allows burying of all the sum terms and flip-flops.

There are 171 total product terms available. A variable format is used to assign between four to eight product terms per sum term. There are two sum terms per output, providing added flexibility. Much more logic can be replaced by this device than by any other 24-pin PLD. With 20 sum terms and flip-flops, complex state machines are easily implemented with logic to spare.

Product terms provide individual clocks and asynchronous resets for each flip-flop. Each flipflop may also be individually configured to have direct input pin controlled clocking. Each output has its own enable product term. One product term provides a common synchronous preset for all flip-flops. Register preload functions are provided to simplify testing. All registers automatically reset upon power-up.

The ATV750BL is a low-power device with speeds as fast as 15 ns. The ATV750BL provides the optimum low-power PLD solution, with full CMOS output levels. This device significantly reduces total system power, thereby allowing battery-powered operation.

Absolute Maximum Ratings*

Temperature Under Bias................................ -55°C to +125°C

Storage Temperature -65°C to +150°C

Voltage on Any Pin with Respect to Ground to +7.0V 1

Voltage on Input Pins with Respect to Ground During to +14.0V 1

Programming Voltage with Respect to Ground to +14.0V 1
Note See ordering information for valid speed and temperature combination.

Industrial
-40°C - 85°C Ambient
5V ± 10%

Military
-55°C - 125°C Case
5V ± 10%

DC Characteristics

Symbol Parameter

Condition

Input Load Current VIN = -0.1V to VCC + 1V

Output Leakage

Current

VOUT = -0.1V to VCC + 0.1V

Com.

B-7, -10

Ind., Mil.

Com.

ICC IOS 1 VIL VIH

VOH Note:

Power Supply Current, Standby

VCC = MAX, VIN = MAX, Outputs Open

B-15, -25 BL-15

Ind., Mil. Com. Ind., Mil.

Output Short Circuit Current

VOUT = 0.5V
-120

Input Low Voltage VCC 5.5V

Input High Voltage

VCC +

IOL = 16 mA Com., Ind.

Output Low

VIN = VIH or VIL,

IOL = 12 mA

Mil.

Voltage

VCC = MIN

IOL = 24 mA Com.

Output High Voltage

VIN = VIH or VIL, VCC = MIN

IOH = -100 µA IOH = mA
See ordering information for valid part numbers.
-10 Min Max

B/BL-15 Min Max
8/12
50/41

B/BL-25 Min Max

Units ns
ns MHz ns

AC Waveforms, Input Pin Clock 1

Note Timing measurement reference is 1.5V. Input AC driving levels are 0.0V and 3.0V, unless otherwise specified.

AC Characteristics, Input Pin Clock
tPD tEA tER tCOS tCFS tSS tSFS tHS tPS tWS fMAXS
tAW tARS
tSPS

Parameter Input or Feedback to Non-Registered Output Input to Output Enable Input to Output Disable Clock to Output Clock to Feedback Input Setup Time Feedback Setup Time Hold Time Clock Period Clock Width External Feedback 1/ tSS+tCOS Internal Feedback 1/ tSFS+tCFS No Feedback 1/ tPS Asynchronous Reset Width Asynchronous Reset Recovery Time Asynchronous Reset to Registered Output Reset Setup Time, Synchronous Preset
-7 Min Max
-10 Min Max

B/BL -15
0 7 0 12 6
15 10
55/44 80 83

B/BL -25

Min Max
9/15
48/37

Units ns
ns MHz ns
6 ATV750B L

Functional Logic Diagram ATV750B, Upper Half

ATV750B L

Functional Logic Diagram ATV750B, Lower Half
8 ATV750B L

Preload of Registered Outputs

ATV750B L

The ATV750B L registers are provided with circuitry to allow loading of each register asynchronously with either a high or a low. This feature will simplify testing since any state can be forced into the registers to control test sequencing. A VIH level on the I/O pin will force the register high a VIL will force it low, independent of the output polarity. The PRELOAD state is entered by placing a 10.25V to 10.75V signal on pin 8 on DIPs, and lead 10 on SMDs. When the clock term is pulsed high, the data on the I/O pins is placed into the register chosen by the Select Pin.

Level Forced on Registered Output Pin during PRELOAD Cycle

VIH VIL VIH VIL

Select Pin State Low High

Register #0 State after Cycle High Low X

Register #1 State after Cycle X High Low

Power-up Reset
Ordering Information
tPD ns
tCOS ns

Ext.
fMAXS MHz
Ordering Code

Package

Operation Range

ATV750B-7JC 1 ATV750B-7PC 1
28J 24P3

Commercial 0°C to 70°C

ATV750B-10JC 1 ATV750B-10PC 1 ATV750B-10SC 1
28J 24P3 24S

Commercial 0°C to 70°C

ATV750B-10JI 1 ATV750B-10PI 1 ATV750B-10SI 1
28J 24P3 24S

Industrial -40°C to 85°C

ATV750B-10DM/883 2 ATV750B-10LM/883 2
24DW3 28LW

Military/883C -55°C to 125°C Class B, Fully Compliant

ATV750B-15JC 1 ATV750B-15PC 1 ATV750B-15SC 1
28J 24P3 24S

Commercial 0°C to 70°C

ATV750B-15JI 1 ATV750B-15PI 1 ATV750B-15SI 1
28J 24P3 24S

Industrial -40°C to 85°C

ATV750B-15DM/883 2 ATV750B-15LM/883 2
24DW3 28LW

Military/883C -55°C to 125°C Class B, Fully Compliant

ATV750B-25JC 1 ATV750B-25PC 1 ATV750B-25SC 1
28J 24P3 24S

Commercial 0°C to 70°C

ATV750B-25JI 1 ATV750B-25PI 1 ATV750B-25SI 1
28J 24P3 24S

Industrial -40°C to 85°C
5962-88726 08 LA 2 5962-88726 08 3X 2
24DW3 28LW

Military/883C -55°C to 125°C Class B, Fully Compliant
5962-88726 09 LA 2 5962-88726 09 3X 2
24DW3 28LW

Military/883C -55°C to 125°C Class B, Fully Compliant

Notes Obsolete, please use ATF750C versions. Continue to be available, but please do not use for new designs. For new designs recommend multiple ATF22V10s.
Ordering Information Continued
tPD ns
tCOS ns

Ext. fMAXS MHz
Ordering Code ATV750BL-15JC 1 ATV750BL-15PC 1 ATV750BL-15SC 1 ATV750BL-15JI 1 ATV750BL-15PI 1 ATV750BL-15SI 1 ATV750BL-15DM/883 2 ATV750BL-15LM/883 2

ATV750BL-25JC 1 ATV750BL-25PC 1 ATV750BL-25SC 1

Package 28J 24P3 24S 28J 24P3 24S 24DW3 28LW
28J 24P3 24S

Operation Range Commercial 0°C to 70°C

Industrial -40°C to 85°C

Military/883C -55°C to 125°C Class B, Fully Compliant

Commercial 0°C to 70°C
15 Notes:

ATV750BL-25JI19 ATV750BL-25PI 1 ATV750BL-25SI 1
28J 24P3 24S

Industrial -40°C to 85°C
5962-88726 11 LX 2 5962-88726 11 3X 2
24DW3 28LW

Military/883C -55°C to 125°C Class B, Fully Compliant

Obsolete, please use ATF750C versions. Continue to be available, but please do not use for new designs. For new designs recommend multiple ATF22V10s.

Using “C” Product for Industrial

To use commercial product for Industrial temperature ranges, down-grade one speed grade from the “I” to the “C” device 7 ns “C” = 10 ns “I” and de-rate power by
24DW3 28J 28LW 24P3 24S

Package Type 24-lead, Wide, Windowed, Ceramic Dual Inline Package Cerdip 28-lead, Plastic J-leaded Chip Carrier OTP PLCC 28-pad, Windowed, Ceramic Leadless Chip Carrier LCC 24-lead, Wide, Plastic Dual Inline Package OTP PDIP 24-lead, Wide, Plastic Gull Wing Small Outline OTP SOIC
16 ATV750B L

ATV750B L

Packaging Information
24DW3, 24-lead, Wide, WIndowed, Ceramic Dual Inline Package Cerdip Dimensions in Inches and Millimeters

MIL-STD-1835 D-9 CONFIG A
28J, 28-lead, Plastic J-leaded Chip Carrier PLCC Dimensions in Inches and Millimeters

JEDEC STANDARD MS-018 AB

X 45° PIN NO. 1 IDENTIFY

X 30° - 45°
.485 12.3 SQ

REF SQ

X 45° MAX 3X
28LW, 28-pad, Windowed, Ceramic Leadless Chip Carrier LCC Dimensions in Inches and Millimeters *

MIL-STD-1835 C-4
*Controlling dimension millimeters
24P3, 24-lead, Wide, Plastic Dual Inline Package PDIP Dimensions in Inches and Millimeters

JEDEC STANDARD MS-001 AF

SEATING PLANE
0 REF 15

Packaging Information
24S, 24-lead, Wide, Plastic Gull Wing Small Outline SOIC Dimensions in Inches and Millimeters

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived ATV750B-10DM/883 Datasheet file may be downloaded here without warranties.

Datasheet ID: ATV750B-10DM/883 519327