ATTINY2313V-10SJ

ATTINY2313V-10SJ Datasheet

Endurance 100,000 Write/Erase Cycles 128 Bytes Internal SRAM Programming Lock for Flash Program and EEPROM Data Security • Peripheral Features One 8-bit Timer/Counter with Separate Prescaler and Compare Mode One 16-bit Timer/Counter with Separate Prescaler, Compare and Capture Modes Four PWM Channels On-chip Analog Comparator Programmable Watchdog Timer with On-chip Oscillator USI Universal Serial Interface Full Duplex USART • Special Microcontroller Features debugWIRE On-chip Debugging In-System Programmable via SPI Port External and Internal Interrupt Sources Low-power Idle, Power-down, and Standby Modes Enhanced Power-on Reset Circuit Programmable Brown-out Detection Circuit Internal Calibrated Oscillator • I/O and Packages 18 Programmable I/O Lines 20-pin PDIP, 20-pin SOIC, 20-pad QFN/MLF • Operating Voltages 5.5V ATtiny2313V 5.5V ATtiny2313 • Speed Grades ATtiny2313V 0 4 MHz - 5.5V, 0 10 MHz 5.5V ATtiny2313 0 10 MHz - 5.5V, 0 20 MHz 5.5V • Typical Power Consumption Active Mode

Part	Datasheet
ATTINY2313V-10SJ	ATTINY2313V-10SJ (pdf)

Related Parts	Information
ATTINY2313V-10SI	ATTINY2313V-10SI

PDF Datasheet Preview
• Utilizes the RISC Architecture • AVR High-performance and Low-power RISC Architecture 120 Powerful Instructions Most Single Clock Cycle Execution 32 x 8 General Purpose Working Registers Fully Static Operation Up to 20 MIPS Throughput at 20 MHz • Data and Non-volatile Program and Data Memories 2K Bytes of In-System Self Programmable Flash Endurance 10,000 Write/Erase Cycles 128 Bytes In-System Programmable EEPROM Endurance 100,000 Write/Erase Cycles 128 Bytes Internal SRAM Programming Lock for Flash Program and EEPROM Data Security • Peripheral Features One 8-bit Timer/Counter with Separate Prescaler and Compare Mode One 16-bit Timer/Counter with Separate Prescaler, Compare and Capture Modes Four PWM Channels On-chip Analog Comparator Programmable Watchdog Timer with On-chip Oscillator USI Universal Serial Interface Full Duplex USART • Special Microcontroller Features debugWIRE On-chip Debugging In-System Programmable via SPI Port External and Internal Interrupt Sources Low-power Idle, Power-down, and Standby Modes Enhanced Power-on Reset Circuit Programmable Brown-out Detection Circuit Internal Calibrated Oscillator • I/O and Packages 18 Programmable I/O Lines 20-pin PDIP, 20-pin SOIC, 20-pad QFN/MLF • Operating Voltages 5.5V ATtiny2313V 5.5V ATtiny2313 • Speed Grades ATtiny2313V 0 4 MHz - 5.5V, 0 10 MHz 5.5V ATtiny2313 0 10 MHz - 5.5V, 0 20 MHz 5.5V • Typical Power Consumption Active Mode 1 MHz, 1.8V 230 µA 32 kHz, 1.8V 20 µA including oscillator Power-down Mode < µA at 1.8V 8-bit Microcontroller with 2K Bytes In-System Programmable Flash ATtiny2313/V Not recommended for new designs. Use ATtiny2313A Figure Pinout ATtiny2313 Configurations PDIP/SOIC RESET/dW PA2 1 RXD PD0 2 TXD PD1 3 XTAL2 PA1 4 XTAL1 PA0 5 CKOUT/XCK/INT0 PD2 6 INT1 PD3 7 T0 PD4 8 OC0B/T1 PD5 9 GND 10 20 VCC 19 PB7 UCSK/SCL/PCINT7 18 PB6 MISO/DO/PCINT6 17 PB5 MOSI/DI/SDA/PCINT5 16 PB4 OC1B/PCINT4 15 PB3 OC1A/PCINT3 14 PB2 OC0A/PCINT2 13 PB1 AIN1/PCINT1 12 PB0 AIN0/PCINT0 11 PD6 ICP 20 PD0 RXD 19 PA2 RESET/dW 18 VCC 17 PB7 UCSK/SCK/PCINT7 16 PB6 MISO/DO/PCINT6 TXD PD1 1 XTAL2 PA1 2 XTAL1 PA0 3 CKOUT/XCK/INT0 PD2 4 INT1 PD3 5 15 PB5 MOSI/DI/SDA/PCINT5 14 PB4 OC1B/PCINT4 13 PB3 OC1A/PCINT3 12 PB2 OC0A/PCINT2 11 PB1 AIN1/PCINT1 T0 PD4 6 OC0B/T1 PD5 7 GND 8 ICP PD6 9 AIN0/PCINT0 PB0 10 Overview NOTE Bottom pad should be soldered to ground. The ATtiny2313 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny2313 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. 2 ATtiny2313 Block Diagram Figure Block Diagram ATtiny2313 PA0 - PA2 PORTA DRIVERS VCC GND DATA REGISTER PORTA DATA DIR. REG. PORTA 8-BIT DATA BUS PROGRAM COUNTER PROGRAM FLASH The parts are characterized at frequencies higher than test limits. Parts are not guaranteed to function properly at frequencies higher than the ordering code indicates. The difference between current consumption in Power-down mode with Watchdog Timer enabled and Power-down mode with Watchdog Timer disabled represents the differential current drawn by the Watchdog Timer. Active Supply Current Figure Active Supply Current vs. Frequency - MHz ACTIVE SUPPLY CURRENT vs. LOW FREQUENCY - MHz ICC mA Frequency MHz Figure Active Supply Current vs. Frequency 1 - 20 MHz ACTIVE SUPPLY CURRENT vs. FREQUENCY 1 - 20 MHz 14 ICC mA Frequency MHz Figure Active Supply Current vs. VCC Internal RC Oscillator, 8 MHz ACTIVE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 8 MHz ICC mA VCC V 184 ATtiny2313 ATtiny2313 Figure Active Supply Current vs. VCC Internal RC Oscillator, 4 MHz ACTIVE SUPPLY CURRENT vs. Vcc INTERNAL RC OSCILLATOR, 4 MHz 6 -40 °C 85 °C 25 °C Icc mA Vcc V Figure Active Supply Current vs. VCC Internal RC Oscillator, 1 MHz ACTIVE SUPPLY CURRENT vs. Vcc INTERNAL RC OSCILLATOR, 1 MHz 85 °C 25 °C -40 °C Icc mA Vcc V Figure Active Supply Current vs. VCC Internal RC Oscillator, MHz ACTIVE SUPPLY CURRENT vs. Vcc INTERNAL RC OSCILLATOR, MHz 1 85 °C 25 °C -40 °C Icc mA Vcc V Figure Active Supply Current vs. VCC Internal RC Oscillator, 128 KHz Ordering Information Speed MHz 3 Power Supply - 5.5V - 5.5V Ordering Code ATtiny2313V-10PI ATtiny2313V-10PU 2 ATtiny2313V-10SI ATtiny2313V-10SU 2 ATtiny2313V-10MU 2 ATtiny2313-20PI ATtiny2313-20PU 2 ATtiny2313-20SI ATtiny2313-20SU 2 ATtiny2313-20MU 2 Package 1 20P3 20S 20M1 20P3 20S 20M1 Operation Range Industrial -40°C to 85°C Industrial -40°C to 85°C Note: This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. Pb-free packaging alternative, complies to the European Directive for Restriction of Hazardous Substances RoHS directive .Also Halide free and fully Green. For Speed vs. VCC, see Figure 82 on page 182 and Figure 83 on page 20P3 20S 20M1 Package Type 20-lead, Wide, Plastic Dual Inline Package PDIP 20-lead, Wide, Plastic Gull Wing Small Outline Package SOIC 20-pad, 4 x 4 x mm Body, Quad Flat No-Lead/Micro Lead Frame Package MLF Packaging Information 20P3 PIN 1 SEATING PLANE A1 B B1 This package conforms to JEDEC reference MS-001, Variation AD. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed mm COMMON DIMENSIONS Unit of Measure = mm SYMBOL MIN NOM MAX NOTE Note 2 Note 2 TITLE 2325 Orchard Parkway 20P3, 20-lead mm Wide Plastic Dual R San Jose, CA 95131 Inline Package PDIP 1/12/04 20P3 218 ATtiny2313 ATtiny2313 20M1 Pin 1 ID 2 SIDE VIEW TOP VIEW A2 D2 A1 Pin #1 Notch R L e BOTTOM VIEW Note Reference JEDEC Standard MO-220, Fig. 1 SAW Singulation WGGD-5. COMMON DIMENSIONS Unit of Measure = mm SYMBOL A A1 A2 b D D2 E E2 e L NOM REF BSC NOTE TITLE 2325 Orchard Parkway 20M1, 20-pad, 4 x 4 x mm Body, Lead Pitch mm, R San Jose, CA 95131 mm Exposed Pad, Micro Lead Frame Package MLF 10/27/04 20M1 220 ATtiny2313 ATtiny2313 Errata • Wrong values read after Erase Only operation • Parallel Programming does not work • Watchdog Timer Interrupt disabled • EEPROM can not be written below volts Updated typos. Updated Figure 1 on page Added “Resources” on page Updated “Default Clock Source” on page Updated “128 kHz Internal Oscillator” on page Updated “Power Management and Sleep Modes” on page 32 Updated Table 3 on page 25,Table 13 on page 32, Table 14 on page 33, Table 19 on page 44, Table 31 on page 62, Table 79 on page Updated “External Interrupts” on page Updated “Bit PCINT7..0 Pin Change Enable Mask on page Updated “Bit 6 ACBG Analog Comparator Bandgap Select” on page Updated “Calibration Byte” on page Updated “DC Characteristics” on page Updated “Register Summary” on page Updated “Ordering Information” on page Changed occurences of OCnA to OCFnA, OCnB to OCFnB and OC1x to OCF1x. 2514G-10/04 to Updated Table 6 on page 27, Table 15 on page 36, Table 68 on page 162 and Table 80 on page Changed CKSEL default value in “Default Clock Source” on page 25 to 8 MHz. Updated “Programming the Flash” on page 167, “Programming the EEPROM” on page 169 and “Enter Programming Mode” on page Updated “DC Characteristics” on page MLF option updated to “Quad Flat No-Lead/Micro Lead Frame QFN/MLF ” 222 ATtiny2313 ATtiny2313 2514F-08/04 to 2514E-04/04 to 2514D-03/04 to 2514C-12/03 to 2514B-09/03 to Updated “Features” on page Updated “Pinout ATtiny2313” on page Updated “Ordering Information” on page Updated “Packaging Information” on page Updated “Errata” on page Updated “Features” on page Updated “Alternate Functions of Port B” on page Updated “Calibration Byte” on page Moved Table 69 on page 162 and Table 70 on page 162 to “Page Size” on page Updated “Enter Programming Mode” on page Updated “Serial Programming Algorithm” on page Updated Table 78 on page Updated “DC Characteristics” on page Updated “ATtiny2313 Typical Characteristics” on page Changed occurences of PCINT15 to PCINT7, EEMWE to EEMPE and EEWE to EEPE in the document. Speed Grades changed - 12MHz to 10MHz - 24MHz to 20MHz Updated Figure 1 on page Updated “Ordering Information” on page Updated “Maximum Speed vs. VCC” on page Updated “ATtiny2313 Typical Characteristics” on page Updated Table 2 on page Replaced “Watchdog Timer” on page Added “Maximum Speed vs. VCC” on page “Serial Programming Algorithm” on page 175 updated. Changed mA to µA in preliminary Figure 136 on page “Ordering Information” on page 217 updated. MLF package option removed Package drawing “20P3” on page 218 updated. Updated C-code examples. Renamed instances of SPMEN to SELFPRGEN, Self Programming Enable. Updated “Calibrated Internal RC Oscillator” on page 2514A-09/03 to Fixed typo from UART to USART and updated Speed Grades and Power Consumption Estimates in “Features” on page Updated “Pin Configurations” on page Updated Table 15 on page 36 and Table 80 on page Updated item 5 in “Serial Programming Algorithm” on page Updated “Electrical Characteristics” on page Updated Figure 82 on page 182 and added Figure 83 on page Changed SFIOR to GTCCR in “Register Summary” on page Updated “Ordering Information” on page Added new errata in “Errata” on page 224 ATtiny2313 Table of Contents Features 1 Pin Configurations 2 Resources 6 About Code Examples 7 Disclaimer 8 AVR CPU Core 9 Introduction 9 Architectural Overview 9 ALU Arithmetic Logic Unit 10 Status Register 10 General Purpose Register File 11 Instruction Execution Timing 13 Reset and Interrupt Handling 14 AVR ATtiny2313 Memories 16 In-System Reprogrammable Flash Program Memory 16 EEPROM Data Memory 18 I/O Memory 22 System Clock and Clock Options 24 Clock Systems and their Distribution 24 Clock Sources 25 Default Clock Source 25 Crystal Oscillator 25 Calibrated Internal RC Oscillator 27 System Clock Prescalar 30 Power Management and Sleep Modes 32 Idle Mode 32 Power-down Mode 33 Standby Mode 33 Minimizing Power Consumption 33 System Control and Reset 35 Interrupts 46 Interrupt Vectors in ATtiny2313 46 I/O-Ports 48 ATtiny2313 Introduction 48 Ports as General Digital I/O 49 Alternate Port Functions 53 External Interrupts 61 Pin Change Interrupt Timing 61 8-bit Timer/Counter0 with PWM 64 Overview 64 Timer/Counter Clock Sources 65 Counter Unit 65 Output Compare Unit 66 Compare Match Output Unit 67 Modes of Operation 68 Timer/Counter Timing Diagrams 73 Timer/Counter0 and Timer/Counter1 Prescalers 82 16-bit Timer/Counter1 84 Overview 84 Accessing 16-bit Registers 86 Counter Unit 90 Input Capture Unit 91 Output Compare Units 92 Modes of Operation 96 USART 113 Overview 113 Clock Generation 114 Frame Formats 117 USART Initialization 118 Asynchronous Data Reception 126 Universal Serial Interface USI 140 Overview 140 Functional Descriptions 141 Alternative USI Usage 146 USI Register Descriptions 146 Analog Comparator 151 debugWIRE On-chip Debug System 153 Features 153 Overview 153 Physical Interface 153 Software Break Points 154 ii ATtiny2313 ATtiny2313 Limitations of debugWIRE 154 debugWIRE Related Register in I/O Memory 154 Self-Programming the Flash 155 Memory Programming 160 Program And Data Memory Lock Bits 160 Signature Bytes 162 Calibration Byte 162 Page Size 162 Parallel Programming Parameters, Pin Mapping, and Commands 163 Serial Programming Pin Mapping 165 Parallel Programming 165 Serial Downloading 174 External Clock Drive 181

PDF Datasheet Preview

• Utilizes the RISC Architecture
• AVR High-performance and Low-power RISC Architecture
120 Powerful Instructions Most Single Clock Cycle Execution 32 x 8 General Purpose Working Registers Fully Static Operation Up to 20 MIPS Throughput at 20 MHz
• Data and Non-volatile Program and Data Memories 2K Bytes of In-System Self Programmable Flash

Endurance 10,000 Write/Erase Cycles 128 Bytes In-System Programmable EEPROM

Endurance 100,000 Write/Erase Cycles 128 Bytes Internal SRAM Programming Lock for Flash Program and EEPROM Data Security
• Peripheral Features One 8-bit Timer/Counter with Separate Prescaler and Compare Mode One 16-bit Timer/Counter with Separate Prescaler, Compare and Capture Modes Four PWM Channels On-chip Analog Comparator Programmable Watchdog Timer with On-chip Oscillator USI Universal Serial Interface Full Duplex USART
• Special Microcontroller Features debugWIRE On-chip Debugging In-System Programmable via SPI Port External and Internal Interrupt Sources Low-power Idle, Power-down, and Standby Modes Enhanced Power-on Reset Circuit Programmable Brown-out Detection Circuit Internal Calibrated Oscillator
• I/O and Packages 18 Programmable I/O Lines 20-pin PDIP, 20-pin SOIC, 20-pad QFN/MLF
• Operating Voltages 5.5V ATtiny2313V 5.5V ATtiny2313
• Speed Grades ATtiny2313V 0 4 MHz - 5.5V, 0 10 MHz 5.5V ATtiny2313 0 10 MHz - 5.5V, 0 20 MHz 5.5V
• Typical Power Consumption Active Mode
1 MHz, 1.8V 230 µA 32 kHz, 1.8V 20 µA including oscillator Power-down Mode < µA at 1.8V
8-bit Microcontroller with 2K Bytes In-System Programmable Flash

ATtiny2313/V

Not recommended for new designs. Use ATtiny2313A

Figure Pinout ATtiny2313

Configurations

PDIP/SOIC

RESET/dW PA2 1 RXD PD0 2 TXD PD1 3

XTAL2 PA1 4 XTAL1 PA0 5 CKOUT/XCK/INT0 PD2 6

INT1 PD3 7

T0 PD4 8

OC0B/T1 PD5 9

GND 10
20 VCC 19 PB7 UCSK/SCL/PCINT7 18 PB6 MISO/DO/PCINT6 17 PB5 MOSI/DI/SDA/PCINT5 16 PB4 OC1B/PCINT4 15 PB3 OC1A/PCINT3 14 PB2 OC0A/PCINT2
13 PB1 AIN1/PCINT1
12 PB0 AIN0/PCINT0
11 PD6 ICP
20 PD0 RXD 19 PA2 RESET/dW 18 VCC 17 PB7 UCSK/SCK/PCINT7 16 PB6 MISO/DO/PCINT6

TXD PD1 1 XTAL2 PA1 2 XTAL1 PA0 3 CKOUT/XCK/INT0 PD2 4 INT1 PD3 5
15 PB5 MOSI/DI/SDA/PCINT5 14 PB4 OC1B/PCINT4 13 PB3 OC1A/PCINT3 12 PB2 OC0A/PCINT2 11 PB1 AIN1/PCINT1

T0 PD4 6 OC0B/T1 PD5 7

GND 8 ICP PD6 9 AIN0/PCINT0 PB0 10

Overview

NOTE Bottom pad should be soldered to ground.

The ATtiny2313 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny2313 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.
2 ATtiny2313

Block Diagram

Figure Block Diagram

ATtiny2313

PA0 - PA2

PORTA DRIVERS

VCC GND

DATA REGISTER PORTA

DATA DIR. REG. PORTA
8-BIT DATA BUS

PROGRAM COUNTER

PROGRAM FLASH
The parts are characterized at frequencies higher than test limits. Parts are not guaranteed to function properly at frequencies higher than the ordering code indicates.

The difference between current consumption in Power-down mode with Watchdog Timer enabled and Power-down mode with Watchdog Timer disabled represents the differential current drawn by the Watchdog Timer.

Active Supply Current Figure Active Supply Current vs. Frequency - MHz

ACTIVE SUPPLY CURRENT vs. LOW FREQUENCY
- MHz

ICC mA

Frequency MHz

Figure Active Supply Current vs. Frequency 1 - 20 MHz

ACTIVE SUPPLY CURRENT vs. FREQUENCY
1 - 20 MHz 14

ICC mA

Frequency MHz

Figure Active Supply Current vs. VCC Internal RC Oscillator, 8 MHz

ACTIVE SUPPLY CURRENT vs. VCC

INTERNAL RC OSCILLATOR, 8 MHz

ICC mA

VCC V
184 ATtiny2313

ATtiny2313

Figure Active Supply Current vs. VCC Internal RC Oscillator, 4 MHz

ACTIVE SUPPLY CURRENT vs. Vcc

INTERNAL RC OSCILLATOR, 4 MHz 6
-40 °C 85 °C 25 °C

Icc mA

Vcc V

Figure Active Supply Current vs. VCC Internal RC Oscillator, 1 MHz

ACTIVE SUPPLY CURRENT vs. Vcc

INTERNAL RC OSCILLATOR, 1 MHz
85 °C
25 °C
-40 °C

Icc mA

Vcc V

Figure Active Supply Current vs. VCC Internal RC Oscillator, MHz

ACTIVE SUPPLY CURRENT vs. Vcc

INTERNAL RC OSCILLATOR, MHz
1 85 °C
25 °C -40 °C

Icc mA

Vcc V

Figure Active Supply Current vs. VCC Internal RC Oscillator, 128 KHz
Ordering Information

Speed MHz 3

Power Supply
- 5.5V
- 5.5V
Ordering Code

ATtiny2313V-10PI ATtiny2313V-10PU 2 ATtiny2313V-10SI ATtiny2313V-10SU 2 ATtiny2313V-10MU 2

ATtiny2313-20PI ATtiny2313-20PU 2 ATtiny2313-20SI ATtiny2313-20SU 2 ATtiny2313-20MU 2

Package 1
20P3 20S 20M1
20P3 20S 20M1

Operation Range

Industrial -40°C to 85°C

Industrial -40°C to 85°C

Note:
This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities.

Pb-free packaging alternative, complies to the European Directive for Restriction of Hazardous Substances RoHS directive .Also Halide free and fully Green.

For Speed vs. VCC, see Figure 82 on page 182 and Figure 83 on page
20P3 20S 20M1

Package Type 20-lead, Wide, Plastic Dual Inline Package PDIP 20-lead, Wide, Plastic Gull Wing Small Outline Package SOIC 20-pad, 4 x 4 x mm Body, Quad Flat No-Lead/Micro Lead Frame Package MLF

Packaging Information
20P3

PIN 1

SEATING PLANE

A1 B B1

This package conforms to JEDEC reference MS-001, Variation AD. Dimensions D and E1 do not include mold Flash or Protrusion.

Mold Flash or Protrusion shall not exceed mm

COMMON DIMENSIONS Unit of Measure = mm

SYMBOL MIN

NOM MAX NOTE

Note 2

Note 2

TITLE 2325 Orchard Parkway 20P3, 20-lead mm Wide Plastic Dual R San Jose, CA 95131 Inline Package PDIP
1/12/04
20P3
218 ATtiny2313

ATtiny2313
20M1

Pin 1 ID 2

SIDE VIEW

TOP VIEW A2

D2 A1

Pin #1 Notch R

L e BOTTOM VIEW

Note Reference JEDEC Standard MO-220, Fig. 1 SAW Singulation WGGD-5.

COMMON DIMENSIONS Unit of Measure = mm

SYMBOL A A1 A2 b D D2 E E2 e L

NOM REF BSC

NOTE

TITLE 2325 Orchard Parkway 20M1, 20-pad, 4 x 4 x mm Body, Lead Pitch mm, R San Jose, CA 95131 mm Exposed Pad, Micro Lead Frame Package MLF
10/27/04
20M1
220 ATtiny2313

ATtiny2313

Errata
• Wrong values read after Erase Only operation
• Parallel Programming does not work
• Watchdog Timer Interrupt disabled
• EEPROM can not be written below volts
Updated typos. Updated Figure 1 on page Added “Resources” on page Updated “Default Clock Source” on page Updated “128 kHz Internal Oscillator” on page Updated “Power Management and Sleep Modes” on page 32 Updated Table 3 on page 25,Table 13 on page 32, Table 14 on page 33, Table 19 on page 44, Table 31 on page 62, Table 79 on page Updated “External Interrupts” on page Updated “Bit PCINT7..0 Pin Change Enable Mask on page Updated “Bit 6 ACBG Analog Comparator Bandgap Select” on page Updated “Calibration Byte” on page Updated “DC Characteristics” on page Updated “Register Summary” on page Updated “Ordering Information” on page Changed occurences of OCnA to OCFnA, OCnB to OCFnB and OC1x to OCF1x.
2514G-10/04 to

Updated Table 6 on page 27, Table 15 on page 36, Table 68 on page 162 and Table 80 on page

Changed CKSEL default value in “Default Clock Source” on page 25 to 8 MHz.

Updated “Programming the Flash” on page 167, “Programming the EEPROM” on page 169 and “Enter Programming Mode” on page

Updated “DC Characteristics” on page

MLF option updated to “Quad Flat No-Lead/Micro Lead Frame QFN/MLF ”
222 ATtiny2313

ATtiny2313
2514F-08/04 to
2514E-04/04 to
2514D-03/04 to
2514C-12/03 to
2514B-09/03 to
Updated “Features” on page Updated “Pinout ATtiny2313” on page Updated “Ordering Information” on page Updated “Packaging Information” on page Updated “Errata” on page

Updated “Features” on page Updated “Alternate Functions of Port B” on page Updated “Calibration Byte” on page Moved Table 69 on page 162 and Table 70 on page 162 to “Page Size” on page Updated “Enter Programming Mode” on page Updated “Serial Programming Algorithm” on page Updated Table 78 on page Updated “DC Characteristics” on page Updated “ATtiny2313 Typical Characteristics” on page Changed occurences of PCINT15 to PCINT7, EEMWE to EEMPE and EEWE to EEPE in the document.
Speed Grades changed - 12MHz to 10MHz - 24MHz to 20MHz Updated Figure 1 on page Updated “Ordering Information” on page Updated “Maximum Speed vs. VCC” on page Updated “ATtiny2313 Typical Characteristics” on page
Updated Table 2 on page Replaced “Watchdog Timer” on page Added “Maximum Speed vs. VCC” on page “Serial Programming Algorithm” on page 175 updated. Changed mA to µA in preliminary Figure 136 on page “Ordering Information” on page 217 updated. MLF package option removed Package drawing “20P3” on page 218 updated. Updated C-code examples. Renamed instances of SPMEN to SELFPRGEN, Self Programming Enable.

Updated “Calibrated Internal RC Oscillator” on page
2514A-09/03 to
Fixed typo from UART to USART and updated Speed Grades and Power Consumption Estimates in “Features” on page Updated “Pin Configurations” on page Updated Table 15 on page 36 and Table 80 on page Updated item 5 in “Serial Programming Algorithm” on page Updated “Electrical Characteristics” on page Updated Figure 82 on page 182 and added Figure 83 on page Changed SFIOR to GTCCR in “Register Summary” on page Updated “Ordering Information” on page Added new errata in “Errata” on page
224 ATtiny2313

Table of Contents

Features 1

Pin Configurations 2

Resources 6

About Code Examples 7

Disclaimer 8

AVR CPU Core 9

Introduction 9 Architectural Overview 9 ALU Arithmetic Logic Unit 10 Status Register 10 General Purpose Register File 11 Instruction Execution Timing 13 Reset and Interrupt Handling 14

AVR ATtiny2313 Memories 16

In-System Reprogrammable Flash Program Memory 16 EEPROM Data Memory 18 I/O Memory 22

System Clock and Clock Options 24

Clock Systems and their Distribution 24 Clock Sources 25 Default Clock Source 25 Crystal Oscillator 25 Calibrated Internal RC Oscillator 27 System Clock Prescalar 30

Power Management and Sleep Modes 32

Idle Mode 32 Power-down Mode 33 Standby Mode 33 Minimizing Power Consumption 33

System Control and Reset 35

Interrupts 46

Interrupt Vectors in ATtiny2313 46

I/O-Ports 48

ATtiny2313

Introduction 48 Ports as General Digital I/O 49 Alternate Port Functions 53

External Interrupts 61

Pin Change Interrupt Timing 61
8-bit Timer/Counter0 with PWM 64

Overview 64 Timer/Counter Clock Sources 65 Counter Unit 65 Output Compare Unit 66 Compare Match Output Unit 67 Modes of Operation 68 Timer/Counter Timing Diagrams 73

Timer/Counter0 and Timer/Counter1 Prescalers 82
16-bit Timer/Counter1 84

Overview 84 Accessing 16-bit Registers 86 Counter Unit 90 Input Capture Unit 91 Output Compare Units 92 Modes of Operation 96

USART 113

Overview 113 Clock Generation 114 Frame Formats 117 USART Initialization 118 Asynchronous Data Reception 126

Universal Serial Interface USI 140

Overview 140 Functional Descriptions 141 Alternative USI Usage 146 USI Register Descriptions 146

Analog Comparator 151
debugWIRE On-chip Debug System 153

Features 153 Overview 153 Physical Interface 153 Software Break Points 154
ii ATtiny2313

ATtiny2313

Limitations of debugWIRE 154 debugWIRE Related Register in I/O Memory 154

Self-Programming the Flash 155 Memory Programming 160

Program And Data Memory Lock Bits 160 Signature Bytes 162 Calibration Byte 162 Page Size 162 Parallel Programming Parameters, Pin Mapping, and Commands 163 Serial Programming Pin Mapping 165 Parallel Programming 165 Serial Downloading 174 External Clock Drive 181

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Datasheet ID: ATTINY2313V-10SJ 519323