ATTINY22L-1SC

ATTINY22L-1SC Datasheet


ATtiny22L

Part Datasheet
ATTINY22L-1SC ATTINY22L-1SC ATTINY22L-1SC (pdf)
Related Parts Information
ATTINY22L-1SI ATTINY22L-1SI ATTINY22L-1SI
ATTINY22L-1PI ATTINY22L-1PI ATTINY22L-1PI
ATTINY22L-1PC ATTINY22L-1PC ATTINY22L-1PC
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• Utilizes the RISC Architecture
• AVR - High-performance and Low-power RISC Architecture
118 Powerful Instructions - Most Single Clock Cycle Execution 32 x 8 General Purpose Working Registers Up to 1MIPS Throughput at 1MHz
• Data and Nonvolatile Program Memory 2K Bytes of In-System Programmable Flash

Endurance 1,000 Write/Erase Cycles 128 Bytes of internal SRAM 128 Bytes of In-System Programmable EEPROM

Endurance 100,000 Write/Erase Cycles Programming Lock for Flash Program and EEPROM Data Security
• Peripheral Features One 8-bit Timer/Counter with Separate Prescaler Programmable Watchdog Timer with On-chip Oscillator SPI Serial Interface for In-System Programming
• Special Microcontroller Features Low-power Idle and Power Down Modes External and Internal Interrupt Sources Power-on Reset Circuit On-chip RC Oscillator
• Specifications Low-power, High-speed CMOS Process Technology Fully Static Operation
• Power Consumption at 3V, 25°C Active mA Idle Mode 100 µA Power Down Mode <1 µA
• I/O and Packages 5 Programmable I/O Lines 8-pin PDIP and SOIC
• Operating Voltages - 6.0V
• Speed Grade Internal Oscillator ~1MHz 5.0V
8-bit Microcontroller with 2K Bytes of In-System Programmable Flash

ATtiny22L

The ATtiny22L is a low-power CMOS 8-bit microcontroller based on the AVR RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny22L achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.

The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit ALU ,

Pin Configuration

PDIP/SOIC

RESET 1 PB3 2 PB4 3 GND 4
8 VCC 7 PB2 SCK/T0 6 PB1 MISO/INT0 5 PB0 MOSI

Note This is a summary document. For the complete 56-page
document, please visit our web site at or e-mail a1t
and request literature #1273B.
allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.

Block Diagram

Figure The ATtiny22L Block Diagram

PROGRAM COUNTER
8-BIT DATA BUS

INTERNAL OSCILLATOR

STACK POINTER

WATCHDOG TIMER

TIMING AND CONTROL

RESET

PROGRAM FLASH

SRAM

MCU CONTROL REGISTER

INSTRUCTION REGISTER

INSTRUCTION DECODER

CONTROL LINES

GENERAL PURPOSE REGISTERS

TIMER/ COUNTER

INTERRUPT UNIT

EEPROM

STATUS REGISTER

PROGRAMMING LOGIC

DATA REGISTER PORTB

DATA DIR. REG. PORTB

PORTB DRIVERS

PB0 - PB4
Ordering Information

Power Supply - 6.0V

Speed MHz

Internal Osc
Ordering Code

ATtiny22L-1PC ATtiny22L-1SC

ATtiny22L-1PI ATtiny22L-1SI

ATtiny22L

Package
8P3 8S2
8P3 8S2

Operation Range

Commercial 0°C to 70°C

Industrial -40°C to 85°C

Package Type
8-pin, Wide, Plastic Dual Inline Package PDIP
8-lead, Wide, Plastic Gull-Wing Small Outline EIAJ SOIC

Packaging Information
8P3, 8-pin, Wide, Plastic Dual Inline Package PDIP Dimensions in Inches and Millimeters

JEDEC STANDARD MS-001 BA

PIN 1

SEATING PLANE
8S2, 8-lead, Wide, Plastic Gull Wing Small Outline EIAJ SOIC Dimensions in Inches and Millimeters

PIN 1

ATtiny22L

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Web Site

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Datasheet ID: ATTINY22L-1SC 519322