ATF2500CL-20JC

ATF2500CL-20JC Datasheet

ATF2500C CPLD Family Datasheet

Part	Datasheet
ATF2500CL-20JC	ATF2500CL-20JC (pdf)

PDF Datasheet Preview
• High-performance, High-density, Electrically-erasable Programmable Logic Device • Fully Connected Logic Array with 416 Product Terms • 15 ns Maximum Pin-to-pin Delay for 5V Operation • 24 Flexible Output Macrocells 48 Flip-flops Two per Macrocell 72 Sum Terms All Flip-flops, I/O Pins Feed in Independently • D- or T-type Flip-flops • Product Term or Direct Input Pin Clocking • Registered or Combinatorial Internal Feedback • Backward Compatible with ATV2500B/BQ and ATV2500H Software • Advanced Electrically-erasable Technology Reprogrammable 100% Tested • 44-lead Surface Mount Package and 40-pin DIP Package • Flexible Design Up to 48 Buried Flip-flops and 24 Combinatorial Outputs Simultaneously • 8 Synchronous Product Terms • Individual Asynchronous Reset per Macrocell • OE Control per Macrocell • Functionality Equivalent to ATV2500B/BQ and ATV2500H • 2000V ESD Protection • Security Fuse Feature to Protect the Code • Commercial, Industrial and Military Temperature Range Offered • 10 Year Data Retention • Pin Keeper Option • 200 mA Latch-up Immunity • Green Package Options Pb/Halide-free/RoHS Compliant Available ATF2500C CPLD Family Datasheet ATF2500C The ATF2500C is the highest-density PLD available in a 44-pin surface mount package. With its fully connected logic array and flexible macrocell structure, high gate utilization is easily obtainable. The ATF2500C is a high-performance CMOS electrically-erasable programmable logic device PLD that utilizes Atmel’s proven electrically-erasable technology. This PLD is now available in a fully Green or LHF lead and halide-free packages. Figure Block Diagram The ATF2500C is organized around a single universal array. All pins and feedback terms are always available to every macrocell. Each of the 38 logic pins are array inputs, as are the outputs of each flip-flop. In the ATF2500C, four product terms are input to each sum term. Furthermore, each macrocell’s three sum terms can be combined to provide up to 12 product terms per sum term with no performance penalty. Each flip-flop is individually selectable to be either D- or T-type, providing further logic compaction. Also, 24 of the flip-flops may be bypassed to provide internal combinatorial feedback to the logic array. Product terms provide individual clocks and asynchronous resets for each flip-flop. The flip-flops may also be individually configured to have direct input pin clocking. Each output has its own enable product term. Eight synchronous preset product terms serve local groups of either four or eight flip-flops. Register preload functions are provided to simplify testing. All registers automatically reset upon power-up. Pin Configurations Table Pin Name IN CLK/IN I/O I/O I/O GND VCC Pin Configurations Function Logic Inputs Pin Clock and Input Bi-directional Buffers Even I/O Buffers Odd I/O Buffers Ground +5V Supply Figure DIP CLK/IN 1 IN 2 IN 3 I/O0 4 I/O1 5 I/O2 6 I/O3 7 I/O4 8 I/O5 9 VCC 10 I/O17 11 I/O16 12 I/O15 13 I/O14 14 I/O13 15 I/O12 16 IN 17 IN 18 IN 19 IN 20 40 IN 39 IN 38 IN 37 IN 36 I/O6 35 I/O7 34 I/O8 33 I/O9 32 I/O10 31 I/O11 30 GND 29 I/O23 28 I/O22 27 I/O21 26 I/O20 25 I/O19 24 I/O18 23 IN 22 IN 21 IN Figure PLCC I/O2 7 I/O3 8 I/O4 9 I/O5 10 VCC 11 VCC 12 I/O17 13 I/O16 14 I/O15 15 I/O14 16 I/O13 17 6 I/O1 5 I/O0 4 GND 3 IN 2 IN 1 CLK/IN 44 IN 43 IN 42 IN 41 IN 40 I/O6 39 I/O7 38 I/O8 37 I/O9 36 I/O10 35 I/O11 34 GND 33 GND 32 I/O23 31 I/O22 30 I/O21 29 I/O20 I/O12 18 IN 19 IN 20 IN 21 IN 22 IN 23 IN 24 IN 25 GND 26 I/O18 27 I/O19 28 Note: PLCC package pin 4 and pin 26 GND connections are not required, but are recommended for improved noise immunity. 2 ATF2500C ATF2500C Using the ATF2500C Family’s Many Advanced Features The ATF2500Cs advanced flexibility packs more usable gates into 44 leads than other PLDs. Some of the ATF2500Cs key features are: • Fully Connected Logic Array Each array input is always available to every product term. This makes logic placement a breeze. • Selectable D- and T-Type Registers Each ATF2500C flip-flop can be individually configured as either D- or T-type. Using the T-type configuration, JK and SR flip-flops are also easily created. These options allow more efficient product term usage. • Buried Combinatorial Feedback Each macrocell’s Q2 register may be bypassed to feed its input D/T2 directly back to the logic array. This provides further logic expansion capability without using precious pin resources. • Selectable Synchronous/Asynchronous Clocking Each of the ATF2500Cs flip-flops has a dedicated clock product term. This removes the constraint that all registers use the same clock. Buried state machines, counters and registers can all coexist in one device while running on separate clocks. Individual flip-flop clock source selection further allows mixing higher performance pin clocking and flexible product term clocking within one design. • A Total of 48 Registers The ATF2500C provides two flip-flops per macrocell a total of Each register has its own clock and reset terms, as well as its own sum term. • Independent I/O Pin and Feedback Paths Each I/O pin on the ATF2500C has a dedicated input path. Each of the 48 registers has its own feedback term into the array as well. These features, combined with individual product terms for each I/O’s output enable, facilitate true bi-directional I/O design. • Combinable Sum Terms Each output macrocell’s three sum terms may be combined into a single term. This provides a fan in of up to 12 product terms per sum term with no speed penalty. • Programmable Pin-keeper Circuits These weak feedback latches are useful for bus interfacing applications. Floating pins can be set to a known state if the Pin-keepers are enabled. • User Row 64 bits Use to store information such as unit history. Power-up Reset The registers in the ATF2500Cs are designed to reset during power-up. At a point delayed slightly from VCC crossing VRST, all registers will be reset to the low state. The output state will depend on the polarity of the output buffer. This feature is critical for state as nature of reset and the uncertainty of how VCC actually rises in the system, the following conditions are required: Ordering Information Standard Package Options tCOS Ext. fMAXS MHz Ordering Code ATF2500C-15JC 52 ATF2500C-15JI ATF2500C-20JC ATF2500C-20PC 40 ATF2500C-20JI ATF2500C-20PI Package 44J 40P6 44J 40P6 Military Temperature Grade Standard Package Options tCOS Ext. fMAXS MHz Ordering Code Package ATF2500C-20KM 40 ATF2500C-20GM 44K 40D6 Green Package Options Pb/Halide-free/RoHS Compliant tCOS Ext. fMAXS MHz Ordering Code Package ATF2500C-15JU ATF2500C-20PU 40P6 Operation Range Commercial 0° C to 70° C Industrial -40° C to 85° C Commercial 0° C to 70° C Industrial -40° C to 85° C Operation Range Military -55° C to 125° C Operation Range Industrial -40° C to 85° C 40D6 40P6 44J 44K Package Type 40-lead, Non-windowed, Ceramic Dual Inline Package Cer DIP 40-pin, Wide, Plastic, Dual Inline Package PDIP 44-lead, Plastic J-leaded Chip Carrier PLCC 44-lead, Non-windowed, Ceramic J-leaded Chip Carrier JLCC 18 ATF2500C Packaging Information 40D6 DIP CerDIP ATF2500C Dimensions in Millimeters and Inches . Controlling dimension Inches. MIL-STD 1835 D-5 Config A Glass Sealed PIN 1 SEATING PLANE 2.54 0.100 BSC 0.127 0.005 MIN 0º~ 15º REF MAX TITLE 2325 Orchard Parkway 40D6, 40-lead, Wide, Non-windowed, R San Jose, CA 95131 Ceramic Dual Inline Package Cerdip 10/23/03 40D6 40P6 PDIP D PIN 1 SEATING PLANE 0º ~ 15º REF This package conforms to JEDEC reference MS-011, Variation AC. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed mm COMMON DIMENSIONS Unit of Measure = mm SYMBOL MIN NOM MAX NOTE Note 2 Note 2 TITLE 2325 Orchard Parkway 40P6, 40-lead mm Wide Plastic Dual R San Jose, CA 95131 Inline Package PDIP 09/28/01 40P6 20 ATF2500C History Added fully Green and Military temperatures packages in Section ”Ordering Information” on page Added 40-pin CerDIP Package Option. Headquarters Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel 1 408 441-0311 Fax 1 408 487-2600 International Atmel Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel 852 2721-9778 Fax 852 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel 33 1-30-60-70-00 Fax 33 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel 81 3-3523-3551 Fax 81 3-3523-7581 Product Contact Web Site Literature Requests Technical Support Sales Contact Disclaimer The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. Atmel Corporation All rights reserved. logo and combinations thereof, Everywhere You and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others.

PDF Datasheet Preview

• High-performance, High-density, Electrically-erasable Programmable Logic Device
• Fully Connected Logic Array with 416 Product Terms
• 15 ns Maximum Pin-to-pin Delay for 5V Operation
• 24 Flexible Output Macrocells
48 Flip-flops Two per Macrocell 72 Sum Terms All Flip-flops, I/O Pins Feed in Independently
• D- or T-type Flip-flops
• Product Term or Direct Input Pin Clocking
• Registered or Combinatorial Internal Feedback
• Backward Compatible with ATV2500B/BQ and ATV2500H Software
• Advanced Electrically-erasable Technology Reprogrammable 100% Tested
• 44-lead Surface Mount Package and 40-pin DIP Package
• Flexible Design Up to 48 Buried Flip-flops and 24 Combinatorial Outputs Simultaneously
• 8 Synchronous Product Terms
• Individual Asynchronous Reset per Macrocell
• OE Control per Macrocell
• Functionality Equivalent to ATV2500B/BQ and ATV2500H
• 2000V ESD Protection
• Security Fuse Feature to Protect the Code
• Commercial, Industrial and Military Temperature Range Offered
• 10 Year Data Retention
• Pin Keeper Option
• 200 mA Latch-up Immunity
• Green Package Options Pb/Halide-free/RoHS Compliant Available

ATF2500C CPLD Family Datasheet

ATF2500C

The ATF2500C is the highest-density PLD available in a 44-pin surface mount package. With its fully connected logic array and flexible macrocell structure, high gate utilization is easily obtainable. The ATF2500C is a high-performance CMOS electrically-erasable programmable logic device PLD that utilizes Atmel’s proven electrically-erasable technology. This PLD is now available in a fully Green or LHF lead and halide-free packages.

Figure Block Diagram

The ATF2500C is organized around a single universal array. All pins and feedback terms are always available to every macrocell. Each of the 38 logic pins are array inputs, as are the outputs of each flip-flop.

In the ATF2500C, four product terms are input to each sum term. Furthermore, each macrocell’s three sum terms can be combined to provide up to 12 product terms per sum term with no performance penalty. Each flip-flop is individually selectable to be either D- or T-type, providing further logic compaction. Also, 24 of the flip-flops may be bypassed to provide internal combinatorial feedback to the logic array.

Product terms provide individual clocks and asynchronous resets for each flip-flop. The flip-flops may also be individually configured to have direct input pin clocking. Each output has its own enable product term. Eight synchronous preset product terms serve local groups of either four or eight flip-flops. Register preload functions are provided to simplify testing. All registers automatically reset upon power-up.

Pin Configurations

Table Pin Name IN CLK/IN I/O I/O I/O GND VCC

Pin Configurations Function Logic Inputs Pin Clock and Input Bi-directional Buffers Even I/O Buffers Odd I/O Buffers Ground +5V Supply

Figure DIP

CLK/IN 1 IN 2 IN 3

I/O0 4 I/O1 5 I/O2 6 I/O3 7 I/O4 8 I/O5 9 VCC 10 I/O17 11 I/O16 12 I/O15 13 I/O14 14 I/O13 15 I/O12 16

IN 17 IN 18 IN 19 IN 20
40 IN 39 IN 38 IN 37 IN 36 I/O6 35 I/O7 34 I/O8 33 I/O9 32 I/O10 31 I/O11 30 GND 29 I/O23 28 I/O22 27 I/O21 26 I/O20 25 I/O19 24 I/O18 23 IN 22 IN 21 IN

Figure PLCC

I/O2 7 I/O3 8 I/O4 9 I/O5 10 VCC 11 VCC 12 I/O17 13 I/O16 14 I/O15 15 I/O14 16 I/O13 17
6 I/O1 5 I/O0 4 GND 3 IN 2 IN 1 CLK/IN 44 IN 43 IN 42 IN 41 IN 40 I/O6
39 I/O7 38 I/O8 37 I/O9 36 I/O10 35 I/O11 34 GND 33 GND 32 I/O23 31 I/O22 30 I/O21 29 I/O20

I/O12 18 IN 19 IN 20 IN 21 IN 22 IN 23 IN 24 IN 25

GND 26 I/O18 27 I/O19 28

Note:

PLCC package pin 4 and pin 26 GND connections are not required, but are recommended for improved noise immunity.
2 ATF2500C

ATF2500C

Using the ATF2500C Family’s Many Advanced Features

The ATF2500Cs advanced flexibility packs more usable gates into 44 leads than other PLDs. Some of the ATF2500Cs key features are:
• Fully Connected Logic Array Each array input is always available to every product term. This makes logic placement a breeze.
• Selectable D- and T-Type Registers Each ATF2500C flip-flop can be individually configured as either D- or T-type. Using the T-type configuration, JK and SR flip-flops are also easily created. These options allow more efficient product term usage.
• Buried Combinatorial Feedback Each macrocell’s Q2 register may be bypassed to feed its input D/T2 directly back to the logic array. This provides further logic expansion capability without using precious pin resources.
• Selectable Synchronous/Asynchronous Clocking Each of the ATF2500Cs flip-flops has a dedicated clock product term. This removes the constraint that all registers use the same clock. Buried state machines, counters and registers can all coexist in one device while running on separate clocks. Individual flip-flop clock source selection further allows mixing higher performance pin clocking and flexible product term clocking within one design.
• A Total of 48 Registers The ATF2500C provides two flip-flops per macrocell a total of Each register has its own clock and reset terms, as well as its own sum term.
• Independent I/O Pin and Feedback Paths Each I/O pin on the ATF2500C has a dedicated input path. Each of the 48 registers has its own feedback term into the array as well. These features, combined with individual product terms for each I/O’s output enable, facilitate true bi-directional I/O design.
• Combinable Sum Terms Each output macrocell’s three sum terms may be combined into a single term. This provides a fan in of up to 12 product terms per sum term with no speed penalty.
• Programmable Pin-keeper Circuits These weak feedback latches are useful for bus interfacing applications. Floating pins can be set to a known state if the Pin-keepers are enabled.
• User Row 64 bits Use to store information such as unit history.

Power-up Reset

The registers in the ATF2500Cs are designed to reset during power-up. At a point delayed slightly from VCC crossing VRST, all registers will be reset to the low state. The output state will depend on the polarity of the output buffer.

This feature is critical for state as nature of reset and the uncertainty of how VCC actually rises in the system, the following conditions are required:
Ordering Information

Standard Package Options
tCOS

Ext. fMAXS
MHz Ordering Code

ATF2500C-15JC 52

ATF2500C-15JI

ATF2500C-20JC

ATF2500C-20PC 40

ATF2500C-20JI

ATF2500C-20PI

Package
44J 40P6 44J 40P6

Military Temperature Grade Standard Package Options
tCOS

Ext. fMAXS
MHz Ordering Code

Package

ATF2500C-20KM 40

ATF2500C-20GM
44K 40D6

Green Package Options Pb/Halide-free/RoHS Compliant
tCOS

Ext. fMAXS
MHz Ordering Code

Package

ATF2500C-15JU

ATF2500C-20PU
40P6

Operation Range Commercial 0° C to 70° C Industrial
-40° C to 85° C Commercial 0° C to 70° C Industrial
-40° C to 85° C

Operation Range Military
-55° C to 125° C

Operation Range Industrial
-40° C to 85° C
40D6 40P6 44J 44K

Package Type 40-lead, Non-windowed, Ceramic Dual Inline Package Cer DIP 40-pin, Wide, Plastic, Dual Inline Package PDIP 44-lead, Plastic J-leaded Chip Carrier PLCC 44-lead, Non-windowed, Ceramic J-leaded Chip Carrier JLCC
18 ATF2500C

Packaging Information
40D6 DIP CerDIP

ATF2500C

Dimensions in Millimeters and Inches . Controlling dimension Inches. MIL-STD 1835 D-5 Config A Glass Sealed

PIN 1

SEATING PLANE
2.54 0.100 BSC
0.127 0.005 MIN
0º~ 15º REF MAX

TITLE 2325 Orchard Parkway 40D6, 40-lead, Wide, Non-windowed, R San Jose, CA 95131 Ceramic Dual Inline Package Cerdip
10/23/03
40D6
40P6 PDIP

D PIN 1

SEATING PLANE
0º ~ 15º REF

This package conforms to JEDEC reference MS-011, Variation AC. Dimensions D and E1 do not include mold Flash or Protrusion.

Mold Flash or Protrusion shall not exceed mm

COMMON DIMENSIONS Unit of Measure = mm

SYMBOL MIN NOM MAX NOTE

Note 2

Note 2

TITLE 2325 Orchard Parkway 40P6, 40-lead mm Wide Plastic Dual R San Jose, CA 95131 Inline Package PDIP
09/28/01
40P6
20 ATF2500C
History Added fully Green and Military temperatures packages in Section ”Ordering Information” on page Added 40-pin CerDIP Package Option.

Headquarters

Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel 1 408 441-0311 Fax 1 408 487-2600

International

Atmel Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel 852 2721-9778 Fax 852 2722-1369

Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel 33 1-30-60-70-00 Fax 33 1-30-60-71-11

Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel 81 3-3523-3551 Fax 81 3-3523-7581

Product Contact

Web Site

Literature Requests

Technical Support

Sales Contact

Disclaimer The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life.

Atmel Corporation All rights reserved. logo and combinations thereof, Everywhere You and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others.

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived ATF2500CL-20JC Datasheet file may be downloaded here without warranties.

Datasheet ID: ATF2500CL-20JC 519256