ATF1504AS-7AC100

ATF1504AS-7AC100 Datasheet

ATF1504AS ATF1504ASL

Part	Datasheet
ATF1504AS-7AC100	ATF1504AS-7AC100 (pdf)

Related Parts	Information
ATF1504AS-10JC68	ATF1504AS-10JC68
ATF1504AS-10QC100	ATF1504AS-10QC100
ATF1504AS-15AC100	ATF1504AS-15AC100
ATF1504AS-10JC84	ATF1504AS-10JC84
ATF1504AS-10AC100	ATF1504AS-10AC100
ATF1504AS-10JC44	ATF1504AS-10JC44
ATF1504AS-10AC44	ATF1504AS-10AC44
ATF1504AS-15AC44	ATF1504AS-15AC44
ATF1504AS-15AI100	ATF1504AS-15AI100
ATF1504AS-15JC68	ATF1504AS-15JC68
ATF1504AS-15JI68	ATF1504AS-15JI68
ATF1504AS-15JC84	ATF1504AS-15JC84
ATF1504AS-15JI44	ATF1504AS-15JI44
ATF1504AS-10AI100	ATF1504AS-10AI100
ATF1504AS-10AI44	ATF1504AS-10AI44
ATF1504AS-10JI44	ATF1504AS-10JI44
ATF1504AS-10JI68	ATF1504AS-10JI68
ATF1504AS-15AI44	ATF1504AS-15AI44
ATF1504AS-10QI100	ATF1504AS-10QI100
ATF1504AS-15JC44	ATF1504AS-15JC44
ATF1504AS-7QC100	ATF1504AS-7QC100
ATF1504AS-7JC84	ATF1504AS-7JC84
ATF1504AS-7JC68	ATF1504AS-7JC68
ATF1504AS-7JC44	ATF1504AS-7JC44
ATF1504AS-7AC44	ATF1504AS-7AC44
ATF1504AS-15QI100	ATF1504AS-15QI100
ATF1504AS-15QC100	ATF1504AS-15QC100
ATF1504AS-15JI84	ATF1504AS-15JI84
ATF1504AS-10JI84	ATF1504AS-10JI84

PDF Datasheet Preview
• High-density, High-performance, Electrically-erasable Complex Programmable Logic Device 64 Macrocells 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell 44, 68, 84, 100 Pins ns Maximum Pin-to-pin Delay Registered Operation up to 125 MHz Enhanced Routing Resources • In-System Programmability ISP via JTAG • Flexible Logic Macrocell D/T/Latch Configurable Flip-flops Global and Individual Register Control Signals Global and Individual Output Enable Programmable Output Slew Rate Programmable Output Open Collector Option Maximum Logic Utilization by Burying a Register with a COM Output • Advanced Power Management Features Automatic µA Standby for “L” Version Pin-controlled 1 mA Standby Mode Programmable Pin-keeper Circuits on Inputs and I/Os Reduced-power Feature per Macrocell • Available in Commercial and Industrial Temperature Ranges • Available in 44-, 68-, and 84-lead PLCC 44- and 100-lead TQFP and 100-lead PQFP • Advanced EE Technology 100% Tested Completely Reprogrammable 10,000 Program/Erase Cycles 20-year Data Retention 2000V ESD Protection 200 mA Latch-up Immunity • JTAG Boundary-scan Testing to IEEE Std. and 1149.1a-1993 Supported • PCI-compliant • 3.3V or 5.0V I/O Pins • Security Fuse Feature Enhanced Features • Improved Connectivity Additional Feedback Routing, Alternate Input Routing • Output Enable Product Terms • Transparent Latch Mode • Combinatorial Output with Registered Feedback within Any Macrocell • Three Global Clock Pins • ITD Input Transition Detection Circuits on Global Clocks, Inputs and I/O • Fast Registered Input from Product Term • Programmable “Pin-keeper” Option • VCC Power-up Reset Option • Pull-up Option on JTAG Pins TMS and TDI • Advanced Power Management Features Edge-controlled Power-down “L” Individual Macrocell Power Option Disable ITD on Global Clocks, Inputs and I/O Highperformance Complex Programmable Logic Device ATF1504AS ATF1504ASL 44-lead TQFP Top View 44 I/O 43 I/O 42 I/O 41 VCC 40 GCLK2/OE2/I 39 GCLR/I 38 I/OE1 37 GCLK1/I 36 GND 35 GCLK3/I/O 34 I/O I/O/TDI 1 I/O 2 I/O 3 GND 4 PD1/I/O 5 I/O 6 TMS/I/O 7 I/O 8 VCC 9 I/O 10 I/O 11 33 I/O 32 I/O/TDO 31 I/O 30 I/O 29 VCC 28 I/O 27 I/O 26 I/O/TCK 25 I/O 24 GND 23 I/O 44-lead PLCC Top View 6 I/O 5 I/O 4 I/O 3 VCC 2 GCLK2/OE2/I 1 GCLR/I 44 OE1/I 43 GCLK1/I 42 GND 41 GCLK3/I/O 40 I/O TDI/I/O 7 I/O 8 I/O 9 GND 10 PD1/I/O 11 I/O 12 I/O/TMS 13 I/O 14 VCC 15 I/O 16 I/O 17 39 I/O 38 I/O/TDO 37 I/O 36 I/O 35 VCC 34 I/O 33 I/O 32 I/O/TCK 31 I/O 30 GND 29 I/O I/O 18 I/O 19 I/O 20 I/O 21 GND 22 VCC 23 I/O 24 PD2/I/O 25 I/O 26 I/O 27 I/O 28 I/O 12 I/O 13 I/O 14 I/O 15 GND 16 VCC 17 I/O 18 PD2/I/O 19 I/O 20 I/O 21 I/O 22 68-lead PLCC Top View 84-lead PLCC Top View 11 I/O 10 I/O 9 I/O 8 I/O 7 GND 6 I/O 5 I/O 4 I/O 3 VCCINT 2 GCLK2/OE2/I 1 I/GCLR 84 I/OE1 83 GCLK1/I 82 GND 81 GCLK3/I/O 80 I/O 79 I/O 78 VCCIO 77 1/O 76 I/O 75 I/O 9 I/O 8 I/O 7 I/O 6 GND 5 I/O 4 I/O 3 VCCINT 2 GCLK2/OE2/I 1 GCLR/I 68 OE1/I 67 GCLK1/I 66 GND 65 GCLK3/I/O 64 I/O 63 VCCIO 62 I/O 61 I/O I/O 10 VCCIO 11 I/O/TD1 12 I/O 13 I/O 14 I/O 15 GND 16 I/O/PD1 17 I/O 18 I/O/TMS 19 I/O 20 VCCIO 21 I/O 22 I/O 23 I/O 24 I/O 25 GND 26 60 I/O 59 I/O 58 GND 57 I/O/TDO 56 I/O 55 I/O 54 I/O 53 VCCIO 52 I/O 51 I/O 50 I/O/TCK 49 I/O 48 GND 47 I/O 46 I/O 45 I/O 44 I/O I/O 12 VCCIO 13 I/O/TDI 14 I/O 15 I/O 16 I/O 17 I/O 18 GND 19 I/O/PD1 20 I/O 21 I/O 22 I/O/TMS 23 I/O 24 I/O 25 VCCIO 26 I/O 27 I/O 28 I/O 29 I/O 30 I/O 31 GND 32 74 I/O 73 I/O 72 GND 71 I/O/TDO 70 I/O 69 I/O 68 I/O 67 I/O 66 VCCIO 65 I/O 64 I/O 63 I/O 62 I/O/TCK 61 I/O 60 I/O 59 GND 58 I/O 57 I/O 56 I/O 55 I/O 54 I/O I/O 27 I/O 28 I/O 29 I/O 30 VCCIO 31 I/O 32 I/O 33 GND 34 VCCINT 35 I/O 36 I/O/PD2 37 GND 38 I/O 39 I/O 40 I/O 41 I/O 42 VCCIO 43 I/O 33 I/O 34 I/O 35 I/O 36 I/O 37 VCCIO 38 I/O 39 I/O 40 I/O 41 GND 42 VCCINT 43 I/O 44 I/O 45 I/O/PD2 46 GND 47 I/O 48 I/O 49 I/O 50 I/O 51 I/O 52 VCCIO 53 2 ATF1504AS L 100-lead PQFP Top View ATF1504AS L Note See ordering information for valid part numbers. -10 Min Max 125 -15 Min Max 100 2 8 1 6 3 -20 Min Max 2 10 1 7 3 -25 Min Max 60 2 12 8 4 Units MHz Timing Model AC Characteristics Continued Symbol Parameter Min Max Min Max Min Max Min Max Min Max Units Output Buffer Enable Delay tZX1 Slow slew rate = OFF; VCCIO = 5.0V CL = 35 pF Output Buffer Enable Delay tZX2 Slow slew rate = OFF; VCCIO = 3.3V CL = 35 pF Output Buffer Enable Delay tZX3 Slow slew rate = ON; VCCIO = 5.0V/3.3V CL = 35 pF Output Buffer Disable Delay CL = 5 pF Register Setup Time Register Hold Time tFSU Register Setup Time of Fast Input Register Hold Time of Fast Input Register Delay tCOMB Combinatorial Delay Array Clock Delay Register Enable Time tGLOB Global Control Delay tPRE Register Preset Time tCLR See ordering information for valid part numbers. The tRPA parameter must be added to the tLAD, tLAC,tTIC, tACL, and tSEXP parameters for macrocells running in the reducedpower mode. Input Test Waveforms and Measurement Levels tR, tF = ns typical 14 ATF1504AS L Output AC Test Loads ATF1504AS L Note *Numbers in parenthesis refer to 3.0V operating conditions preliminary . Power-down Mode The ATF1504AS includes an optional pin-controlled power-down feature. When this mode is enabled, the PD pin acts as the power-down pin. When the PD pin is high, the device supply current is reduced to less than 10 mA. During power-down, all output data and internal logic states are latched internally and held. Therefore, all registered and combinatorial output data remain valid. Any outputs that were in a high-Z state at the onset will remain at high-Z. During power-down, all input signals except the power-down pin are blocked. Input and I/O hold latches remain active to ensure that pins do not float to indeterminate levels, further reducing system power. The power-down mode feature is enabled in the logic design file or as a fitted or translated s/w option. Designs using the power-down pin may not use the PD pin as a logic array input. However, all other PD pin macrocell resources may still be used, including the buried feedback and foldback product term array inputs. Power Down AC Characteristics 1 2 Symbol Parameter Min Max tIVDH Valid I, I/O before PD High tGVDH Valid OE 2 before PD High tCVDH Valid Clock 2 before PD High tDHIX I, I/O Don’t Care after PD High tDHGX OE 2 Don’t Care after PD High tDHCX Clock 2 Don’t Care after PD High tDLIV PD Low to Valid I, I/O tDLGV PD Low to Valid OE Pin or Term tDLCV PD Low to Valid Clock Pin or Term tDLOV PD Low to Valid Output Notes For slow slew outputs, add tSSO. Pin or product term. Includes tRPA due to reduced power bit enabled. -10 Min Max 10 -15 Min Max 15 -20 Min Max 20 -25 Min Max 25 Units ns µs µs µs µs JTAG-BST/ISP Overview ATF1504AS Ordering Information tPD ns tCO1 ns fMAX MHz Ordering Code ATF1504AS-7 AC44 ATF1504AS-7 JC44 ATF1504AS-7 JC68 ATF1504AS-7 JC84 ATF1504AS-7 QC100 ATF1504AS-7 AC100 ATF1504AS-10 AC44 ATF1504AS-10 JC44 ATF1504AS-10 JC68 ATF1504AS-10 JC84 ATF1504AS-10 QC100 ATF1504AS-10 AC100 ATF1504AS-10 AI44 ATF1504AS-10 JI44 ATF1504AS-10 JI68 ATF1504AS-10 JI84 ATF1504AS-10 QI100 ATF1504AS-10 AI100 ATF1504AS-15 AC44 ATF1504AS-15 JC44 ATF1504AS-15 JC68 ATF1504AS-15 JC84 ATF1504AS-15 QC100 ATF1500AS-15 AC100 ATF1504AS-15 AI44 ATF1504AS-15 JI44 ATF1504AS-15 JI68 ATF1504AS-15 JI84 ATF1504AS-15 QI100 ATF1504AS-15 AI100 Package 44A 44J 68J 84J 100Q1 100A 44A 44J 68J 84J 100Q1 100A 44A 44J 68J 84J 100Q1 100A 44A 44J 68J 84J 100Q1 100A 44A 44J 68J 84J 100Q1 100A Operation Range Commercial 0°C to 70°C Commercial 0°C to 70°C Industrial -40°C to +85°C Commercial 0°C to 70°C Industrial -40°C to +85°C Using “C” Product for Industrial To use commercial product for Industrial temperature ranges, down-grade one speed grade from the “I” to the “C” device 7 ns “C” = 10 ns “I” and de-rate power by ATF1504ASL Ordering Information tPD ns tCO1 ns fMAX MHz Ordering Code ATF1504ASL-20 AC44 ATF1504ASL-20 JC44 ATF1504ASL-20 JC68 ATF1504ASL-20 JC84 ATF1504ASL-20 QC100 ATF1504ASL-20 AC100 ATF1504ASL-25 AI44 ATF1504ASL-25 JI84 ATF1504ASL-25 JI68 ATF1504ASL-25 JI84 ATF1504ASL-25 QI100 ATF1504ASL-25 AI100 Package 44A 44J 68J 84J 100Q1 100A 44A 44J 68J 84J 100Q1 100A Operation Range Commercial 0°C to 70°C Industrial -40°C to +85°C Using “C” Product for Industrial To use commercial product for Industrial temperature ranges, down-grade one speed grade from the “I” to the “C” device 7 ns “C” = 10 ns “I” and de-rate power by 26 ATF1504AS L Packaging Information 44A TQFP ATF1504AS L PIN 1 e PIN 1 IDENTIFIER B E1 E A1 A2 L This package conforms to JEDEC reference MS-026, Variation ACB. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. Lead coplanarity is mm maximum. COMMON DIMENSIONS Unit of Measure = mm SYMBOL MIN NOM MAX NOTE Note 2 Note 2 2325 Orchard Parkway R San Jose, CA 95131 44A, 44-lead, 10 x 10 mm Body Size, mm Body Thickness, mm Lead Pitch, Thin Profile Plastic Quad Flat Package TQFP 44J PLCC PIN NO. 1 IDENTIFIER e D1 D D2/E2 A2 A1 A 0.51 0.020 MAX 3X COMMON DIMENSIONS Unit of Measure = mm This package conforms to JEDEC reference MS-018, Variation AC. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is mm per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. Lead coplanarity is mm maximum. SYMBOL MIN NOM MAX NOTE Note 2 Note 2 D2/E2 TITLE 2325 Orchard Parkway 44J, 44-lead, Plastic J-leaded Chip Carrier PLCC R San Jose, CA 95131

PDF Datasheet Preview

• High-density, High-performance, Electrically-erasable Complex Programmable Logic Device 64 Macrocells 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell 44, 68, 84, 100 Pins ns Maximum Pin-to-pin Delay Registered Operation up to 125 MHz Enhanced Routing Resources
• In-System Programmability ISP via JTAG
• Flexible Logic Macrocell

D/T/Latch Configurable Flip-flops Global and Individual Register Control Signals Global and Individual Output Enable Programmable Output Slew Rate Programmable Output Open Collector Option Maximum Logic Utilization by Burying a Register with a COM Output
• Advanced Power Management Features Automatic µA Standby for “L” Version Pin-controlled 1 mA Standby Mode Programmable Pin-keeper Circuits on Inputs and I/Os Reduced-power Feature per Macrocell
• Available in Commercial and Industrial Temperature Ranges
• Available in 44-, 68-, and 84-lead PLCC 44- and 100-lead TQFP and 100-lead PQFP
• Advanced EE Technology 100% Tested Completely Reprogrammable 10,000 Program/Erase Cycles 20-year Data Retention 2000V ESD Protection 200 mA Latch-up Immunity
• JTAG Boundary-scan Testing to IEEE Std. and 1149.1a-1993 Supported
• PCI-compliant
• 3.3V or 5.0V I/O Pins
• Security Fuse Feature

Enhanced Features
• Improved Connectivity Additional Feedback Routing, Alternate Input Routing
• Output Enable Product Terms
• Transparent Latch Mode
• Combinatorial Output with Registered Feedback within Any Macrocell
• Three Global Clock Pins
• ITD Input Transition Detection Circuits on Global Clocks, Inputs and I/O
• Fast Registered Input from Product Term
• Programmable “Pin-keeper” Option
• VCC Power-up Reset Option
• Pull-up Option on JTAG Pins TMS and TDI
• Advanced Power Management Features

Edge-controlled Power-down “L” Individual Macrocell Power Option Disable ITD on Global Clocks, Inputs and I/O

Highperformance Complex Programmable Logic Device

ATF1504AS ATF1504ASL
44-lead TQFP Top View
44 I/O 43 I/O 42 I/O 41 VCC 40 GCLK2/OE2/I 39 GCLR/I 38 I/OE1 37 GCLK1/I 36 GND 35 GCLK3/I/O 34 I/O

I/O/TDI 1 I/O 2 I/O 3

GND 4 PD1/I/O 5

I/O 6 TMS/I/O 7

I/O 8 VCC 9

I/O 10 I/O 11
33 I/O 32 I/O/TDO 31 I/O 30 I/O 29 VCC 28 I/O 27 I/O 26 I/O/TCK 25 I/O 24 GND 23 I/O
44-lead PLCC Top View
6 I/O 5 I/O 4 I/O 3 VCC 2 GCLK2/OE2/I 1 GCLR/I 44 OE1/I 43 GCLK1/I 42 GND 41 GCLK3/I/O 40 I/O

TDI/I/O 7 I/O 8 I/O 9

GND 10 PD1/I/O 11

I/O 12 I/O/TMS 13

I/O 14 VCC 15

I/O 16 I/O 17
39 I/O 38 I/O/TDO 37 I/O 36 I/O 35 VCC 34 I/O 33 I/O 32 I/O/TCK 31 I/O 30 GND 29 I/O

I/O 18 I/O 19 I/O 20 I/O 21 GND 22 VCC 23 I/O 24 PD2/I/O 25 I/O 26 I/O 27 I/O 28

I/O 12 I/O 13 I/O 14 I/O 15 GND 16 VCC 17 I/O 18 PD2/I/O 19 I/O 20 I/O 21 I/O 22
68-lead PLCC Top View
84-lead PLCC Top View
11 I/O 10 I/O
9 I/O 8 I/O 7 GND 6 I/O 5 I/O 4 I/O 3 VCCINT 2 GCLK2/OE2/I 1 I/GCLR 84 I/OE1 83 GCLK1/I 82 GND 81 GCLK3/I/O 80 I/O 79 I/O 78 VCCIO 77 1/O 76 I/O 75 I/O
9 I/O 8 I/O 7 I/O 6 GND 5 I/O 4 I/O 3 VCCINT 2 GCLK2/OE2/I 1 GCLR/I 68 OE1/I 67 GCLK1/I 66 GND 65 GCLK3/I/O 64 I/O 63 VCCIO 62 I/O 61 I/O

I/O 10 VCCIO 11 I/O/TD1 12

I/O 13 I/O 14 I/O 15 GND 16 I/O/PD1 17 I/O 18 I/O/TMS 19 I/O 20 VCCIO 21 I/O 22 I/O 23 I/O 24 I/O 25 GND 26
60 I/O 59 I/O 58 GND 57 I/O/TDO 56 I/O 55 I/O 54 I/O 53 VCCIO 52 I/O 51 I/O 50 I/O/TCK 49 I/O 48 GND 47 I/O 46 I/O 45 I/O 44 I/O

I/O 12 VCCIO 13 I/O/TDI 14

I/O 15 I/O 16 I/O 17 I/O 18 GND 19 I/O/PD1 20 I/O 21 I/O 22 I/O/TMS 23 I/O 24 I/O 25 VCCIO 26 I/O 27 I/O 28 I/O 29 I/O 30 I/O 31 GND 32
74 I/O 73 I/O 72 GND 71 I/O/TDO 70 I/O 69 I/O 68 I/O 67 I/O 66 VCCIO 65 I/O 64 I/O 63 I/O 62 I/O/TCK 61 I/O 60 I/O 59 GND 58 I/O 57 I/O 56 I/O 55 I/O 54 I/O

I/O 27 I/O 28 I/O 29 I/O 30 VCCIO 31 I/O 32 I/O 33 GND 34 VCCINT 35 I/O 36 I/O/PD2 37 GND 38 I/O 39 I/O 40 I/O 41 I/O 42 VCCIO 43 I/O 33 I/O 34 I/O 35 I/O 36 I/O 37 VCCIO 38 I/O 39 I/O 40 I/O 41 GND 42 VCCINT 43 I/O 44 I/O 45 I/O/PD2 46 GND 47 I/O 48 I/O 49 I/O 50 I/O 51 I/O 52 VCCIO 53
2 ATF1504AS L
100-lead PQFP Top View

ATF1504AS L
Note See ordering information for valid part numbers.
-10 Min Max 125
-15 Min Max 100
2 8 1 6 3
-20 Min Max
2 10 1 7 3
-25 Min Max 60
2 12 8 4

Units MHz

Timing Model

AC Characteristics Continued

Symbol Parameter

Min Max Min Max Min Max Min Max Min Max Units

Output Buffer Enable Delay
tZX1

Slow slew rate = OFF;

VCCIO = 5.0V CL = 35 pF

Output Buffer Enable Delay
tZX2

Slow slew rate = OFF;

VCCIO = 3.3V CL = 35 pF

Output Buffer Enable Delay
tZX3

Slow slew rate = ON;

VCCIO = 5.0V/3.3V CL = 35 pF

Output Buffer Disable Delay CL = 5 pF

Register Setup Time

Register Hold Time
tFSU

Register Setup Time of Fast Input

Register Hold Time of Fast Input

Register Delay
tCOMB

Combinatorial Delay

Array Clock Delay

Register Enable Time
tGLOB

Global Control Delay
tPRE

Register Preset Time
tCLR
See ordering information for valid part numbers.

The tRPA parameter must be added to the tLAD, tLAC,tTIC, tACL, and tSEXP parameters for macrocells running in the reducedpower mode.

Input Test Waveforms and Measurement Levels
tR, tF = ns typical
14 ATF1504AS L

Output AC Test Loads

ATF1504AS L

Note *Numbers in parenthesis refer to 3.0V operating conditions preliminary .

Power-down Mode

The ATF1504AS includes an optional pin-controlled power-down feature. When this mode is enabled, the PD pin acts as the power-down pin. When the PD pin is high, the device supply current is reduced to less than 10 mA. During power-down, all output data and internal logic states are latched internally and held. Therefore, all registered and combinatorial output data remain valid. Any outputs that were in a high-Z state at the onset will remain at high-Z. During power-down, all input signals except the power-down pin are blocked. Input and I/O hold latches remain active to ensure that pins do not float to indeterminate levels, further reducing system power. The power-down mode feature is enabled in the logic design file or as a fitted or translated s/w option. Designs using the power-down pin may not use the PD pin as a logic array input. However, all other PD pin macrocell resources may still be used, including the buried feedback and foldback product term array inputs.

Power Down AC Characteristics 1 2

Symbol Parameter

Min Max
tIVDH

Valid I, I/O before PD High
tGVDH

Valid OE 2 before PD High
tCVDH

Valid Clock 2 before PD High
tDHIX

I, I/O Don’t Care after PD High
tDHGX

OE 2 Don’t Care after PD High
tDHCX

Clock 2 Don’t Care after PD High
tDLIV

PD Low to Valid I, I/O
tDLGV

PD Low to Valid OE Pin or Term
tDLCV

PD Low to Valid Clock Pin or Term
tDLOV

PD Low to Valid Output

Notes For slow slew outputs, add tSSO. Pin or product term.

Includes tRPA due to reduced power bit enabled.
-10 Min Max 10
-15 Min Max 15
-20 Min Max 20
-25 Min Max 25

Units ns µs µs µs µs

JTAG-BST/ISP Overview
ATF1504AS Ordering Information
tPD ns
tCO1 ns
fMAX MHz
Ordering Code

ATF1504AS-7 AC44 ATF1504AS-7 JC44 ATF1504AS-7 JC68 ATF1504AS-7 JC84 ATF1504AS-7 QC100 ATF1504AS-7 AC100

ATF1504AS-10 AC44 ATF1504AS-10 JC44 ATF1504AS-10 JC68 ATF1504AS-10 JC84 ATF1504AS-10 QC100 ATF1504AS-10 AC100

ATF1504AS-10 AI44 ATF1504AS-10 JI44 ATF1504AS-10 JI68 ATF1504AS-10 JI84 ATF1504AS-10 QI100 ATF1504AS-10 AI100

ATF1504AS-15 AC44 ATF1504AS-15 JC44 ATF1504AS-15 JC68 ATF1504AS-15 JC84 ATF1504AS-15 QC100 ATF1500AS-15 AC100

ATF1504AS-15 AI44 ATF1504AS-15 JI44 ATF1504AS-15 JI68 ATF1504AS-15 JI84 ATF1504AS-15 QI100 ATF1504AS-15 AI100

Package
44A 44J 68J 84J 100Q1 100A
44A 44J 68J 84J 100Q1 100A
44A 44J 68J 84J 100Q1 100A
44A 44J 68J 84J 100Q1 100A
44A 44J 68J 84J 100Q1 100A

Operation Range Commercial 0°C to 70°C

Commercial 0°C to 70°C

Industrial -40°C to +85°C

Commercial 0°C to 70°C

Industrial -40°C to +85°C

Using “C” Product for Industrial

To use commercial product for Industrial temperature ranges, down-grade one speed grade from the “I” to the “C” device 7 ns “C” = 10 ns “I” and de-rate power by
ATF1504ASL Ordering Information
tPD ns
tCO1 ns
fMAX MHz
Ordering Code

ATF1504ASL-20 AC44 ATF1504ASL-20 JC44 ATF1504ASL-20 JC68 ATF1504ASL-20 JC84 ATF1504ASL-20 QC100 ATF1504ASL-20 AC100

ATF1504ASL-25 AI44 ATF1504ASL-25 JI84 ATF1504ASL-25 JI68 ATF1504ASL-25 JI84 ATF1504ASL-25 QI100 ATF1504ASL-25 AI100

Package
44A 44J 68J 84J 100Q1 100A
44A 44J 68J 84J 100Q1 100A

Operation Range Commercial 0°C to 70°C

Industrial -40°C to +85°C

Using “C” Product for Industrial

To use commercial product for Industrial temperature ranges, down-grade one speed grade from the “I” to the “C” device 7 ns “C” = 10 ns “I” and de-rate power by
26 ATF1504AS L

Packaging Information
44A TQFP

ATF1504AS L

PIN 1 e

PIN 1 IDENTIFIER

B E1 E

A1 A2 L

This package conforms to JEDEC reference MS-026, Variation ACB. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. Lead coplanarity is mm maximum.

COMMON DIMENSIONS Unit of Measure = mm

SYMBOL MIN

NOM MAX

NOTE

Note 2 Note 2
2325 Orchard Parkway R San Jose, CA 95131
44A, 44-lead, 10 x 10 mm Body Size, mm Body Thickness, mm Lead Pitch, Thin Profile Plastic Quad Flat Package TQFP
44J PLCC

PIN NO. 1 IDENTIFIER
e D1 D

D2/E2

A2 A1 A
0.51 0.020 MAX 3X

COMMON DIMENSIONS Unit of Measure = mm

This package conforms to JEDEC reference MS-018, Variation AC. Dimensions D1 and E1 do not include mold protrusion.

Allowable protrusion is mm per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. Lead coplanarity is mm maximum.

SYMBOL MIN NOM MAX NOTE

Note 2

Note 2

D2/E2

TITLE 2325 Orchard Parkway 44J, 44-lead, Plastic J-leaded Chip Carrier PLCC R San Jose, CA 95131

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived ATF1504AS-7AC100 Datasheet file may be downloaded here without warranties.

Datasheet ID: ATF1504AS-7AC100 519251