ATF1502ASL-25JI44

ATF1502ASL-25JI44 Datasheet

ATF1502AS ATF1502ASL

Part	Datasheet
ATF1502ASL-25JI44	ATF1502ASL-25JI44 (pdf)

Related Parts	Information
ATF1502AS-10JC44	ATF1502AS-10JC44
ATF1502AS-10AC44	ATF1502AS-10AC44
ATF1502AS-7JC44	ATF1502AS-7JC44
ATF1502ASL-25JC44	ATF1502ASL-25JC44
ATF1502AS-10AI44	ATF1502AS-10AI44
ATF1502AS-10JI44	ATF1502AS-10JI44
ATF1502AS-7AC44	ATF1502AS-7AC44
ATF1502ASL-25AC44	ATF1502ASL-25AC44
ATF1502AS-15JI	ATF1502AS-15JI
ATF1502ASL-25AI44	ATF1502ASL-25AI44
ATF1502AS-15AC44	ATF1502AS-15AC44
ATF1502AS-15JI44	ATF1502AS-15JI44
ATF1502AS-15JC44	ATF1502AS-15JC44
ATF1502AS-15AI44	ATF1502AS-15AI44

PDF Datasheet Preview
• High-density, High-performance, Electrically-erasable Complex Programmable Logic Device 32 Macrocells 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell 44 Pins ns Maximum Pin-to-pin Delay Registered Operation up to 125 MHz Enhanced Routing Resources • In-System Programmability ISP via JTAG • Flexible Logic Macrocell D/T Latch Configurable Flip-flops Global and Individual Register Control Signals Global and Individual Output Enable Programmable Output Slew Rate Programmable Output Open Collector Option Maximum Logic Utilization by Burying a Register with a COM Output • Advanced Power Management Features • Automatic 10 µA Standby for “L” Version • Pin-controlled 1 mA Standby Mode • Programmable Pin-keeper Inputs and I/Os • Reduced-power Feature per Macrocell • Available in Commercial and Industrial Temperature Ranges • Available in 44-lead PLCC and TQFP • Advanced EEPROM Technology 100% Tested Completely Reprogrammable 10,000 Program/Erase Cycles 20-year Data Retention 2000V ESD Protection 200 mA Latch-up Immunity • JTAG Boundary-scan Testing to IEEE Std. and 1149.1a-1993 Supported • PCI-compliant • Security Fuse Feature Enhanced Features • Improved Connectivity Additional Feedback Routing, Alternate Input Routing • Output Enable Product Terms • D Latch Mode • Combinatorial Output with Registered Feedback within Any Macrocell • Three Global Clock Pins • ITD Input Transition Detection Circuits on Global Clocks, Inputs and I/O “L” versions • Fast Registered Input from Product Term • Programmable “Pin-keeper” Option • VCC Power-up Reset Option • Pull-up Option on JTAG Pins TMS and TDI • Advanced Power Management Features Input Transition Detection Power-down “L” versions Individual Macrocell Power Option Disable ITD on Global Clocks, Inputs and I/O Highperformance EEPROM CPLD ATF1502AS ATF1502ASL 44-lead TQFP Top View 44 I/O 43 I/O 42 I/O 41 VCC 40 GCLK2/OE2/I 39 GCLR/I 38 I/OE1 37 GCLK1/I 36 GND 35 GCLK3/I/O 34 I/O I/O/TDI 1 I/O 2 I/O 3 GND 4 PD1/I/O 5 I/O 6 TMS/I/O 7 I/O 8 VCC 9 I/O 10 I/O 11 33 I/O 32 I/O/TDO 31 I/O 30 I/O 29 VCC 28 I/O 27 I/O 26 I/O/TCK 25 I/O 24 GND 23 I/O I/O 12 I/O 13 I/O 14 I/O 15 GND 16 VCC 17 I/O 18 PD2/I/O 19 I/O 20 I/O 21 I/O 22 44-lead PLCC Top View 6 I/O 5 I/O 4 I/O 3 VCC 2 GCLK2/OE2/I 1 GCLR/I 44 OE1/I 43 GCLK1/I 42 GND 41 GCLK3/I/O 40 I/O TDI/I/O 7 I/O 8 I/O 9 GND 10 PD1/I/O 11 I/O 12 I/O/TMS 13 I/O 14 VCC 15 I/O 16 I/O 17 39 I/O 38 I/O/TDO 37 I/O 36 I/O 35 VCC 34 I/O 33 I/O 32 I/O/TCK 31 I/O 30 GND 29 I/O I/O 18 I/O 19 I/O 20 I/O 21 GND 22 VCC 23 I/O 24 PD2/I/O 25 I/O 26 I/O 27 I/O 28 The ATF1502AS is a high-performance, high-density complex programmable logic device CPLD that utilizes Atmel’s proven electrically-erasable technology. With 32 logic macrocells and up to 36 inputs, it easily integrates logic from several TTL, SSI, MSI, LSI and classic PLDs. The ATF1502AS’s enhanced routing switch matrices increase usable gate count and the odds of successful pin-locked design modifications. The ATF1502AS has up to 32 bi-directional I/O pins and four dedicated input pins, depending on the type of device package selected. Each dedicated pin can also serve as a global control signal, register clock, register reset or output enable. Each of these control signals can be selected for use individually within each macrocell. 2 ATF1502AS L Block Diagram ATF1502AS L Each of the 32 macrocells generates a buried feedback that goes to the global bus. Each input and I/O pin also feeds into the global bus. The switch matrix in each logic block then selects 40 individual signals from the global bus. Each macrocell also generates a foldback logic term that goes to a regional bus. Cascade logic between macrocells in the ATF1502AS allows fast, efficient generation of complex logic functions. The ATF1502AS contains four such logic chains, each capable of creating sum term logic with a fan-in of up to 40 product terms. The ATF1502AS macrocell, shown in Figure 1, is flexible enough to support highly complex logic functions operating at high speed. The macrocell consists of five sections product terms and product term select multiplexer, OR/XOR/CASCADE logic, a flip-flop, output select and enable, and logic array inputs. The ATF1502AS device is an in-system programmable ISP device. It uses the industry standard 4-pin JTAG interface IEEE Std. and is fully compliant with JTAG’s Boundaryscan Description Language BSDL . ISP allows the device to be programmed without removing it from the printed circuit board. In addition to simplifying the manufacturing flow, ISP also allows design modifications to be made in the field via software. Figure ATF1502AS Macrocell Product Terms and Select Mux Each ATF1502AS macrocell has five product terms. Each product term receives as its inputs all signals from both the global bus and regional bus. The product term select multiplexer PTMUX allocates the five product terms as needed to the macrocell logic gates and control signals. The PTMUX programming is determined by the design compiler, which selects the optimum macrocell configuration. OR/XOR/ CASCADE Logic The ATF1502AS’s logic structure is designed to efficiently support all types of logic. Within a single macrocell, all the product terms can be routed to the OR gate, creating a 5-input AND/OR sum term. With the addition of the CASIN from neighboring macrocells, this can be expanded to as many as 40 product terms with little additional delay. See ordering information for valid part numbers. The tRPA parameter must be added to the tLAD, tLAC,tTIC, tACL, and tSEXP parameters for macrocells running in the reducedpower mode. 16 ATF1502AS L ICC mA ICC mA SUPPLY CURRENT VS. SUPPLY VOLTAGE AS VERSION TA = 25°C, F = 0 STANDARD POWER 20 REDUCED POWER VCC V SUPPLY CURRENT VS. SUPPLY VOLTAGE PIN-CONTROLLED POWER-DOWN MODE TA = 25°C, F = 0 8 TBD VCC V SUPPLY CURRENT VS. FREQUENCY AS VERSION TA = 25°C STANDARD POWER REDUCED POWER FREQUENCY MHz OUTPUT SOURCE CURRENT VS. SUPPLY VOLTAGE VOH = 2.4V, TA = 25°C SUPPLY VOLTAGE V ICC mA IOH mA IOH mA ICC mA ATF1502AS L SUPPLY CURRENT VS. SUPPLY VOLTAGE T = 25°C, NON-TURBO, BIT6 = 0, BIT 30 = 0 VCC V ICC µA SUPPLY CURRENT VS. FREQUENCY ASL LOW-POWER VERSION TA = 25°C STANDARD POWER REDUCED POWER FREQUENCY MHz OUTPUT SOURCE CURRENT VS. OUTPUT VOLTAGE VCC = 5V, TA = 25°C OUTPUT VOLTAGE V INPUT CURRENT mA IOL mA 0 -10 -20 -30 -40 -50 -60 INPUT CLAMP CURRENT VS. INPUT VOLTAGE VCC = 5V, TA = 25°C INPUT VOLTAGE V 43 42 41 40 39 38 37 36 35 34 OUTPUT SINK CURRENT VS. SUPPLY VOLTAGE VOL = 0.5V, TA = 25°C SUPPLY VOLTAGE V Ordering Information tPD ns tCO1 ns fMAX MHz Ordering Code ATF1502AS-7 AC44 ATF1502AS-7 JC44 ATF1502AS-10 AC44 ATF1502AS-10 JC444 ATF1502AS-10 AI44 ATF1502AS-10 JI44 ATF1502AS-15 AC44 ATF1502AS-15 JC44 ATF1502AS-15 AI44 ATF1502AS-15 JI44 ATF1502ASL-25 AC44 ATF1502ASL-25 JC44 ATF1502ASL-25 AI44 ATF1502ASL-25 JI44 Package 44A 44J 44A 44J 44A 44J 44A 44J 44A 44J 44A 44J 44A 44J Operation Range Commercial 0°C to 70°C Commercial 0°C to 70°C Industrial -40°C to +85°C Commercial 0°C to 70°C Industrial -40°C to +85°C Commercial 0°C to 70°C Industrial -40°C to +85°C Using “C” Product for Industrial To use commercial product for industrial temperature ranges, down-grade one speed grade from the “I” to the “C” device 7 ns “C” = 10 ns “I” and de-rate power by Package Type 44-lead, Thin Plastic Gull Wing Quad Flatpack TQFP 44-lead, Plastic J-leaded Chip Carrier OTP PLCC 22 ATF1502AS L Packaging Information 44A TQFP ATF1502AS L PIN 1 e PIN 1 IDENTIFIER B E1 E A1 A2 L This package conforms to JEDEC reference MS-026, Variation ACB. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. Lead coplanarity is mm maximum. COMMON DIMENSIONS Unit of Measure = mm SYMBOL MIN NOM MAX NOTE Note 2 Note 2 2325 Orchard Parkway R San Jose, CA 95131 44A, 44-lead, 10 x 10 mm Body Size, mm Body Thickness, mm Lead Pitch, Thin Profile Plastic Quad Flat Package TQFP 44J PLCC PIN NO. 1 IDENTIFIER e D1 D D2/E2 A2 A1 A 0.51 0.020 MAX 3X COMMON DIMENSIONS Unit of Measure = mm This package conforms to JEDEC reference MS-018, Variation AC. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is mm per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. Lead coplanarity is mm maximum. SYMBOL MIN NOM MAX NOTE

PDF Datasheet Preview

• High-density, High-performance, Electrically-erasable Complex Programmable Logic Device 32 Macrocells 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell 44 Pins ns Maximum Pin-to-pin Delay Registered Operation up to 125 MHz Enhanced Routing Resources
• In-System Programmability ISP via JTAG
• Flexible Logic Macrocell

D/T Latch Configurable Flip-flops Global and Individual Register Control Signals Global and Individual Output Enable Programmable Output Slew Rate Programmable Output Open Collector Option Maximum Logic Utilization by Burying a Register with a COM Output
• Advanced Power Management Features
• Automatic 10 µA Standby for “L” Version
• Pin-controlled 1 mA Standby Mode
• Programmable Pin-keeper Inputs and I/Os
• Reduced-power Feature per Macrocell
• Available in Commercial and Industrial Temperature Ranges
• Available in 44-lead PLCC and TQFP
• Advanced EEPROM Technology 100% Tested Completely Reprogrammable 10,000 Program/Erase Cycles 20-year Data Retention 2000V ESD Protection 200 mA Latch-up Immunity
• JTAG Boundary-scan Testing to IEEE Std. and 1149.1a-1993 Supported
• PCI-compliant
• Security Fuse Feature

Enhanced Features
• Improved Connectivity Additional Feedback Routing, Alternate Input Routing
• Output Enable Product Terms
• D Latch Mode
• Combinatorial Output with Registered Feedback within Any Macrocell
• Three Global Clock Pins
• ITD Input Transition Detection Circuits on Global Clocks, Inputs and I/O
“L” versions
• Fast Registered Input from Product Term
• Programmable “Pin-keeper” Option
• VCC Power-up Reset Option
• Pull-up Option on JTAG Pins TMS and TDI
• Advanced Power Management Features

Input Transition Detection Power-down “L” versions Individual Macrocell Power Option Disable ITD on Global Clocks, Inputs and I/O

Highperformance EEPROM CPLD

ATF1502AS ATF1502ASL
44-lead TQFP Top View
44 I/O 43 I/O 42 I/O 41 VCC 40 GCLK2/OE2/I 39 GCLR/I 38 I/OE1 37 GCLK1/I 36 GND 35 GCLK3/I/O 34 I/O

I/O/TDI 1 I/O 2 I/O 3

GND 4 PD1/I/O 5

I/O 6 TMS/I/O 7

I/O 8 VCC 9

I/O 10 I/O 11
33 I/O 32 I/O/TDO 31 I/O 30 I/O 29 VCC 28 I/O 27 I/O 26 I/O/TCK 25 I/O 24 GND 23 I/O

I/O 12 I/O 13 I/O 14 I/O 15 GND 16 VCC 17 I/O 18 PD2/I/O 19 I/O 20 I/O 21 I/O 22
44-lead PLCC Top View
6 I/O 5 I/O 4 I/O 3 VCC 2 GCLK2/OE2/I 1 GCLR/I 44 OE1/I 43 GCLK1/I 42 GND 41 GCLK3/I/O 40 I/O

TDI/I/O 7 I/O 8 I/O 9

GND 10 PD1/I/O 11

I/O 12 I/O/TMS 13

I/O 14 VCC 15

I/O 16 I/O 17
39 I/O 38 I/O/TDO 37 I/O 36 I/O 35 VCC 34 I/O 33 I/O 32 I/O/TCK 31 I/O 30 GND 29 I/O

I/O 18 I/O 19 I/O 20 I/O 21 GND 22 VCC 23 I/O 24 PD2/I/O 25 I/O 26 I/O 27 I/O 28

The ATF1502AS is a high-performance, high-density complex programmable logic device CPLD that utilizes Atmel’s proven electrically-erasable technology. With 32 logic macrocells and up to 36 inputs, it easily integrates logic from several TTL, SSI, MSI, LSI and classic PLDs. The ATF1502AS’s enhanced routing switch matrices increase usable gate count and the odds of successful pin-locked design modifications.

The ATF1502AS has up to 32 bi-directional I/O pins and four dedicated input pins, depending on the type of device package selected. Each dedicated pin can also serve as a global control signal, register clock, register reset or output enable. Each of these control signals can be selected for use individually within each macrocell.
2 ATF1502AS L

Block Diagram

ATF1502AS L

Each of the 32 macrocells generates a buried feedback that goes to the global bus. Each input and I/O pin also feeds into the global bus. The switch matrix in each logic block then selects 40 individual signals from the global bus. Each macrocell also generates a foldback logic term that goes to a regional bus. Cascade logic between macrocells in the ATF1502AS allows fast, efficient generation of complex logic functions. The ATF1502AS contains four such logic chains, each capable of creating sum term logic with a fan-in of up to 40 product terms.

The ATF1502AS macrocell, shown in Figure 1, is flexible enough to support highly complex logic functions operating at high speed. The macrocell consists of five sections product terms and product term select multiplexer, OR/XOR/CASCADE logic, a flip-flop, output select and enable, and logic array inputs.

The ATF1502AS device is an in-system programmable ISP device. It uses the industry standard 4-pin JTAG interface IEEE Std. and is fully compliant with JTAG’s Boundaryscan Description Language BSDL . ISP allows the device to be programmed without removing it from the printed circuit board. In addition to simplifying the manufacturing flow, ISP also allows design modifications to be made in the field via software.

Figure ATF1502AS Macrocell

Product Terms and Select Mux

Each ATF1502AS macrocell has five product terms. Each product term receives as its inputs all signals from both the global bus and regional bus.

The product term select multiplexer PTMUX allocates the five product terms as needed to the macrocell logic gates and control signals. The PTMUX programming is determined by the design compiler, which selects the optimum macrocell configuration.

OR/XOR/ CASCADE Logic

The ATF1502AS’s logic structure is designed to efficiently support all types of logic. Within a single macrocell, all the product terms can be routed to the OR gate, creating a 5-input AND/OR sum term. With the addition of the CASIN from neighboring macrocells, this can be expanded to as many as 40 product terms with little additional delay.
See ordering information for valid part numbers.

The tRPA parameter must be added to the tLAD, tLAC,tTIC, tACL, and tSEXP parameters for macrocells running in the reducedpower mode.
16 ATF1502AS L

ICC mA

ICC mA

SUPPLY CURRENT VS. SUPPLY VOLTAGE AS VERSION TA = 25°C, F = 0

STANDARD POWER
20 REDUCED POWER

VCC V

SUPPLY CURRENT VS. SUPPLY VOLTAGE PIN-CONTROLLED POWER-DOWN MODE TA = 25°C, F = 0
8 TBD

VCC V

SUPPLY CURRENT VS. FREQUENCY AS VERSION TA = 25°C

STANDARD POWER

REDUCED POWER

FREQUENCY MHz

OUTPUT SOURCE CURRENT VS. SUPPLY VOLTAGE

VOH = 2.4V, TA = 25°C

SUPPLY VOLTAGE V

ICC mA

IOH mA

IOH mA

ICC mA

ATF1502AS L

SUPPLY CURRENT VS. SUPPLY VOLTAGE T = 25°C, NON-TURBO, BIT6 = 0, BIT 30 = 0

VCC V

ICC µA

SUPPLY CURRENT VS. FREQUENCY ASL LOW-POWER VERSION TA = 25°C

STANDARD POWER

REDUCED POWER

FREQUENCY MHz

OUTPUT SOURCE CURRENT VS. OUTPUT VOLTAGE VCC = 5V, TA = 25°C

OUTPUT VOLTAGE V

INPUT CURRENT mA

IOL mA
0 -10 -20 -30 -40 -50 -60

INPUT CLAMP CURRENT VS. INPUT VOLTAGE VCC = 5V, TA = 25°C

INPUT VOLTAGE V
43 42 41 40 39 38 37 36 35 34

OUTPUT SINK CURRENT VS. SUPPLY VOLTAGE VOL = 0.5V, TA = 25°C

SUPPLY VOLTAGE V
Ordering Information
tPD ns
tCO1 ns
fMAX MHz
Ordering Code ATF1502AS-7 AC44 ATF1502AS-7 JC44 ATF1502AS-10 AC44 ATF1502AS-10 JC444 ATF1502AS-10 AI44 ATF1502AS-10 JI44 ATF1502AS-15 AC44 ATF1502AS-15 JC44 ATF1502AS-15 AI44 ATF1502AS-15 JI44 ATF1502ASL-25 AC44 ATF1502ASL-25 JC44 ATF1502ASL-25 AI44 ATF1502ASL-25 JI44

Package 44A 44J 44A 44J 44A 44J 44A 44J 44A 44J 44A 44J 44A 44J

Operation Range

Commercial 0°C to 70°C Commercial 0°C to 70°C

Industrial -40°C to +85°C

Commercial 0°C to 70°C

Industrial -40°C to +85°C

Commercial 0°C to 70°C

Industrial -40°C to +85°C

Using “C” Product for Industrial

To use commercial product for industrial temperature ranges, down-grade one speed grade from the “I” to the “C” device 7 ns “C” = 10 ns “I” and de-rate power by

Package Type
44-lead, Thin Plastic Gull Wing Quad Flatpack TQFP
44-lead, Plastic J-leaded Chip Carrier OTP PLCC
22 ATF1502AS L

Packaging Information
44A TQFP

ATF1502AS L

PIN 1 e

PIN 1 IDENTIFIER

B E1 E

A1 A2 L

This package conforms to JEDEC reference MS-026, Variation ACB. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. Lead coplanarity is mm maximum.

COMMON DIMENSIONS Unit of Measure = mm

SYMBOL MIN

NOM MAX

NOTE

Note 2 Note 2
2325 Orchard Parkway R San Jose, CA 95131
44A, 44-lead, 10 x 10 mm Body Size, mm Body Thickness, mm Lead Pitch, Thin Profile Plastic Quad Flat Package TQFP
44J PLCC

PIN NO. 1 IDENTIFIER
e D1 D

D2/E2

A2 A1 A
0.51 0.020 MAX 3X

COMMON DIMENSIONS Unit of Measure = mm

This package conforms to JEDEC reference MS-018, Variation AC. Dimensions D1 and E1 do not include mold protrusion.

Allowable protrusion is mm per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. Lead coplanarity is mm maximum.

SYMBOL MIN NOM MAX NOTE

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived ATF1502ASL-25JI44 Datasheet file may be downloaded here without warranties.

Datasheet ID: ATF1502ASL-25JI44 519250