ATA6621N
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ATA6621N-PGQW (pdf) |
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• Supply Voltage up to 40V • Operating Voltage VS = 5V to 18V • Slew Rate Control according to LIN Specification • Supply Current during Sleep Mode Typically 10 µA • Supply Current in Silent Mode Typically 40 µA • Linear Low-drop Voltage Regulator: Normal Mode VCC = 5V ±2%/50 mA Silent Mode VCC = 5V ±7%/50 mA Sleep Mode VCC is Switched Off • VCC Undervoltage Detection 10 ms Reset time and Watchdog Reset Logically Combined at Output NRES • Possibility of Boosting the Voltage Regulator with an External NPN Transistor • LIN Physical Layer according to LIN Specification • Wake-up Capability via LIN Bus or WAKE Pin • Wake-up Recognition • TXD Time-out Timer • Debug Mode Watchdog Is Switched Off • 60V Load Dump Protection at LIN Pin • Bus Pin is Overtemperature and Short Circuit Protected versus GND and Battery • Adjustable Watchdog Time via External Resistor • Positive and Negative Trigger Input for Watchdog • 5V CMOS Compatible I/O Pins to MCU • Analog Temperature Monitor Output • High EMC and ESD Level • Package QFN 5 x 5 with 20 Pins LIN Transceiver with 5V Regulator and Watchdog ATA6621N The ATA6621N is a fully integrated LIN transceiver, complying with the LIN specification, and with a low-drop voltage regulator for 5V/50 mA output and a window watchdog adjustable via an external resistor. In this QFN20 package, the voltage regulator is able to source 50 mA at VS = 18V even at an ambient temperature of 105°C. The output current of the regulator can be boosted by using an external NPN transistor. This combination makes it possible to develop simple, but powerful and cheap, slave nodes in LIN bus systems. ATA6621N is designed to handle the low speed data communication in vehicles, for example, in convenience electronics. Improved slope control at the LIN driver ensures secure data communication up to 20 kBaud. The bus output is capable of withstanding 60V. Sleep mode and Silent mode guarantee a very low current consumption. Figure Block Diagram 9 RXD VCC Receiver Normal Mode 20 VS 4 WAKE 11 TXD 5 GND 17 TEMP 16 GND Filter 7 LIN TXD Time-out Timer Debounce Time Wake-up Bus Timer Slew Rate Control Short Circuit and Overtemperature Protection Control Unit Standby Mode Normal Mode 5V ± 2%/50 mA Silent Mode 5V ± 7%/50 mA Undervoltage Reset 19 VCC 18 PVCC 12 NRES Internal Testing Unit 15 14 MODE TM OUT Watchdog VCC 23 PTRIG NTRIG Adjustable Watchdog Oscillator 13 WD_OSC 2 ATA6621N Pin Configuration Figure Pinning QFN20 VS VCC PVCC TEMP GND 20 19 18 17 16 Ordering Information Extended Type Number ATA6621N-PGPW ATA6621N-PGQW Package Information Package QFN20 Package QFN 20 - 5 x 5 Exposed pad x Dimensions in mm Not indicated tolerances ± Drawing-No. Issue 1; Remarks Pb-free, 1.5k, taped and reeled Pb-free, 6k, taped and reeled 16 20 11 10 5 6 nom. technical drawings according to DIN specifications 26 ATA6621N ATA6621N History 4887I-AUTO-09/09 • Put datasheet in newest template • Heading Supply Pin VS text changed • El. Characteristics table row changed 4887H-AUTO-12/07 • Section “Physical Layer Compatibility” on page 3 added 4887G-AUTO-10/07 • Section 6 “Ordering Information” on page 26 changed • Put datasheet in a new template • Capital T for time generally changed in a lower case t • Section “Undervoltage Reset Output NRES ” on page 4 added • Section “Sleep Mode” on page 9 changed 4887F-AUTO-07/07 • Section “Fail-safe Features” on page 13 changed • Section “Voltage Regulator” on page 14 changed • Section “Watchdog” on page 14 changed • Section 4 “Absolute Maximum Ratings” on page 17 changed • Section 5 “Electrical Characteristics” numbers and changed • Section title on page 4 renamed • Section “TXD Dominant Time-out Function” on page 5 changed • Figure 3-3 “LIN Wake-up Waveform Diagram from Silent Mode on page 8 changed • Section “Pre-normal Mode” on page 9 changed • Figure 3-5 “LIN Wake-up Waveform Diagram from Sleep Mode” on page 10 changed • Section “Remote Wake-up via Dominant Bus State” on page 11 changed 4887E-AUTO-04/07 • Section “Local Wake-up via Pin Wake” on page 11 changed • Section “Wake-up Source Recognition” on page 11 changed • Figure 3-6 “Wake-up from Sleep/Silent Mode at an Insufficient Falling Edge at Pin LIN” on page 12 changed • Figure title 3-8 on page 14 renamed • Section 5 “Electrical Characteristics” number on page 18 changed • Figure 5-2 “Application Circuit” on page 24 changed • Figure 5-3 “Application Circuit with External NPN” on page 25 changed • Put datasheet in a new template • Table 2-1 “Pin Description” on page 3 changed • Section “Supply Pin VS ” on page 4 changed • Section “TXD Dominant Time-out Function” on page 5 changed • Section “Sleep Mode” on page 8 changed 4887D-AUTO-12/06 • Section in “Wake-up Scenarios from Silent or Sleep Mode” renamed • Section “Fail-safe Features” on page 11 changed • Section “Temperature Monitor at Pin TEMP” changed • Table “Electrical Characteristics” numbers and on pages 20 to 21 changed • Table “Electrical Characteristics” numbers and on page 22 added • Section 6 “Ordering Information” on page 25 changed Headquarters Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel 1 408 441-0311 Fax 1 408 487-2600 International Atmel Asia Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon Hong Kong Tel 852 2245-6100 Fax 852 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-en-Yvelines Cedex France Tel 33 1-30-60-70-00 Fax 33 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel 81 3-3523-3551 Fax 81 3-3523-7581 Product Contact Web Site Literature Requests Technical Support Sales Contact Disclaimer The information in this document is provided in connection with Atmel products. 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