AT94S10AL-25DGC

AT94S10AL-25DGC Datasheet

AT94S Secure Series Programmable SLI

Part	Datasheet
AT94S10AL-25DGC	AT94S10AL-25DGC (pdf)

Related Parts	Information
AT94S05AL-25DGI	AT94S05AL-25DGI
AT94S10AL-25DGI	AT94S10AL-25DGI
AT94S40AL-25DGC	AT94S40AL-25DGC
AT94S40AL-25DGI	AT94S40AL-25DGI
AT94S10AL-25BQI	AT94S10AL-25BQI
AT94S05AL-25DGC	AT94S05AL-25DGC
AT94S10AL-25BQC	AT94S10AL-25BQC

PDF Datasheet Preview
• Multichip Module Containing Field Programmable System Level Integrated Circuit and Secure Configuration EEPROM Memory • 512 Kbits to 1 Mbit of Configuration Memory with Security Protection and In-System Programming ISP • Field Programmable System Level Integrated Circuit FPSLIC AT40K SRAM-based FPGA with Embedded High-performance RISC Core and Extensive Data and Instruction SRAM • 5,000 to 40,000 Gates of Patented SRAM-based AT40K FPGA with FreeRAM 2 - Kbits of Distributed Single/Dual Port FPGA User SRAM High-performance DSP Optimized FPGA Core Cell Dynamically Reconfigurable In-System FPGA Configuration Access Available On-chip from AVR Microcontroller Core to Support Cache Designs Very Low Static and Dynamic Power Consumption Ideal for Portable and Handheld Applications • Patented AVR Enhanced RISC Architecture 120+ Powerful Instructions Most Single Clock Cycle Execution High-performance Hardware Multiplier for DSP-based Systems Approaching 1 MIPS per MHz Performance C Code Optimized Architecture with 32 x 8 General-purpose Internal Registers Low-power Idle, Power-save, and Power-down Modes 100 µA Standby and Typical 2-3 mA per MHz Active • Up to 36 Kbytes of Dynamically Allocated Instruction and Data SRAM Up to 16 Kbytes x 16 Internal 15 ns Instructions SRAM Up to 16 Kbytes x 8 Internal 15 ns Data SRAM • JTAG IEEE Std. Compliant Interface Extensive On-chip Debug Support Limited Boundary-scan Capabilities According to the JTAG Standards AVR Ports • AVR Fixed Peripherals Industry-standard 2-wire Serial Interface Two Programmable Serial UARTs Two 8-bit Timer/Counters with Separate Prescaler and PWM One 16-bit Timer/Counter with Separate Prescaler, Compare, Capture Modes and Dual 8-, 9- or 10-bit PWM • Support for FPGA Custom Peripherals AVR Peripheral Control Up to 16 Decoded AVR Address Lines Directly Accessible to FPGA Macro Library of Custom Peripherals • Up to 16 FPGA Supplied Internal Interrupts to AVR • Up to Four External Interrupts to AVR • 8 Global FPGA Clocks Two FPGA Clocks Driven from AVR Logic FPGA Global Clock Access Available from FPGA Core • Multiple Oscillator Circuits Programmable Watchdog Timer with On-chip Oscillator to AVR Internal Clock Circuit Software-selectable Clock Frequency Oscillator to Timer/Counter for Real-time Clock Secure 5K - 40K Gates of AT40K FPGA with 8-bit Microcontroller, up to 36 Kbytes of SRAM and On-chip Program Storage EEPROM AT94S Secure Series Programmable SLI • VCC 3.0V - 3.6V • 5V Tolerant I/O • 3.3V 33 MHz PCI Compliant FPGA I/O 20 mA Sink/Source High-performance I/O Structures All FPGA I/O Individually Programmable • High-performance, Low-power CMOS Five-layer Metal Process • State-of-the-art Integrated PC-based Software Suite including Co-verification The AT94S Series Secure FPSLIC family shown in Table 1-1 is a combination of the popular Atmel AT40K Series SRAM FPGAs, the AT17 Series Configuration Memories and the high-performance Atmel AVR 8-bit RISC microcontroller with standard peripherals. Extensive data and instruction SRAM as well as device control and management logic are included in this multi-chip module MCM . The embedded AT40K FPGA core is a fully 3.3V PCI-compliant, SRAM-based FPGA with distributed 10 ns programmable synchronous/asynchronous, dual-port/single-port SRAM, 8 global clocks, Cache Logic ability partially or fully reconfigurable without loss of data and 5,000 to 40,000 usable gates. Table The AT94S Series Family Device AT94S05AL Configuration Memory Size 1 Mbit FPGA Gates FPGA Core Cells FPGA SRAM Bits 2048 FPGA Registers Total Maximum FPGA User I/O AVR Programmable I/O Lines Program SRAM Bytes 4K - 16K Data SRAM Bytes 4K - 16K Hardware Multiplier 8-bit 2-wire Serial Interface UARTs Watchdog Timer Timer/Counters Real-time Clock JTAG ICE Typical AVR Throughput Bit Ordering Protocol The most significant bit is the first bit of a byte transmitted on the cSDA line for the Device Address Byte and the EEPROM Address Bytes. It is followed by the lesser significant bits until the eighth bit, the least significant bit, is transmitted. However, for Data Bytes both writing and reading , the first bit transmitted is the least significant bit. This protocol is shown in the diagrams below. Device Address Byte The contents of the Device Address Byte are shown below, along with the order in which the bits are clocked into the device. The CE pin cannot be used for device selection in programming mode i.e., when SER_EN is drive Low . Figure Start and Stop Conditions cSCK cSDA 8th Bit ACK BIT Byte n Table MSB 1 1st Device Address Byte Where:R/W=1 Read = 0 Write STOP Condition START Condition 6 AT94S Secure Family AT94S Secure Family EEPROM Address Byte Order 512-Kbit/1-Mbit Page Length 0 AE16 ACK AE15 AE14 AE13 AE12 AE11 AE10 AE9 AE8 ACK AE7 AE6 AE5 AE4 AE3 AE2 AE1 AE0 ACK 1st 2nd 3rd 4th 5th 6th 7th 8th 1st 2nd 3rd 4th 5th 6th 7th 8th 1st 2nd 3rd 4th 5th 6th 7th 8th 512-Kbit Address Space 1-Mbit Address Space The EEPROM Address consists of three bytes on the 1-Mbit part. Each Address Byte is followed by an Acknowledge Bit provided by the Configurator . These bytes define the normal address space of the Configurator. The order in which each byte is clocked into the Configurator is also indicated. Unused bits in an Address Byte must be set to Exceptions to this are when reading Device and Manufacturer Codes. Programming Summary Write to Whole Device START SER_EN Low PAGE_COUNT 0 Send Start Condition BYTE_COUNT 0 Send Device Address ACK? Send MSB of EEPROM Address 1 ACK? Middle Byte EEPROM Address ACK? Send LSB of EEPROM Address 1 ACK? Note The Manufacturer’s Code and Device Code are read using the byte ordering specified for Data Bytes i.e., LSB first, MSB last. Programming the Device All the bytes in a given page must be written. The page access order is not important but it is suggested that the Configurator be written sequentially from address Writing is accomplished by using the cSDA and cSCK pins. Important Note on AT94S Series Configurators Programming The first byte of data will not be cached for read back during FPGA Configuration i.e., when SER_EN is driven High until the Configurator is power-cycled. Verifying the Device All bytes in the Configurator should be read and compared to their intended values. Reading is done using the cSDA and cSCK pins. 12 AT94S Secure Family AT94S Secure Family In-System Programming Applications The AT94S Series Configurators are in-system re programmable ISP . The example shown on the following page supports the following programmer functions: Read the Manufacturer’s Code and the Device Code. Program the device. Verify the device data. While Atmel’s Secure FPSLIC Configurators can be programmed from various sources e.g., onboard microcontrollers or PLDs , the applications shown here are designed to facilitate users of our ATDH2225 Configurator Programming Cable. The typical system setup is shown in Figure The pages within the configuration EEPROM can be selectively rewritten. This document is limited to example implementations for Atmel’s AT94S application. Figure Typical System Setup 10-pin Ribbon Cable Target System Secure FPSLIC ATDH2225 10 PC Programming Dongle In-System Programming Connector Header The diode connection between the AT94S’ RESET pin and the SER_EN signal allows the external programmer to force the FPGA into a reset state during ISP. This eliminates the potential for contention on the cSCK line. The pull-up resistors required on the lines to RESET, CON and INIT are present on the inputs internally to the AT94S FPSLIC, see Figure Figure ISP of the AT17LV512/010 in an AT94S FPSLIC Application cSDA 1 cSCK 3 4 VCC 6 8 10 RESET AT94S RESET SER_EN DATA0 cSDA 1 CLK cSCK 1 M2 INIT RESET/OE 1 CON CE 1 SER_EN Note Configurator signal names are shown in parenthesis. Figure Serial Data Timing Diagram t LOW t HIGH cSCK t HD.STA Ordering Information Usable Gates Speed Grade 5,000 25 MHz 10,000 25 MHz 40,000 16 MHz Ordering Code AT94S05AL-25DGC AT94S05AL-25BQC AT94S05AL-25DGI AT94S05AL-25BQI AT94S10AL-25DGC AT94S10AL-25BQC AT94S10AL-25DGI AT94S10AL-25BQI AT94S40AL-25DGC AT94S40AL-25DGI AT94S Secure Family Package 256ZA 144L1 256ZA 144L1 256ZA 144L1 256ZA 144L1 256ZA 256ZA Operation Range Commercial 0°C - 70°C Industrial -40°C - 85°C Commercial 0°C - 70°C Industrial -40°C - 85°C Commercial 0°C - 70°C Industrial -40°C - 85°C 256ZA 144L1 Package Type 256-ball, Chip Array Ball Grid Array Package CABGA 144-lead, Low Profile Plastic Gull Wing Quad Flat Package LQFP Packaging Information 256ZA CABGA A1 Ball Pad Corner Top View A1 Ball Pad Corner 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bottom View 256 SOLDER BALLS Side View SYMBOL D E A A1 A2 A3 COMMON DIMENSIONS Unit of Measure = mm NOM 17 BSC 17 BSC BSC REF NOTE Notes This drawing is for general information only. Refer to JEDEC Drawing MO-205 for proper dimensions, tolerances, datums, etc. Array as seen from the bottom of the package. 2325 Orchard Parkway R San Jose, CA 95131 TITLE 256ZA, 256-ball 16 x 16 Array , 17 x 17 mm Body, Chip Array Ball Grid Array CABGA Package 11/07/01 256ZA 30 AT94S Secure Family 144L1 LQFP AT94S Secure Family Top View A2 A1 Side View Bottom View

PDF Datasheet Preview

• Multichip Module Containing Field Programmable System Level Integrated Circuit and Secure Configuration EEPROM Memory
• 512 Kbits to 1 Mbit of Configuration Memory with Security Protection and In-System Programming ISP
• Field Programmable System Level Integrated Circuit FPSLIC AT40K SRAM-based FPGA with Embedded High-performance RISC Core and Extensive Data and Instruction SRAM
• 5,000 to 40,000 Gates of Patented SRAM-based AT40K FPGA with FreeRAM 2 - Kbits of Distributed Single/Dual Port FPGA User SRAM High-performance DSP Optimized FPGA Core Cell Dynamically Reconfigurable In-System FPGA Configuration Access Available On-chip from AVR Microcontroller Core to Support Cache Designs Very Low Static and Dynamic Power Consumption Ideal for Portable and Handheld Applications
• Patented AVR Enhanced RISC Architecture 120+ Powerful Instructions Most Single Clock Cycle Execution High-performance Hardware Multiplier for DSP-based Systems Approaching 1 MIPS per MHz Performance C Code Optimized Architecture with 32 x 8 General-purpose Internal Registers Low-power Idle, Power-save, and Power-down Modes 100 µA Standby and Typical 2-3 mA per MHz Active
• Up to 36 Kbytes of Dynamically Allocated Instruction and Data SRAM Up to 16 Kbytes x 16 Internal 15 ns Instructions SRAM Up to 16 Kbytes x 8 Internal 15 ns Data SRAM
• JTAG IEEE Std. Compliant Interface Extensive On-chip Debug Support Limited Boundary-scan Capabilities According to the JTAG Standards AVR Ports
• AVR Fixed Peripherals Industry-standard 2-wire Serial Interface Two Programmable Serial UARTs Two 8-bit Timer/Counters with Separate Prescaler and PWM One 16-bit Timer/Counter with Separate Prescaler, Compare, Capture Modes and Dual 8-, 9- or 10-bit PWM
• Support for FPGA Custom Peripherals AVR Peripheral Control Up to 16 Decoded AVR Address Lines Directly Accessible to FPGA Macro Library of Custom Peripherals
• Up to 16 FPGA Supplied Internal Interrupts to AVR
• Up to Four External Interrupts to AVR
• 8 Global FPGA Clocks

Two FPGA Clocks Driven from AVR Logic FPGA Global Clock Access Available from FPGA Core
• Multiple Oscillator Circuits Programmable Watchdog Timer with On-chip Oscillator to AVR Internal Clock Circuit Software-selectable Clock Frequency Oscillator to Timer/Counter for Real-time Clock

Secure 5K - 40K Gates of AT40K FPGA with 8-bit Microcontroller, up to 36 Kbytes of SRAM and On-chip Program Storage EEPROM

AT94S Secure Series Programmable SLI
• VCC 3.0V - 3.6V
• 5V Tolerant I/O
• 3.3V 33 MHz PCI Compliant FPGA I/O
20 mA Sink/Source High-performance I/O Structures All FPGA I/O Individually Programmable
• High-performance, Low-power CMOS Five-layer Metal Process
• State-of-the-art Integrated PC-based Software Suite including Co-verification

The AT94S Series Secure FPSLIC family shown in Table 1-1 is a combination of the popular Atmel AT40K Series SRAM FPGAs, the AT17 Series Configuration Memories and the high-performance Atmel AVR 8-bit RISC microcontroller with standard peripherals. Extensive data and instruction SRAM as well as device control and management logic are included in this multi-chip module MCM .

The embedded AT40K FPGA core is a fully 3.3V PCI-compliant, SRAM-based FPGA with distributed 10 ns programmable synchronous/asynchronous, dual-port/single-port SRAM, 8 global clocks, Cache Logic ability partially or fully reconfigurable without loss of data and 5,000 to 40,000 usable gates.

Table The AT94S Series Family

Device

AT94S05AL

Configuration Memory Size
1 Mbit

FPGA Gates

FPGA Core Cells

FPGA SRAM Bits
2048

FPGA Registers Total

Maximum FPGA User I/O

AVR Programmable I/O Lines

Program SRAM Bytes
4K - 16K

Data SRAM Bytes
4K - 16K

Hardware Multiplier 8-bit
2-wire Serial Interface

UARTs

Watchdog Timer

Timer/Counters

Real-time Clock

JTAG ICE

Typical AVR Throughput
Bit Ordering Protocol

The most significant bit is the first bit of a byte transmitted on the cSDA line for the Device Address Byte and the EEPROM Address Bytes. It is followed by the lesser significant bits until the eighth bit, the least significant bit, is transmitted. However, for Data Bytes both writing and reading , the first bit transmitted is the least significant bit. This protocol is shown in the diagrams below.

Device Address Byte

The contents of the Device Address Byte are shown below, along with the order in which the bits are clocked into the device.

The CE pin cannot be used for device selection in programming mode i.e., when SER_EN is drive Low .

Figure Start and Stop Conditions
cSCK
cSDA
8th Bit

ACK BIT

Byte n

Table MSB 1 1st

Device Address Byte

Where:R/W=1 Read = 0 Write

STOP Condition

START

Condition
6 AT94S Secure Family

AT94S Secure Family

EEPROM Address

Byte Order
512-Kbit/1-Mbit Page Length
0 AE16 ACK AE15 AE14 AE13 AE12 AE11 AE10 AE9 AE8 ACK AE7 AE6 AE5 AE4 AE3 AE2 AE1 AE0 ACK
1st 2nd 3rd 4th 5th 6th 7th 8th
1st 2nd 3rd 4th 5th 6th 7th 8th
1st 2nd 3rd 4th 5th 6th 7th 8th
512-Kbit Address Space
1-Mbit Address Space

The EEPROM Address consists of three bytes on the 1-Mbit part. Each Address Byte is followed by an Acknowledge Bit provided by the Configurator . These bytes define the normal address space of the Configurator. The order in which each byte is clocked into the Configurator is also indicated. Unused bits in an Address Byte must be set to Exceptions to this are when reading Device and Manufacturer Codes.

Programming Summary Write to Whole Device

START

SER_EN Low PAGE_COUNT 0

Send Start Condition BYTE_COUNT 0

Send Device Address

ACK?

Send MSB of EEPROM Address 1

ACK?

Middle Byte EEPROM Address

ACK?

Send LSB of EEPROM Address 1

ACK?
Note The Manufacturer’s Code and Device Code are read using the byte ordering specified for Data Bytes i.e., LSB first, MSB last.

Programming the Device All the bytes in a given page must be written. The page access order is not important but it is suggested that the Configurator be written sequentially from address Writing is accomplished by using the cSDA and cSCK pins.

Important Note on AT94S Series Configurators Programming The first byte of data will not be cached for read back during FPGA Configuration i.e., when SER_EN is driven High until the Configurator is power-cycled.

Verifying the Device All bytes in the Configurator should be read and compared to their intended values. Reading is done using the cSDA and cSCK pins.
12 AT94S Secure Family

AT94S Secure Family

In-System Programming Applications

The AT94S Series Configurators are in-system re programmable ISP . The example shown on the following page supports the following programmer functions:

Read the Manufacturer’s Code and the Device Code. Program the device. Verify the device data.

While Atmel’s Secure FPSLIC Configurators can be programmed from various sources e.g., onboard microcontrollers or PLDs , the applications shown here are designed to facilitate users of our ATDH2225 Configurator Programming Cable. The typical system setup is shown in Figure

The pages within the configuration EEPROM can be selectively rewritten.

This document is limited to example implementations for Atmel’s AT94S application.

Figure Typical System Setup
10-pin Ribbon Cable

Target System

Secure FPSLIC

ATDH2225
10 PC

Programming Dongle

In-System Programming

Connector Header

The diode connection between the AT94S’ RESET pin and the SER_EN signal allows the external programmer to force the FPGA into a reset state during ISP. This eliminates the potential for contention on the cSCK line. The pull-up resistors required on the lines to RESET, CON and INIT are present on the inputs internally to the AT94S FPSLIC, see Figure

Figure ISP of the AT17LV512/010 in an AT94S FPSLIC Application
cSDA 1 cSCK 3
4 VCC
6 8 10

RESET

AT94S

RESET

SER_EN

DATA0 cSDA 1

CLK cSCK 1

M2 INIT RESET/OE 1

CON CE 1

SER_EN

Note Configurator signal names are shown in parenthesis.

Figure Serial Data Timing Diagram
t LOW
t HIGH
cSCK
t HD.STA
Ordering Information

Usable Gates

Speed Grade
5,000
25 MHz
10,000
25 MHz
40,000
16 MHz
Ordering Code AT94S05AL-25DGC AT94S05AL-25BQC AT94S05AL-25DGI AT94S05AL-25BQI AT94S10AL-25DGC AT94S10AL-25BQC AT94S10AL-25DGI AT94S10AL-25BQI

AT94S40AL-25DGC

AT94S40AL-25DGI

AT94S Secure Family

Package 256ZA 144L1 256ZA 144L1 256ZA 144L1 256ZA 144L1
256ZA
256ZA

Operation Range Commercial 0°C - 70°C Industrial
-40°C - 85°C Commercial 0°C - 70°C

Industrial -40°C - 85°C

Commercial 0°C - 70°C

Industrial -40°C - 85°C
256ZA 144L1

Package Type 256-ball, Chip Array Ball Grid Array Package CABGA 144-lead, Low Profile Plastic Gull Wing Quad Flat Package LQFP

Packaging Information
256ZA CABGA

A1 Ball Pad Corner

Top View

A1 Ball Pad Corner
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

Bottom View
256 SOLDER BALLS

Side View

SYMBOL D E A

A1 A2 A3

COMMON DIMENSIONS Unit of Measure = mm

NOM 17 BSC 17 BSC

BSC REF

NOTE

Notes This drawing is for general information only. Refer to JEDEC Drawing MO-205 for proper dimensions, tolerances, datums, etc. Array as seen from the bottom of the package.
2325 Orchard Parkway R San Jose, CA 95131

TITLE 256ZA, 256-ball 16 x 16 Array , 17 x 17 mm Body, Chip Array Ball Grid Array CABGA Package
11/07/01
256ZA
30 AT94S Secure Family
144L1 LQFP

AT94S Secure Family

Top View

A2 A1

Side View

Bottom View

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Datasheet ID: AT94S10AL-25DGC 519152