AT94K05AL-25AJI

AT94K05AL-25AJI Datasheet

AT94KAL Series Field Programmable System Level Integrated Circuit

Part	Datasheet
AT94K05AL-25AJI	AT94K05AL-25AJI (pdf)

Related Parts	Information
AT94K05AL-25AQU	AT94K05AL-25AQU
AT94K10AL-25DQI	AT94K10AL-25DQI
AT94K05AL-25AQI	AT94K05AL-25AQI
AT94K10AL-25DQC	AT94K10AL-25DQC
AT94K05AL-25BQU	AT94K05AL-25BQU
AT94K10AL-25BQI	AT94K10AL-25BQI
AT94K10AL-25BQC	AT94K10AL-25BQC
AT94K10AL-25BQU	AT94K10AL-25BQU
AT94K05AL-25AQC	AT94K05AL-25AQC
AT94K10AL-25DQU	AT94K10AL-25DQU
AT94K40AL-25BQU	AT94K40AL-25BQU
AT94K40AL-25DQU	AT94K40AL-25DQU
AT94K40AL-25BQC	AT94K40AL-25BQC
AT94K40AL-25DQC	AT94K40AL-25DQC
AT94K40AL-25BQI	AT94K40AL-25BQI
AT94K40AL-25DQI	AT94K40AL-25DQI
AT94K10AL-25AJI	AT94K10AL-25AJI
AT94K10AL-25AQC	AT94K10AL-25AQC
AT94K05AL-25AJC	AT94K05AL-25AJC
AT94K10AL-25AQI	AT94K10AL-25AQI
AT94K05AL-25DQI	AT94K05AL-25DQI
AT94K05AL-25DQC	AT94K05AL-25DQC
AT94K05AL-25BQI	AT94K05AL-25BQI
AT94K05AL-25BQC	AT94K05AL-25BQC
AT94K10AL-25AJC	AT94K10AL-25AJC

PDF Datasheet Preview
• Monolithic Field Programmable System Level Integrated Circuit FPSLIC AT40K SRAM-based FPGA with Embedded High-performance RISC Core, Extensive Data and Instruction SRAM and JTAG ICE • 5,000 to 40,000 Gates of Patented SRAM-based AT40K FPGA with FreeRAM 2 - Kbits of Distributed Single/Dual Port FPGA User SRAM High-performance DSP Optimized FPGA Core Cell Dynamically Reconfigurable In-System FPGA Configuration Access Available On-chip from AVR Microcontroller Core to Support Cache Designs Very Low Static and Dynamic Power Consumption Ideal for Portable and Handheld Applications • Patented AVR Enhanced RISC Architecture 120+ Powerful Instructions Most Single Clock Cycle Execution High-performance Hardware Multiplier for DSP-based Systems Approaching 1 MIPS per MHz Performance C Code Optimized Architecture with 32 x 8 General-purpose Internal Registers Low-power Idle, Power-save and Power-down Modes 100 µA Standby and Typical 2-3 mA per MHz Active • Up to 36 Kbytes of Dynamically Allocated Instruction and Data SRAM Up to 16 Kbytes x 16 Internal 15 ns Instructions SRAM Up to 16 Kbytes x 8 Internal 15 ns Data SRAM • JTAG IEEE std. Compliant Interface Extensive On-chip Debug Support Limited Boundary-scan Capabilities According to the JTAG Standard AVR Ports • AVR Fixed Peripherals Industry-standard 2-wire Serial Interface Two Programmable Serial UARTs Two 8-bit Timer/Counters with Separate Prescaler and PWM One 16-bit Timer/Counter with Separate Prescaler, Compare, Capture Modes and Dual 8-, 9- or 10-bit PWM • Support for FPGA Custom Peripherals AVR Peripheral Control 16 Decoded AVR Address Lines Directly Accessible to FPGA Macro Library of Custom Peripherals • 16 FPGA Supplied Internal Interrupts to AVR • Up to Four External Interrupts to AVR • 8 Global FPGA Clocks Two FPGA Clocks Driven from AVR Logic FPGA Global Clock Access Available from FPGA Core • Multiple Oscillator Circuits Programmable Watchdog Timer with On-chip Oscillator to AVR Internal Clock Circuit Software-selectable Clock Frequency Oscillator to Timer/Counter for Real-time Clock • VCC 3.0V - 3.6V • 3.3V 33 MHz PCI-compliant FPGA I/O 20 mA Sink/Source High-performance I/O Structures All FPGA I/O Individually Programmable • High-performance, Low-power CMOS Five-layer Metal Process • State-of-the-art Integrated PC-based Software Suite including Co-verification • 5V I/O Tolerant 5K - 40K Gates of AT40K FPGA with 8-bit Microcontroller, up to 36K Bytes of SRAM and On-chip JTAG ICE AT94KAL Series Field Programmable System Level Integrated Circuit The AT94KAL Series FPSLIC family shown in Table 1 is a combination of the popular Atmel AT40K Series SRAM FPGAs and the high-performance Atmel AVR 8-bit RISC microcontroller with standard peripherals. Extensive data and instruction SRAM as well as device control and management logic are included on this monolithic device, fabricated on Atmel’s fivelayer metal CMOS process. The AT40K FPGA core is a fully 3.3V PCI-compliant, SRAM-based FPGA with distributed 10 ns programmable synchronous/asynchronous, dual-port/single-port SRAM, 8 global clocks, Cache Logic ability partially or fully reconfigurable without loss of data and 5,000 to 40,000 usable gates. Table The AT94K Series Characteristics Device AT94K05AL FPGA Gates FPGA Core Cells FPGA SRAM Bits 2048 FPGA Registers Total Maximum FPGA User I/O AVR Programmable I/O Lines Program SRAM 4 Kbytes - 16 Kbytes Data SRAM 4 Kbytes - 16 Kbytes Hardware Multiplier 8-bit 2-wire Serial Interface UARTs Watchdog Timer Timer/Counters Real-time Clock JTAG ICE Yes 1 Typical AVR throughput Operating Voltage 2 25 MHz AL 19 MIPS - 3.6V 2 AT94K10AL 10K 576 4096 846 144 16 20 Kbytes - 32 Kbytes 4 Kbytes- 16 Kbytes 2 Yes Ordering Information Usable Gates Speed Grade 5,000 -25 MHz 10,000 -25 MHz 40,000 -25 MHz Ordering Code AT94K05AL-25AJC AT94K05AL-25AQC AT94K05AL-25BQC AT94K05AL-25DQC AT94K05AL-25AJI AT94K05AL-25AQI AT94K05AL-25BQI AT94K05AL-25DQI AT94K10AL-25AJC AT94K10AL-25AQC AT94K10AL-25BQC AT94K10AL-25DQC AT94K10AL-25AJI AT94K10AL-25AQI AT94K10AL-25BQI AT94K10AL-25DQI AT94K40AL-25BQC AT94K40AL-25DQC AT94K40AL-25BQI AT94K40AL-25DQI Package 84J 100A 144L1 208Q1 84J 100A 144L1 208Q1 84J 100A 144L1 208Q1 84J 100A 144L1 208Q1 144L1 208Q1 144L1 208Q1 Operation Range Commercial 0°C - 70°C Industrial -40°C - 85°C Commercial 0°C - 70°C Industrial -40°C - 85°C Commercial 0°C - 70°C Industrial -40°C - 85°C 84J 100A 144L1 208Q1 Package Type 84-lead, Plastic J-leaded Chip Carrier PLCC 100-lead, Thin mm Plastic Quad Flat Package TQFP 144-lead, Low Profile Plastic Gull Wing Quad Flat Package LQFP 208-lead, Plastic Gull Wing Quad Flat Package PQFP 184 AT94KAL Series FPSLIC Packaging Information 84J PLCC AT94KAL Series FPSLIC PIN NO. 1 IDENTIFIER e D1 D D2/E2 A2 A1 A 0.51 0.020 MAX 3X This package conforms to JEDEC reference MS-018, Variation AF. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is mm per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. Lead coplanarity is mm maximum. COMMON DIMENSIONS Unit of Measure = mm SYMBOL MIN NOM MAX NOTE Note 2 Note 2 D2/E2 TITLE 2325 Orchard Parkway 84J, 84-lead, Plastic J-leaded Chip Carrier PLCC R San Jose, CA 95131 10/04/01 100A TQFP

PDF Datasheet Preview

• Monolithic Field Programmable System Level Integrated Circuit FPSLIC AT40K SRAM-based FPGA with Embedded High-performance RISC Core, Extensive Data and Instruction SRAM and JTAG ICE
• 5,000 to 40,000 Gates of Patented SRAM-based AT40K FPGA with FreeRAM 2 - Kbits of Distributed Single/Dual Port FPGA User SRAM High-performance DSP Optimized FPGA Core Cell Dynamically Reconfigurable In-System FPGA Configuration Access Available On-chip from AVR Microcontroller Core to Support Cache Designs Very Low Static and Dynamic Power Consumption Ideal for Portable and Handheld Applications
• Patented AVR Enhanced RISC Architecture 120+ Powerful Instructions Most Single Clock Cycle Execution High-performance Hardware Multiplier for DSP-based Systems Approaching 1 MIPS per MHz Performance C Code Optimized Architecture with 32 x 8 General-purpose Internal Registers Low-power Idle, Power-save and Power-down Modes 100 µA Standby and Typical 2-3 mA per MHz Active
• Up to 36 Kbytes of Dynamically Allocated Instruction and Data SRAM Up to 16 Kbytes x 16 Internal 15 ns Instructions SRAM Up to 16 Kbytes x 8 Internal 15 ns Data SRAM
• JTAG IEEE std. Compliant Interface Extensive On-chip Debug Support Limited Boundary-scan Capabilities According to the JTAG Standard AVR Ports
• AVR Fixed Peripherals Industry-standard 2-wire Serial Interface Two Programmable Serial UARTs Two 8-bit Timer/Counters with Separate Prescaler and PWM One 16-bit Timer/Counter with Separate Prescaler, Compare, Capture Modes and Dual 8-, 9- or 10-bit PWM
• Support for FPGA Custom Peripherals AVR Peripheral Control 16 Decoded AVR Address Lines Directly Accessible to FPGA Macro Library of Custom Peripherals
• 16 FPGA Supplied Internal Interrupts to AVR
• Up to Four External Interrupts to AVR
• 8 Global FPGA Clocks

Two FPGA Clocks Driven from AVR Logic FPGA Global Clock Access Available from FPGA Core
• Multiple Oscillator Circuits Programmable Watchdog Timer with On-chip Oscillator to AVR Internal Clock Circuit Software-selectable Clock Frequency Oscillator to Timer/Counter for Real-time Clock
• VCC 3.0V - 3.6V
• 3.3V 33 MHz PCI-compliant FPGA I/O 20 mA Sink/Source High-performance I/O Structures All FPGA I/O Individually Programmable
• High-performance, Low-power CMOS Five-layer Metal Process
• State-of-the-art Integrated PC-based Software Suite including Co-verification
• 5V I/O Tolerant
5K - 40K Gates of AT40K FPGA with 8-bit Microcontroller, up to 36K Bytes of SRAM and On-chip JTAG ICE

AT94KAL Series Field Programmable System Level Integrated Circuit

The AT94KAL Series FPSLIC family shown in Table 1 is a combination of the popular Atmel AT40K Series SRAM FPGAs and the high-performance Atmel AVR 8-bit RISC microcontroller with standard peripherals. Extensive data and instruction SRAM as well as device control and management logic are included on this monolithic device, fabricated on Atmel’s fivelayer metal CMOS process.

The AT40K FPGA core is a fully 3.3V PCI-compliant, SRAM-based FPGA with distributed 10 ns programmable synchronous/asynchronous, dual-port/single-port SRAM, 8 global clocks, Cache Logic ability partially or fully reconfigurable without loss of data and 5,000 to 40,000 usable gates.

Table The AT94K Series Characteristics

Device

AT94K05AL

FPGA Gates

FPGA Core Cells

FPGA SRAM Bits
2048

FPGA Registers Total

Maximum FPGA User I/O

AVR Programmable I/O Lines

Program SRAM
4 Kbytes - 16 Kbytes

Data SRAM
4 Kbytes - 16 Kbytes

Hardware Multiplier 8-bit
2-wire Serial Interface

UARTs

Watchdog Timer

Timer/Counters

Real-time Clock JTAG ICE

Yes 1

Typical AVR throughput

Operating Voltage 2
25 MHz AL
19 MIPS - 3.6V 2

AT94K10AL 10K 576 4096 846 144 16
20 Kbytes - 32 Kbytes 4 Kbytes- 16 Kbytes
2 Yes
Ordering Information

Usable Gates

Speed Grade
5,000
-25 MHz
10,000
-25 MHz
40,000
-25 MHz
Ordering Code

AT94K05AL-25AJC AT94K05AL-25AQC AT94K05AL-25BQC AT94K05AL-25DQC

AT94K05AL-25AJI AT94K05AL-25AQI AT94K05AL-25BQI AT94K05AL-25DQI

AT94K10AL-25AJC AT94K10AL-25AQC AT94K10AL-25BQC AT94K10AL-25DQC

AT94K10AL-25AJI AT94K10AL-25AQI AT94K10AL-25BQI AT94K10AL-25DQI

AT94K40AL-25BQC AT94K40AL-25DQC

AT94K40AL-25BQI AT94K40AL-25DQI

Package
84J 100A 144L1 208Q1
84J 100A 144L1 208Q1
84J 100A 144L1 208Q1
84J 100A 144L1 208Q1
144L1 208Q1
144L1 208Q1

Operation Range Commercial 0°C - 70°C

Industrial -40°C - 85°C

Commercial 0°C - 70°C

Industrial -40°C - 85°C

Commercial 0°C - 70°C

Industrial -40°C - 85°C
84J 100A 144L1 208Q1

Package Type 84-lead, Plastic J-leaded Chip Carrier PLCC 100-lead, Thin mm Plastic Quad Flat Package TQFP 144-lead, Low Profile Plastic Gull Wing Quad Flat Package LQFP 208-lead, Plastic Gull Wing Quad Flat Package PQFP
184 AT94KAL Series FPSLIC

Packaging Information
84J PLCC

AT94KAL Series FPSLIC

PIN NO. 1 IDENTIFIER
e D1 D

D2/E2

A2 A1 A
0.51 0.020 MAX 3X

This package conforms to JEDEC reference MS-018, Variation AF. Dimensions D1 and E1 do not include mold protrusion.

Allowable protrusion is mm per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. Lead coplanarity is mm maximum.

COMMON DIMENSIONS Unit of Measure = mm

SYMBOL MIN NOM MAX NOTE

Note 2

Note 2

D2/E2

TITLE 2325 Orchard Parkway 84J, 84-lead, Plastic J-leaded Chip Carrier PLCC R San Jose, CA 95131
10/04/01
100A TQFP

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Datasheet ID: AT94K05AL-25AJI 519151